100LVELT22M - Fairchild Semiconductor

January 2003

Revised January 2003

100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator

100LVELT22

3.3V Dual LVTTL/LVCMOS to

Differential LVPECL Translator

General Description

The 100LVELT22 is a LVTTL/LVCMOS to differential

LV PECL translator o perating from a single +3.3V supply.

Both outputs of a differential pair should be terminated in

50Ω to VCC - 2.0V even if only one output is being used. If

an output pair is unused both outputs can be left open

(un-terminated).

The 100 series is temperature compensated.

Features

■Typical propagation delay of 350 ps

■<100 ps skew between outpu ts

■Max ICC of 28 mA at 25°C

■When TTL input is left Open Q output defaults HIGH

■Fairchild MSOP-8 package is a drop-in replacement to

ON TSSOP-8

■Flow through pinout

■Meets or exceeds JEDEC specification EIA/JESD78 IC

latch-up test

■Moisture Sensitivity Level 1

■ESD Perform ance:

Human Body Mod el > 2000V

Machine Model > 200V

Ordering Code:

Devices also available in Tape and R eel. Spe ci fy by append ing suffix lette r “X” to the ord ering co de.

Connection Diagram

Top View

Pin Descriptions

Logic Diagram

Order Number Product Package DescriptionPackage Code

Number Top Mark

100LVELT22M M08A KVT22 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

100LVELT22M8

(Preliminary) MA08D KR22 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide

Pin Name Description

Qn, QnLVPECL Diffe rential Outputs

D0, D1LVTTL/LVCMOS Inputs

VCC Positive Supply

GND Ground

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100LVELT22

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are th ose values be yond which

the saf ety of the device cannot be gu aranteed. Th e device shoul d not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Oper ating Co ndition s” table will def ine the condit ions

for actu al device operation.

LVPECL DC Electrical Characteristics VCC = 3.3V ; GND = 0.0V ( Note 2)

Note 2: Output parameters vary 1 to 1 with VCC. VCC can vary ±0.15V.

Note 3: Outputs ar e t erminat ed t hrough a 50Ω resistor to VCC − 2.0V.

Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than

500LFPM maintained.

LVTTL/LVCMOS DC Electrical Characteristics VCC = 3.3V; GND = 0.0V ( Note 4)

Note 4: VCC can vary ±0.15V.

Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than

500LFPM maintained.

AC Electrical Characteristics VCC = 3.3V; GND = 0. 0V (Note 5)

Note 5: VCC can vary ±0.15V.

Note 6: Specifications for standard LVTTL input signal (see Figure 1).

Supply Voltage (VCC) 0.0V to +7.0V

Input Voltage (VI) VI ≤ VCC 0.0V to +7.0V

DC Output Current (IOUT)

Continuous 50 mA

Surge 100 mA

Storage Temperature (TSTG)−65°C to +150°C

Power Supply Operating VCC = 3.0V to 3.8V

LVTTL/LVCMOS Input Voltage 0.0V to VCC

Free Air Operating Temperature (TA)−40°C to +85°C

Symbol Parameter −40°C 25°C 85°CUnits

Min Typ Max Min Typ Max Min Typ Max

ICC Power Supply Current 28 28 29 mA

VOH Output HIGH Voltage (Note 3) 2215 2420 2275 2420 2275 2420 mV

VOL Output LOW Voltage (Note 3) 1470 1745 1490 1680 1490 1680 mV

Symbol Parameter TA = −40°C t o 85 °CUnits Condition

Min Typ Max

IIH Input HIGH Current 20 µAVIN = 2.7V

100 VIN = VCC

IIL Input LOW Current −200 µAV

IN = 0.5V

VIK Clamp Diode Voltage −1.2 V IIN = −18 mA

VIH Input HIGH Voltage 2.0 V

VIL Input LOW Voltage 0.8 V

Symbol Parameter −40°C25°C85°CUnits Figure

Min Typ Max Min Typ Max Min Typ Max Number

fMAX Maximum Toggle Frequency TBD TBD TBD MHz

tJITTER Cycle-to-Cycle Jitter TBD TBD TBD ps

tPLH / tPHL Propagation Delay (Note 6) 200 350 600 200 350 600 200 350 600 ps Figure 1

tSKEW Skew Output-to-Output 30 100 30 100 30 100 ps

Part-to-Part 400 400 400

tr, tfOutput Rise Time Q (20% to 80%) 200 550 200 500 200 500 ns Figure 2

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100LVELT22

Switching Waveforms

FIGURE 1. LVTTL to Differential LVPECL Propagation Delay

FIGURE 2. Differential Output Edge Rates

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100LVELT22

Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M08A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

5 www.fairchildsemi.com

100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

8-Lead Mol ded Small Outline Package (MSOP), JEDEC MO-187, 3.0 mm Wide

Package Number MA08D

Fairchild does not assume an y res ponsibility fo r use of any circu itry descr ibed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.