W83176R-733 W83176G-733 Winbond Dual Bank DDR BUFFER For VIA CHIPSET Date: Mar/22/2006 Revision: 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET W83176R-733/W83176G-733 Data Sheet Revision History PAGES DATES VERSION WEB VERSION All of the versions before 0.50 are for internal use. 1 2 3 4 MAIN CONTENTS n.a. 09/09/03 0.5 n.a. First published preliminary version. 3,4,5,8 12/18/03 0.6 n.a. Correction IC version, correction description and default value 03/22/2006 1.0 1.0 Update on Web and add lead free part some 5 6 7 8 9 10 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -I- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET Table of Content1. GENERAL DESCRIPTION ......................................................................................................... 1 2. PRODUCT FEATURES .............................................................................................................. 1 3. PIN CONFIGURATION ............................................................................................................... 1 4. BLOCK DIAGRAM ...................................................................................................................... 2 5. PIN DESCRIPTION..................................................................................................................... 3 5.1 Clock Function Pins..................................................................................................................3 5.2 Control Signal Pins...................................................................................................................3 6. POWER PINS ............................................................................................................................. 4 7. I2C CONTROL AND STATUS REGISTERS .............................................................................. 4 8. 9. 7.1 Register 0 ~ Register 5 RESERVED.......................................................................................4 7.2 Register 6: Output Control (1 = Enable, 0 = Disable) (Default: FFh)......................................4 7.3 Register 7: Output Control (1 = Enable, 0 = Disable) (Default: FFh)......................................4 7.4 REGISTER 8 ~ Register 17 RESERVED ...............................................................................5 7.5 Skew step reference Table ......................................................................................................5 7.6 Register 18: Skew Control (Default: 88h)................................................................................5 7.7 Register 19: Skew Control (Default: 80h)................................................................................5 7.8 Slew rate reference table .........................................................................................................6 7.9 Register 20: Skew & Slew Rate Control (Default: 8Ah) ..........................................................6 7.10 Register 21: Slew Rate Control (Default: AAh) .......................................................................6 7.11 Register 22: Slew Rate Control (Default: AAh) .......................................................................6 7.12 Register 23: Slew Rate Control (Default: AAh) .......................................................................7 ACCESS INTERFACE ................................................................................................................ 8 8.1 Block Write Protocol .................................................................................................................8 8.2 Block Read Protocol.................................................................................................................8 8.3 Byte Write Protocol...................................................................................................................8 8.4 Byte Read Protocol ..................................................................................................................8 SPECIFICATIONS ...................................................................................................................... 9 9.1 ABSOLUTE MAXIMUM RATINGS .........................................................................................9 9.2 AC CHARACTERISTICS.........................................................................................................9 9.3 DC CHARACTERISTICS ........................................................................................................9 10. ORDERING INFORMATION..................................................................................................... 10 11. HOW TO READ THE TOP MARKING...................................................................................... 10 12. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 11 - II - W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 1. GENERAL DESCRIPTION The W83176R-733 is a 2.5V Dual Bank D.D.R. Clock buffer designed for VIA system. W83176R-733 can support 4 D.D.R. DRAM DIMMs. The W83176R-733 provides I2C serial bus interface to program the registers to enable or disable each clock outputs. The W83176R-733 accepts a reference clock as its input and runs on 2.5V supply. 2. PRODUCT FEATURES * * * * * Low Skew outputs (< 100ps) Two Feedback pins for synchronous for each bank. Supports up to 4 D.D.R. DIMMs Supports PC3200 D.D.R. SDRAM I2C 2-Wire serial interface and supports Byte or Block Date RW * 48-pin SSOP package 3. PIN CONFIGURATION V D D 2. 5 G ND FB _O U T B B U F_ IN B D D RB T 0 D D RB C 0 D D RB T 1 D D RB C 1 G ND V D D 2. 5 D DR AT0 D DR AC 0 D DR AT1 D DR AC 1 G ND V D D 2. 5 FB _O U T A BU F_I N A D DR AT2 D DR AC 2 D DR AT3 D DR AC 3 V D D 2. 5 G ND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 V D D 2 .5 G ND O E _O D D * O E _E V E N * D D R BT 2 D D R BC 2 D D R BT 3 D D R BC 3 G ND V D D 2 .5 D DR AT4 D DR AC 4 D DR AT5 D DR AC 5 G ND V D D 2 .5 D D R BT 4 D D R BC 4 D D R BT 5 D D R BC 5 V D D 2 .5 G ND S DATA * S CL K * *: Internal pull-up resistor 120K to VDD -1- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 4. BLOCK DIAGRAM FB_OUTA DDRAT[5:0] BUF_INA DDRAC[5:0] FB_OUTB BUF_INB SCLK* SDATA* OE_ODD* OE_EVEN* DDRBT[5:0] Control Logic DDRBC[5:0] -2- W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 5. PIN DESCRIPTION BUFFER TYPE SYMBOL IN Input OUT Output I/OD Bi-directional Pin, Open Drain * 5.1 DESCRIPTION Internal 120k pull-up Clock Function Pins PIN PIN NAME TYPE 18 BUF_INTA IN 36,35,38,37,2 DDRAT/C 1,22,20,19,14 [5:0] ,13,11,12 5.2 Bank A DDR Buffer clocks of differential pair outputs. Bank A DDR Buffer True Feedback output, dedicated for external feedback. FB_OUTA OUT 4 BUF_INTB IN 3 FB_OUTB Bank A DDR Buffer True reference clock input. OUT 17 30,29,32,31,42,4 DDRBT/C [5:0] 1,44,43,7,8,5,6 DESCRIPTION Bank B DDR Buffer True reference clock input. OUT Bank B DDR Buffer clocks of differential pair outputs. OUT Bank B DDR Buffer True Feedback output, dedicated for external feedback. Control Signal Pins PIN PIN NAME TYPE DESCRIPTION 2 Serial data of I C 2-wire control interface 26 SDATA * I/OD 25 SCLK * IN 45 OE_EVEN* IN OE_EVEN=1 Enable, OE_EVEN=0 Disable, Even Buffer clock output pairs (DDR0, 2,4), Internal pull-up resistor 120K to VDD2.5 46 OE_ODD* IN OE_ODD=1 Enable, OE_ODD=0 Disable, ODD Buffer clock output pairs (DDR1, 3, 5), Internal pull-up resistor 120K to VDD2.5 Internal pull-up resistor 120K to VDD2.5 Serial clock of I2C 2-wire control interface Internal pull-up resistor 120K to VDD2.5 -3- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 6. POWER PINS PIN PIN NAME 2,9,15,24,27,34,40,47 GND 1,10,16,23,28,33,39,48 VDD2.5 DESCRIPTION Ground Power Supply 2.5V 7. I2C CONTROL AND STATUS REGISTERS 7.1 Register 0 ~ Register 5 RESERVED 7.2 Register 6: Output Control (1 = Enable, 0 = Disable) (Default: FFh) BIT PIN NO PWD 7 Reserved 1 Reserved 6 17 1 FB_OUTA output control 5 36,35 1 DDRA_T5/C5 output control 4 38,37 1 DDRA_T4/C4 output control 3 21,22 1 DDRA_T3/C3 output control 2 20,19 1 DDRA_T2/C2 output control 1 13,14 1 DDRA_T1/C1 output control 0 11,12 1 DDRA_T0/C0 output control 7.3 DESCRIPTION Register 7: Output Control (1 = Enable, 0 = Disable) (Default: FFh) Bit Pin No PWD Description 7 Reserved 1 Reserved 6 3 1 FB_OUTB output control 5 30,29 1 DDRB_T5/C5 output control 4 32,31 1 DDRB_T4/C4 output control 3 42,41 1 DDRB_T3/C3 output control 2 44,43 1 DDRB_T2/C2 output control 1 7,8 1 DDRB_T1/C1 output control 0 5,6 1 DDRB_T0/C0 output control -4- W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 7.4 REGISTER 8 ~ Register 17 RESERVED 7.5 Skew step reference Table 7.6 BIT SKEW<2:0>/<1:0> DELAY TIME (PS) 000 0 001 250 010 500 011 750 100 1000 101 1250 110 1500 111 1750 Register 18: Skew Control (Default: 88h) NAME PWD DESCRIPTION 7 Reserved 1 Reserved 6 DDRA_TSKEW<2> 0 5 DDRA_TSKEW<1> 0 DDRA True clock outputs with FB_OUTA True clock SKEW control bits 4 DDRA_TSKEW<0> 0 3 Reserved 1 Reserved 2 DDRA_CSKEW<2> 0 1 DDRA_CSKEW<1> 0 DDRA Complementary clock outputs with FB_OUTA True clock SKEW control bits 0 DDRA_CSKEW<0> 0 7.7 BIT Register 19: Skew Control (Default: 80h) NAME PWD DESCRIPTION 7 Reserved 1 Reserved 6 DDRB_CSKEW<2> 0 5 DDRB_CSKEW<1> 0 DDRB Complementary clock outputs with FB_OUTB True clock SKEW control bits 4 DDRB_CSKEW<0> 0 3 FAOUT_SKEW<1> 0 2 FAOUT_SKEW<0> 0 1 FBOUT_SKEW<1> 0 0 FBOUT_SKEW<0> 0 FB_OUTA, DDRA clock outputs with BUF_INA clock SKEW control bits FB_OUTB, DDRB clock outputs with BUF_INB clock SKEW control bits -5- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 7.8 Slew rate reference table SR<1:0> STATUS 10/01 Normal (default) 11 Strong 00 Weak 7.9 BIT Register 20: Skew & Slew Rate Control (Default: 8Ah) NAME PWD DESCRIPTION 7 Reserved 1 Reserved 6 DDRB_TSKEW<2> 0 5 DDRB_TSKEW<1> 0 DDRB True clock outputs with FB_OUTB True clock SKEW control bits 4 DDRB_TSKEW<0> 0 3 DDRAT/C0_SR<1> 1 2 DDRAT/C0_SR<0> 0 1 DDRAT/C1_SR<1> 1 0 DDRAT/C1_SR<0> 0 DDRAT/C0 slew rate control bits DDRAT/C1 slew rate control bits 7.10 Register 21: Slew Rate Control (Default: AAh) BIT NAME PWD 7 DDRAT/C2_SR<1> 1 6 DDRAT/C2_SR<0> 0 5 DDRAT/C3_SR<1> 1 4 DDRAT/C3_SR<0> 0 3 DDRAT/C4_SR<1> 1 2 DDRAT/C4_SR<0> 0 1 DDRAT/C5_SR<1> 1 0 DDRAT/C5_SR<0> 0 DESCRIPTION DDRAT/C2 slew rate control bits DDRAT/C3 slew rate control bits DDRAT/C4 slew rate control bits DDRAT/C5 slew rate control bits 7.11 Register 22: Slew Rate Control (Default: AAh) BIT NAME PWD 7 DDRBT/C0_SR<1> 1 6 DDRBT/C0_SR<0> 0 5 DDRBT/C1_SR<1> 1 4 DDRBT/C1_SR<0> 0 DESCRIPTION DDRBT/C0 slew rate control bits DDRBT/C1 slew rate control bits -6- W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET Register 22: Slew Rate Control (Default: AAh), continued BIT NAME PWD 3 DDRBT/C2_SR<1> 1 2 DDRBT/C2_SR<0> 0 1 DDRBT/C3_SR<1> 1 0 DDRBT/C3_SR<0> 0 DESCRIPTION DDRBT/C2 slew rate control bits DDRBT/C3 slew rate control bits 7.12 Register 23: Slew Rate Control (Default: AAh) BIT NAME PWD 7 DDRBT/C4_SR<1> 1 6 DDRBT/C4_SR<0> 0 5 DDRBT/C5_SR<1> 1 4 DDRBT/C5_SR<0> 0 3 FBOUT_SR<1> 1 2 FBOUT_SR<0> 0 1 FAOUT_SR<1> 1 0 FAOUT_SR<0> 0 DESCRIPTION DDRBT/C4 slew rate control bits DDRBT/C5 slew rate control bits FB_OUTB slew rate control bits FB_OUTA slew rate control bits -7- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 8. ACCESS INTERFACE The W83176R-733 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83176R-733 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C write address is defined at 0xD4. The I2C read address is defined at 0xD5. 8.1 Block Write Protocol 8.2 Block Read Protocol ## In block mode, the command code must filled `00h' 8.3 Byte Write Protocol 8.4 Byte Read Protocol -8- W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD2.5). 9.2 PARAMETER RATING Voltage on any pin with respect to GND Storage Temperature - 0.5 V to + 3.6 V Ambient Temperature - 55C to + 125C Operating Temperature Input ESD protection (Human body model) 0C to + 70C 2000V - 65C to + 150C AC CHARACTERISTICS VDD2.5 = 2.5V 5 %, TA = 0C to +70C, Test load = 10 pF PARAMETER SYMBOL MIN Operating clock frequency Input Clock Duty Cycle Dynamic Supply Current Cycle to Cycle Jitter Output to Output Skew Output clock Rise time Output clock Fall time Output clock Duty Cycle Output differential-pair crossing voltage FIN Dtin Idd C-Cjitter Tskew Tor Tof Dtot 100 45 9.3 Voc TYP MAX UNITS 650 650 45 (Vdd/2) -0.2 MHz % mA ps ps ps ps % Vdd/ 2 200 55 200 200 100 950 950 55 (Vdd/2) + 0.2 MIN TYP MAX UNITS 1.0 Vdc V TEST CONDITIONS Fin=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz DC CHARACTERISTICS VDD2.5= 2.5V 5 %, TA = 0C to +70C PARAMETER SDATA, SCLK Input Low Voltage SDATA, SCLK Input High Voltage BUF_IN Input Voltage Low BUF_IN Input Voltage High Input Pin Capacitance Output Pin Capacitance Input Pin Inductance SYMBOL SVIL SVIH 2.2 Vdc VIL VIH CIN COUT LIN TEST CONDITIONS 0.4 Vdc Fin=100 to 200Mhz Fin=100 to 200Mhz 5 6 7 Vdc pF pF nH 2.1 -9- Publication Release Date: March, 2006 Revision 1.0 W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 10. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83176R-733 48 PIN SSOP Commercial, 0C to +70C W83176G-733 48 PIN SSOP(Lead free part) Commercial, 0C to +70C 11. HOW TO READ THE TOP MARKING W83176R-733 28051234 342GAASA W83176G-733 28051234 342GAASA 1st line: Winbond logo and the type number: Normal:W83176R-733, Lead free part: W83176G-733 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G E D SA 342: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision SA: Internal use code All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 10 - W83176R-733/W83176G-733 DUAL BANK DDR BUFFER FOR VIA CHIPSET 12. PACKAGE DRAWING AND DIMENSIONS .035 .045 0.40/0.50 DIA E END VIEW HE TOP VIEW SEE DETAIL "A" c D A2 A A1 e SIDE VIEW b c 0.13 D HE 18.2 18.42 18.54 910.16 10.31 10.41 E 7.42 0.51 7.52 0.64 7.59 0.76 0.61 0.81 1.40 1.02 PARTING LINE Y c DIMENSION IN INCH MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 A A1 A2 b e L L1 Y SEATING PLANE DIMENSION IN MM SYMBOL .045 .055 0 0.25 0.08 8 0.005 0.720 0.400 0.292 0.020 0.024 MAX. 0.110 0.016 0.092 0.0135 0.010 0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 0 8 L L1 DETAIL"A" Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 11 - Publication Release Date: March, 2006 Revision 1.0