841S104EGILF - Integrated Device Technology

DATA SHEET

Crystal-to-HCSL 100MHz

PCI ExpressTM Clock Synthesizer

ICS841S104I

General Description

The ICS841S104I is a PLL-based clock synthesizer specifically

designed for PCI_Express™ Clock applications. This device

generates a 100MHz differential HCSL clock from an input reference

of 25MHz. The input reference may be derived from an external

source or by the addition of a 25MHz crystal to the on-chip crystal

oscillator. An external reference is applied to the XTAL_IN pin with

the XTAL_OUT pin left floating.The device offers spread spectrum

clock output for reduced EMI applications. An I2C bus interface is

used to enable or disable spread spectrum operation as well as

select either a down spread value of -0.35% or -0.5%.The

ICS841S104I is available in a lead-free 24-Lead package.

Features

•Four 0.7V current mode differential HCSL output pairs

•Crystal oscillator interface: 25MHz

•Output frequency: 100MHz

•RMS phase jitter @ 100MHz (12kHz – 20MHz): 1.145ps (typical)

•Cycle-to-cycle jitter: 20ps (maximum)

•I2C support with readback capabilities up to 400kHz

•Spread Spectrum for electromagnetic interference (EMI) reduction

•3.3V operating supply mode

•-40°C to 85°C ambient operating temperature

•Available lead-free (RoHS 6) package

•PCI Express Gen 1, 2, 3 jitter compliant

HiPerClockS™

OSC PLL Divider

Network

I2C

Logic

SDATA

SCLK

IREF

Pullup

SRCT[1:4]

SRCC[1:4]

25MHz

XTAL_IN

XTAL_OUT

ICS841S104I

24-Lead TSSOP

4.4mm x 7.8mm x 0.925mm package body

G Package

Top View

SRCC1

SRCT1

SRCC2

SRCT2

SRCC3

SRCT3

IREF

SRCC4

SRCT4

SDATA

SCLK

XTAL_OUT

XTAL_IN

DDA

Pin Assignment

Block Diagram

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Table 1. Pin Descriptions

NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1, 2 SRCT3, SRCC3 Output Differential output pair. HCSL interface levels.

3, 9, 11, 13, 16 VSS Power Power supply ground.

4, 10, 17, 22 VDD Power Positive supply pins.

5, 6 SRCT2, SRCC2 Output Differential output pair. HCSL interface levels.

7, 8 SRCT1, SRCC1 Output Differential output pair. HCSL interface levels.

12 IREF Input

An external fixed precision resistor (475Ω) from this pin to ground provides a

reference current used for differential current-mode SRCCx, SRCTx clock

outputs.

14 VDDA Power Analog supply for PLL.

15 nc Unused No connect.

18,

XTAL_IN,

XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.

20 SCLK Input Pullup I2C compatible SCLK. This pin has an internal pullup resistor.

LVCMOS/LVTTL interface levels.

21 SDATA I/O Pullup I2C compatible SDATA. This pin has an internal pullup resistor. Open drain.

LVCMOS/LVTTL interface levels.

23, 24 SRCT4, SRCC4 Output Differential output pair. HCSL interface levels.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 2pF

RPULLUP Input Pullup Resistor 51 kΩ

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer, a

two-signal I2C serial interface is provided. Through the Serial Data

Interface, various device functions, such as clock output buffers, can

be individually enabled or disabled. The registers associated with the

serial interface initialize to their default settings upon power-up, and

therefore, use of this interface is optional. Clock device register

changes are normally made upon system initialization, if any are

required.

Data Protocol

The clock driver serial protocol accepts byte write, byte read, block

write and block read operations from the controller. For block

write/read operation, the bytes must be accessed in sequential order

from lowest to highest byte (most significant bit first) with the ability to

stop after any complete byte has been transferred. For byte write and

byte read operations, the system controller can access individually

indexed bytes. The offset of the indexed byte is encoded in the

command code, as described in Table 3A.

The block write and block read protocol is outlined in Table 3B, while

Table 3C outlines the corresponding byte write and byte read

protocol. The slave receiver address is 11010010 (D2h).

Table 3A.Command Code Definition

Bit Description

7 0 = Block read or block write operation, 1 = Byte read or byte write operation

6:5 Chip select address, set to “00” to access device.

4:0 Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Table 3B. Block Read and Block Write Protocol

Table 3C. Byte Read and Byte Write Protocol

Bit Description = Block Write Bit Description = Block Read

1Start 1Start

2:8 Slave address - 7 bits 2:8 Slave address - 7 bits

9Write 9Write

10 Acknowledge from slave 10 Acknowledge from slave

11:18 Command Code - 8 bits 11:18 Command Code - 8 bits

19 Acknowledge from slave 19 Acknowledge from slave

20:27 Byte Count - 8 bits 20 Repeat start

28 Acknowledge from slave 21:27 Slave address - 7 bits

29:36 Data byte 1 - 8 bits 28 Read = 1

37 Acknowledge from slave 29 Acknowledge from slave

38:45 Data byte 2 - 8 bits 30:37 Byte Count from slave - 8 bits

46 Acknowledge from slave 38 Acknowledge

Data Byte/Slave Acknowledges 39:46 Data Byte 1 from slave - 8 bits

Data Byte N - 8 bits 47 Acknowledge

Acknowledge from slave 48:55 Data Byte 2 from slave - 8 bits

Stop 56 Acknowledge

Data Bytes from Slave/Acknowledge

Data Byte N from slave - 8 bits

Not Acknowledge

Bit Description = Byte Write Bit Description = Byte Read

1 Start 1 Start

2:8 Slave address - 7 bits 2:8 Slave address - 7 bits

9 Write 9 Write

10 Acknowledge from slave 10 Acknowledge from slave

11:18 Command Code - 8 bits 11:18 Command Code - 8 bits

19 Acknowledge from slave 19 Acknowledge from slave

20:27 Data Byte- 8 bits 20 Repeat start

28 Acknowledge from slave 21:27 Slave address - 7 bits

29 Stop 28 Read

29 Acknowledge from slave

30:37 Data from slave - 8 bits

38 Not Acknowledge

39 Stop

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Control Registers

Table 3D. Byte 0: Control Register 0

NOTE: Pup denotes Power-up.

Table 3E. Byte 1: Control Register 1

Table 3F. Byte 2: Control Register 2

Table 3G. Byte 3:Control Register 3

Table 3H. Byte 4: Control Register 4

Table 3I. Byte 5: Control Register 5

Bit @Pup Name Description

7 0 Reserved Reserved

6 1 SRC[T/C]4

SRC[T/C]4 Output Enable

0 = Disable (Hi-Z)

1 = Enable

5 1 SRC[T/C]3

SRC[T/C]3 Output Enable

0 = Disable (Hi-Z)

1 = Enable

4 1 SRC[T/C]2

SRC[T/C]2 Output Enable

0 = Disable (Hi-Z)

1 = Enable

3 1 SRC[T/C]1

SRC[T/C]1 Output Enable

0 = Disable (Hi-Z)

1 = Enable

2 1 Reserved Reserved

1 0 Reserved Reserved

0 0 Reserved Reserved

Bit @Pup Name Description

7 0 Reserved Reserved

6 0 Reserved Reserved

5 0 Reserved Reserved

4 0 Reserved Reserved

3 0 Reserved Reserved

2 0 Reserved Reserved

1 0 Reserved Reserved

0 0 Reserved Reserved

Bit @Pup Name Description

7 1 SRCT/C Spread Spectrum Selection

0 = -0.35%, 1 = - 0.5%

6 1 Reserved Reserved

5 1 Reserved Reserved

4 0 Reserved Reserved

3 1 Reserved Reserved

20SRC

SRC Spread Spectrum

Enable

0 = Spread Off,

1 = Spread On

1 1 Reserved Reserved

0 0 Reserved Reserved

Bit @Pup Name Description

7 1 Reserved Reserved

6 0 Reserved Reserved

5 1 Reserved Reserved

4 0 Reserved Reserved

3 1 Reserved Reserved

2 1 Reserved Reserved

1 1 Reserved Reserved

0 1 Reserved Reserved

Bit @Pup Name Description

7 0 Reserved Reserved

6 0 Reserved Reserved

5 0 Reserved Reserved

4 0 Reserved Reserved

3 0 Reserved Reserved

2 0 Reserved Reserved

1 0 Reserved Reserved

0 1 Reserved Reserved

Bit @Pup Name Description

7 0 Reserved Reserved

6 0 Reserved Reserved

5 0 Reserved Reserved

4 0 Reserved Reserved

3 0 Reserved Reserved

2 0 Reserved Reserved

1 0 Reserved Reserved

0 0 Reserved Reserved

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Table 3J. Byte 6: Control Register 6

NOTE: Pup denotes Power-up.

Table 3K. Byte 7: Control Register 7

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C

Bit @Pup Name Description

7 0 TEST_SEL REF/N or Hi-Z Select

0 = Hi-Z, 1 = REF/N

6 0 TEST_MODE

TEST Clock

Mode Entry Control

0 = Normal Operation,

1 = REF/N or Hi-Z Mode

5 0 Reserved Reserved

4 1 Reserved Reserved

3 0 Reserved Reserved

2 0 Reserved Reserved

1 1 Reserved Reserved

0 1 Reserved Reserved

Bit @Pup Name Description

7 0 Revision Code Bit 3

6 0 Revision Code Bit 2

5 0 Revision Code Bit 1

4 0 Revision Code Bit 0

3 0 Vendor ID Bit 3

2 0 Vendor ID Bit 2

1 0 Vendor ID Bit 1

0 1 Vendor ID Bit 0

Item Rating

Supply Voltage, VDD 4.6V

Inputs, VI

XTAL_IN

Other Inputs

0V to VDD

-0.5V to VDD + 0.5V

Outputs, VO-0.5V to VDD + 0.5V

Package Thermal Impedance, θJA 77.5°C/W (0 mps)

Storage Temperature, TSTG -65°C to 150°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Positive Supply Voltage 3.135 3.3 3.465 V

VDDA Analog Supply Voltage VDD – 0.21 3.3 VDD V

IDD Power Supply Current 80 mA

IDDA Analog Supply Current 21 mA

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C

Table 5. Crystal Characteristics

NOTE: Characterized using an 18pF parallel resonant crystal.

AC Electrical Characteristics

Table 6A. PCI Express Jitter Specifications, VDD = 3.3V±5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.

NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1

is 86ps peak-to-peak for a sample size of 106 clock periods.

NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS

(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).

NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express

Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.

NOTE 4: This parameter is guaranteed by characterization. Not tested in production.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage 2.2 VDD + 0.3 V

VIL Input Low Voltage -0.3 0.8 V

IIH Input High Current SDATA, SCLK VDD = VIN = 3.465V 10 µA

IIL Input Low Current SDATA, SCLK VDD = 3.465V, VIN = 0V -150 µA

Parameter Test Conditions Minimum Typical Maximum Units

Mode of Oscillation Fundamental

Frequency 25 MHz

Equivalent Series Resistance (ESR) 50 Ω

Shunt Capacitance 7pF

Parameter Symbol Test Conditions Minimum Typical Maximum

PCIe Industry

Specification Units

(PCIe Gen 1)

Phase Jitter

Peak-to-Peak;

NOTE 1, 4

ƒ = 100MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

13.8 21 86 ps

tREFCLK_HF_RMS

(PCIe Gen 2)

Phase Jitter RMS;

NOTE 2, 4

ƒ = 100MHz, 25MHz Crystal Input

High Band: 1.5MHz - Nyquist

(clock frequency/2)

1.34 3.03 3.1 ps

tREFCLK_LF_RMS

(PCIe Gen 2)

Phase Jitter RMS;

NOTE 2, 4

ƒ = 100MHz, 25MHz Crystal Input

Low Band: 10kHz - 1.5MHz 0.18 0.3 3.0 ps

tREFCLK_RMS

(PCIe Gen 3)

Phase Jitter RMS;

NOTE 3, 4

ƒ = 100MHz, 25MHz Crystal Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

0.28 0.71 0.8 ps

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

AC Electrical Characteristics

Table 6B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: Characterized using a 25MHz quartz crystal.

NOTE 1: Refer to phase jitter plot.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross

points.

NOTE 4: Spread Spectrum clocking enabled.

NOTE 5: Measurement taken from differential waveform.

NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is

allowed to drop back into the VRB ±100mV differential range.

NOTE 7: Measurement taken from single-ended waveform.

NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.

NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.

NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of SRCT equals the falling edge of SRCC.

NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing

points for this measurement.

NOTE 12: Defined as the total variation of all crossing voltages of rising SRCT and falling SRCC, This is the maximum allowed variance in

Vcross for any particular system.

NOTE 13: Measured from -150mV to +150mV on the differential waveform (SRCT minus SRCC). The signal must be monotonic through the

measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 100 MHz

fREF Reference frequency 25 MHz

tjit(Ø) Phase Jitter, RMS (Random);

NOTE 1

25MHz crystal, ƒ = 100MHz,

Integration Range: 12kHz – 20MHz 1.145 ps

tsk(o) Output Skew; NOTE 2, 3 40 ps

tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 PLL Mode 20 ps

tLPLL Lock Time 50 ms

SSC Modulation Frequency;

NOTE 4 25MHz Crystal 30 32 33.33 kHz

SSCRED Spectral Reduction; NOTE 4 -7 -10 dB

VRB

Ring-back Voltage Margin;

NOTE 5, 6 -100 100 mV

VMAX

Absolute Max. Output Voltage;

NOTE 7, 8 1150 mV

VMIN

Absolute Min. Output Voltage;

NOTE 7, 9 -300 mV

VCROSS

Absolute Crossing Voltage;

NOTE 7, 10, 11 250 550 mV

∆VCROSS

Total Variation of VCROSS over

all edges; NOTE 7, 10, 12 140 mV

Rise/Fall Edge Rate;

NOTE 7, 13 Measured between 150mV to +150mV 0.6 4.0 V/ns

odc Output Duty Cycle 48 52 %

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Typical Phase Noise at 100MHz

Noise Power dBc

Offset Frequency (Hz)

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Parameter Measurement Information

3.3V HCSL Output Load AC Test Circuit

Cycle-to-Cycle Jitter

Single-ended Measurement Points for Absolute Cross

Point and Swing

3.3V HCSL Output Load AC Test Circuit

Output Skew

Single-ended Measurement Points for Delta Cross Point

475Ω

Measurement

Point

33Ω50Ω

50Ω

33Ω

Measurement

Point

49.9Ω

HCSL

GND

2pF

IREF

VDDA

VDD

3.3V±5%

SRCT[1:4]

➤

tcycle n tcycle n+1

tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

SRCC[1:4]

CROSS_MAX

= 550mV

CROSS_MIN

= 250mV

MAX

= 1.15V

MIN

= -0.30V

SRCC

SRCT

475Ω

50Ω

HCSL

GND

SCOPE

IREF

This load condition is used for IDD, tjit(cc), tjit(Ø), and tsk(o)

measurements.

3.3V±5%

VDDA

3.3V±5%

VDD

SRCCx

SRCTy

tsk(o)

CROSS_DELTA

= 140mV

SRCC

SRCT

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Parameter Measurement Information, continued

Differential Measurement Points for Ringback

Differential Measurement Points for Rise/Fall Edge Rate

Differential Measurement Points for Duty Cycle/Period

RMS Phase Jitter

TSTABLE

-150mV

= -100mV

= +100mV

+150mV

0.0V

TSTABLE

SRCT -

SRCC

-150mV

+150mV

0.0V

Fall Edge RateRise Edge Rate

SRCC -

SRCT

0.0V

Clock Period (Differential)

Positive Duty

Cycle (Differential)

Negative Duty

Cycle (Differential)

SRCT -

SRCC

Offset Frequency

f1f2

Phase Noise Plot

RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers

Noise Power

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Application Information

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The ICS841S104I provides

separate power supplies to isolate any high switching noise from the

outputs to the internal PLL. VDD and VDDA should be individually

connected to the power supply plane through vias, and 0.01µF

bypass capacitors should be used for each pin. Figure 1 illustrates

this for a generic VDD pin and also shows that VDDA requires that an

additional 10Ω resistor along with a 10µF bypass capacitor be

connected to the VDDA pin.

Figure 1. Power Supply Filtering

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pullups; additional resistance is not

required but can be added for additional protection. A 1kΩ resistor

can be used.

Outputs:

Differential Outputs

All unused differential outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

VDD

VDDA

3.3V

10Ω

10µF.01µF

.01µF

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Crystal Input Interface

The ICS841S104I has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in Figure

2 below were determined using a 25MHz, 18pF parallel resonant

crystal and were chosen to minimize the ppm error. The optimum C1

and C2 values can be slightly adjusted for different board layouts.

Figure 2. Crystal Input Interface

Overdriving the XTAL Interface

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A general interface diagram is

shown in Figure 3A. The XTAL_OUT pin can be left floating. The

maximum amplitude of the input signal should not exceed 2V and the

input edge rate can be as slow as 10ns. This configuration requires

that the output impedance of the driver (Ro) plus the series

resistance (Rs) equals the transmission line impedance. In addition,

matched termination at the crystal input will attenuate the signal in

half. This can be done in one of two ways. First, R1 and R2 in parallel

should equal the transmission line impedance. For most 50Ω

applications, R1 and R2 can be 100Ω. This can also be

accomplished by removing R1 and making R2 50Ω. By overdriving

the crystal oscillator, the device will be functional, but note, the device

performance is guaranteed by using a quartz crystal.

Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface

Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface

XTAL_IN

XTAL_OUT

18pF Parallel Crystal

15pF

22pF

100

RS 43

Ro ~ 7 Ohm

Driver_LVCMOS

Zo = 50 Ohm C1

0.1uF

3.3V

Cry stal Input Interface

XTA L _ I N

XTA L _ O U T

Cry stal Input Interface

XTAL_IN

XTAL_OUT

0.1uF

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

VCC=3.3V

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Recommended Termination

Figure 4A is the recommended termination for applications which

require the receiver and driver to be on a separate PCB. All traces

should be 50Ω impedance.

Figure 4A. Recommended Termination

Figure 4B is the recommended termination for applications which

require a point to point connection and contain the driver and receiver

on the same PCB. All traces should all be 50Ω impedance.

Figure 4B. Recommended Termination

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

PCI Express Application Note

PCI Express jitter analysis methodology models the system response

to reference clock jitter. The block diagram below shows the most

frequently used Common Clock Architecture in which a copy of the

reference clock is provided to both ends of the PCI Express Link.

In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs

are modeled as well as the phase interpolator in the receiver. These

transfer functions are called H1, H2, and H3 respectively. The overall

system transfer function at the receiver is:

The jitter spectrum seen by the receiver is the result of applying this

system transfer function to the clock spectrum X(s) and is:

In order to generate time domain jitter numbers, an inverse Fourier

Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].

PCI Express Common Clock Architecture

For PCI Express Gen 1, one transfer function is defined and the

evaluation is performed over the entire spectrum: DC to Nyquist (e.g

for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is

reported in peak-peak.

PCIe Gen 1 Magnitude of Transfer Function

For PCI Express Gen 2, two transfer functions are defined with 2

evaluation ranges and the final jitter number is reported in rms. The

two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz

(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the

individual transfer functions as well as the overall transfer function Ht.

PCIe Gen 2A Magnitude of Transfer Function

PCIe Gen 2B Magnitude of Transfer Function

For PCI Express Gen 3, one transfer function is defined and the

evaluation is performed over the entire spectrum. The transfer

function parameters are different from Gen 1 and the jitter result is

reported in RMS.

PCIe Gen 3 Magnitude of Transfer Function

For a more thorough overview of PCI Express jitter analysis

methodology, please refer to IDT Application Note PCI Express

Reference Clock Requirements.

Ht s() H3 s() H1 s() H2 s()–[]×=

Ys() Xs() H3 s()×H1 s() H2 s()–[]×=

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Schematic Layout

Figure 5 shows an example of ICS841S104I application schematic.

In this example, the device is operated at VDD = 3.3V. The 18pF

parallel resonant 25MHz crystal is used. The C1 =18pF and C2 =

33pF are recommended for frequency accuracy. For different board

layouts, the C1 and C2 may be slightly adjusted for optimizing

frequency accuracy. Two examples of HCSL termination are shown

in this schematic. The decoupling capacitors should be located as

close as possible to the power pin.

Figure 5. ICS841S104I Application Schematic.

(U1-17)(U1-4)

10uF

TL7

Zo = 50

SCL

R9 0

VDD

IREF

VDDA

SDA

R5 33

0.1uF

R11

33pF

SRCT1

TL6

Zo = 50

TL5

Zo = 50

SCLK

X125MHz

VDD

SRCC1

SRCT4

VDD=3.3V

VDD

(U1-10)

R7 33

Recommended for PCI

Express Point-to-Point

Connection

VDD

1213

24 SRCT3

SRCC3

VSS

VDD

SRCT2

SRCC2

SRCT1

SRCC1

VSS

VDD

VSS

IREFVSS

VDDA

VSS

VDD

XTAL_IN

XTAL_OUT

SCLK

SDATA

VDD

SRCT4

SRCC4

18pF

SRCC4

VDD

0.01u

R12

(U1-22)

VDD

SDATA

HCSL Termination

18pF

0.1uF

R13

475 Ohm

0.1uF

Recommended for PCI

Express Add-In Card

TL3

Zo = 50

0.1uF

R8 0

VDD

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Spread Spectrum

Spread-spectrum clocking is a frequency modulation technique for

EMI reduction. When spread-spectrum is enabled, a 32kHz triangle

waveform is used with 0.5% down-spread from the nominal 100MHz

clock frequency. An example of a triangle frequency modulation

profile is shown in Figure 6A below.

The ICS841S104I triangle modulation frequency deviation is 0.5%

down-spread from the nominal clock frequency. An example of the

amount of down spread relative to the nominal clock frequency can

be seen in the frequency domain, as shown in Figure 6B. The ratio of

this difference to the fundamental frequency is typically 0.5%. The

resulting spectral reduction will be greater than 7dB, as shown in

Figure 2B. It is important to note the ICS841S104I 7dB minimum

spectral reduction is the component-specific EMI reduction, and will

not necessarily be the same as the system EMI reduction.

Figure 6A. Triangle Frequency Modulation

Figure 6B. 100MHz Clock Output In Frequency Domain

(A) Spread-Spectrum OFF

(B) Spread-Spectrum ON

➤

1/fm0.5/fm

Fnom

(1 - δ) Fnom

∆ – 7dBm

δ = 0.25%

➔

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS841S104I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS841S104I is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

The maximum current at 85°C is as follows:

IDD_MAX = 77mA

IDDA_MAX = 20mA

• Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(77mA + 20mA) = 336.105mW

• Power (outputs)MAX = 44.5mW/Loaded Output pair

If all outputs are loaded, the total power is 4 * 44.5mW = 178mW

Total Power_MAX = 336.105mW + 178mW = 514.105mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 77.5°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.514W * 77.5°C/W = 124.8°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resistance θJA for 24 Lead TSSOP, Forced Convection

θJA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 77.5°C/W 73.2°C/W 71.0°C/W

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

3. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.

HCSL output driver circuit and termination are shown in Figure 7.

Figure 7. HCSL Driver Circuit and Termination

HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,

use the following equations which assume a 50Ω load to ground.

The highest power dissipation occurs when VDD_MAX.

Power = (VDD_MAX – VOUT) * IOUT

since VOUT – IOUT * RL

= (VDD_MAX – IOUT * RL) * IOUT

= (3.465V – 17mA * 50Ω) * 17mA

Total Power Dissipation per output pair = 44.5mW

OUT

50Ω

➤

OUT = 17mA

REF =

475

Ω

± 1%

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Reliability Information

Table 8. θJA vs. Air Flow Table for a 24 Lead TSSOP

Transistor Count

The transistor count for ICS841S104I is: 11,775

Package Outline and Package Dimensions

Package Outline - G Suffix for 24 Lead TSSOP Table 9. Package Dimensions

Reference Document: JEDEC Publication 95, MO-153

θJA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 77.5°C/W 73.2°C/W 71.0°C/W

All Dimensions in Millimeters

Symbol Minimum Maximum

N24

A1.20

A1 0.05 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D7.70 7.90

E6.40 Basic

E1 4.30 4.50

e0.65 Basic

L0.45 0.75

α0° 8°

aaa 0.10

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

Ordering Information

Table 10. Ordering Information

NOTE: Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Part/Order Number Marking Package Shipping Packaging Temperature

841S104EGILF ICS841S104EIL “Lead-Free” 24 Lead TSSOP Tube -40°C to 85°C

841S104EGILFT ICS841S104EIL “Lead-Free” 24 Lead TSSOP 2500 Tape & Reel -40°C to 85°C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without

additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support

devices or critical medical instruments.

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESSTM CLOCK SYNTHESIZER

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including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

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