LS193 National Semiconductor 54LS193/DM54LS193/DM74LS193 Synchronous 4-Bit Up/Down Binary Counters with Dual Clock General Description This circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change togeth- er when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally as- sociated with asynchronous (ripple-clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is held high. The counter is fully programmable; that is, aach output may be preset to either level by entering the desired data at the inputs while the load input is low. The output will change independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modify- ing the count length with the preset inputs. A clear input has been provided which, when taken to a high level, forces all outputs to the low level; independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements of clock drivers, tc., required for long words. These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up and down counting functions. The borrow output produces a pulse equal in width to the count down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count down input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count down and count up inputs respectively of the succeeding counter. Features @ Fully independent clear input m Synchronous operation m@ Cascading circuitry provided internally @ Individual preset each flip-flop @ Alternate Military/Aerospace device (54LS193) is avail- able, Contact a National Semiconductor Sales Office/ Distributor for specifications. Connection Diagram Dual-in-Line Package INPUTS OUTPUTS INPLTS -__ eor DATA DATA DATA Yoo =A ~~ CLEAR BORROW CARRY LOAD D Jie fis fra fits i241 tos [9 1 2 3 4 DATAB Qe COUNT COUNT QQ 5 6 7 Ip GND INPUT ~ DOWN UP OUTPUTS ee OUTPUTS INPUTS TL/F/6406-1 Order Number 54LS193DMQB, 54LS193FMQB, 54.S193LMQB, DM54LS193J, DM54LS193W, DM74LS193M or DM74LS193N See NS Package Number E20A, J16A, M16A, N16E or W16A 2-238Absolute Maximum Ratings (note) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Vv Input Voltage 7 Note: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaran- feed. The device should not be operated at these limits. The Parametric values defined in the Electrical Characteristics fable are not guaranteed at the absolute maximum ratings. The FRlecommended Operating Conditions table wil! define Operating Free Air Temperature Range DM54LS and 54LS DM74LS Storage Temperature Range ~55C to + 125C OC to + 70C 65 C to +150C Recommended Operating Conditions the conditions for actual device operation. Symbol Parameter DM54LS193 DM74LS193 Units Min Nom Max Min Nom Max Vec Supply Voltage 4.5 5 5.5 4.75 5 5.25 Vv ViH High Level Input Voltage 2 2 v VIL Low Level Input Voltage 0.7 0.8 Vv lou High Level Output Current 0.4 0.4 mA fot Low Level Output Current 4 8 mA tok Clock Frequency (Note 1) 25 25 MHz Clock Frequency (Note 2) 20 20 MHz tw Pulse Width of Any Input (Note 6) 20 20 ns tsy Data Setup Time (Note 6) 20 20 ns ty Data Hold Time (Note 6) 0 0) ns taeL Release Time (Note 6) 40 40 ns Ta Free Air Operating Temperatura 55 125 0 70 C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units (Note 3) vi Input Clamp Voltage Voc = Min, |) = -18mA 1.5 Vv Vou High Level Output Voc = Min, loy = Max DM54 2.5 3.4 Voltage Vit = Max, Vin = Min v ortag It IH DM74 2.7 3.4 VoL Low Level Output Voc = Min, lol = Max DM54 0.25 0.4 Voltage Vit = Max, Viy = Min DM74 0.35 0.5 Vv lol = 4mMA, Veo = Min DM74 0.25 0.4 4 Input Current @ Max Voc = Max, V; = 7V 0.1 mA Input Voltage he High Levei Input Current Voc = Max, V) = 2.7V 20 pA tie Low Level Input Current Voc = Max, V; = 0.4V 0.4 mA los Short Circuit Veco = Max DM54 20 100 mA Output Current {Note 4) DM74 20 ~100 loc Supply Current Voc = Max (Note 5) 19 34 mA Note 1:C, = 15 pF, AL = 2 kf, la = 25C and Voo = 5N, Note 2:0, = 50 pF,RL = 2k, 1, = 25C and Voo = 5V. Note 3: All typicais are at Vong. = 5V, Ta = 25C. Note 4: Not more than one Gutput should be shorted at a time, and the duration should not exceed one second. Note : loc is measured with all outputs open, CLEAR and LOAD inputs grounded, and al! other inputs at 4.5V, Note 6 Ta = 25C and Voc = SV. 2-239 61S1LS193 Switching Characteristics a Voc = 5V and Ta = 25C (See Section 1 for Test Waveforms and Output Load) R, = 2k0 From (Input) Symbol Parameter To (Output) CL = 15 pF C. = 50 pF Units Min Max Min Max fax Maximum Clock Frequency 25 20 MHz tpLy Propagation Delay Time Count Up 26 30 ns Low to High Level Output to Carry {PHL Propagation Delay Time Count Up 24 36 ns High to Low Level Output to Carry fPLH Propagation Delay Time Count Down 24 29 ns Low to High Level Output to Borrow teHL Propagation Delay Time Count Down 24 a2 ns High to Low Level Output to Borrow tpLy Propagation Delay Time Either Count 38 45 ns Low to High Level Output to Any Q tPHL Propagation Delay Time Either Count 47 54 ns High to Low Level Output to Any Q teLH Propagation Delay Time Load to 40 At ns Low to High Level Output Any Q tPHL Propagation Delay Time Load to 40 47 ns High to Low Level Output Any @ tPHL Propagation Delay Time Clear to 35 44 ns High to Low Level Output AnyQ 2-240Logic Diagram (13) Borrow OUTPUT (12) carry OUTPUT paTA (15 INPUT A DOWN (4 COUNT (3) OUTPUT Q, up (5) COUNT oata (1) INPUT B 2 ( ) ouput Qy pata (10) INPUT C 6 ( ) output Q% pata (9) INPUT D 14 curar $ ) OUTPUT Q, "W LOAD TL/F/64062 2-241 61S1LS193 Timing Diagrams CLEAR ry Typical Clear, Load, and Count Sequences LOAD LI | aj DATA c_] o_| poedeedhaee COUNT UP COUNT DOWN Q, OUTPUTS LU LI _.-LL_ J LF LSJ 1 LSJ LJ 1 LL. | CARRY LU BORROW lel CLEAR bs] GVYr t4 15 0 { 2 1 0 15 14 13 COUNT UP + COUNT DOWN TL/F/6406-3 PRESET Note A: Clear overrides load, data, and count inputs. Note B: When counting up, count-down input must be high; when counting down, count-up input must be high. 2-242