8752 www.icst.com REV. A FEBRUARY 20, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PRELIMINARY
BLOCK DIAGRAM PIN ASSIGNMENT
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB1
QB0
VDDO
VDDO
QA3
QA2
GND
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
REF_CLK1
GND
FB_IN
VDDO
QA1
QA0
GND
REF_CLK2
VDDI
VDDA
CLK_SEL
VDDO
QB2
QB3
GND
GND
nc
PLL_SEL
VDDI
ICS8752
32-Lead LQFP
Y package
Top View
÷2
÷4
÷6
÷8
÷12
PLL
PHASE
DETECTOR
PLL_SEL
FB_IN
REF_CLK1
REF_CLK2
REF_SEL
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
MR/nOE
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
0
11
0
00
01
10
11
00
01
10
11
VCO
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
GENERAL DESCRIPTION
The ICS8752 is a low voltage, low skew clock
generator and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. With output frequencies up to 250MHz
the ICS8752 is targeted for high performance
clock applications. Along with a fully integrated PLL the
ICS8752 contains frequency configurable outputs and an
external feedback input for regenerating clocks with “zero de-
lay”.
Dual clock inputs, REF_CLK1 and REF_CLK2, support
redundant clock applications. The CLK_SEL input determines
which reference clock is used. The output divider values of
Bank A and B are controlled by the DIV_SELA0:1, and
DIV_SELB0:1, respectively.
For test and system debug purposes the PLL_SEL input
allows the PLL to be bypassed. When HIGH the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The effec-
tive fanout of each output can be doubled by utilizing the
ability of each output to drive two series terminated trans-
mission lines.
FEATURES
•Fully integrated PLL
•8 L VCMOS outputs, 7Ω typical output impedance
•External feedback for ”zero delay” clock regeneration
•Output frequency up to 250MHz
•Dual L VCMOS clock inputs for redundant clock applications
•L VCMOS control inputs
•Bank skew, tsk(b), 350ps
•Output skew , tsk(o), 450ps
•Multiple-frequency skew , tsk(w), 550ps
•Cycle-to-cycle jitter , tjit(cc), ±100ps, typical
•PLL reference zero delay , t(Ø), ±100ps
•Full 3.3V
•32 lead low-profile QFP(LQFP)
•7mm x 7mm x 1.4mm package body , 0.8mm lead pitch
•0°C to 70°C ambient operating temperature
•Functionally compatible with the MPC952 in some applications
•Industrial temperature versions available upon request
HiPerClockS™
,&6
8752 www.icst.com REV. A FEBRUARY 20, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
2,1 ,0BLES_VID 1BLES_VID tupnInwodlluP .3elbaTnidebircsedsaBknabrofseulavredividtuptuosenimreteD .slevelecafretniLTTVL/SOMCVL
4,3 ,0ALES_VID 1ALES_VID tupnInwodlluP .3elbaTnidebircsedsaAknabrofseulavredividtuptuosenimreteD .slevelecafretniLTTVL/SOMCVL
5EOn/RMtupnInwodlluP .stuptuoehtfoetatsenimreteddnasredividsteseR .slevelecafretniLTTVL/SOMCVL
61KLC_FERtupnInwodlluP.slevelecafretniSOMCVL.tupnikcolcecnerefeR
31,7 ,42,71 92,82 DNGrewoP.dnuorgottcennoC.nipdnuorG
8NI_BFtupnInwodlluP ."yaledorez"htiwskcolcgnitarenegerrofrotcetedesahpottupnikcabdeeF .slevelecafretniLTTVL/SOMCVL
9LES_FERtupnInwodlluP .ecnereferrotcetedesahpsa2KLC_FERro1KLC_FERneewtebstceleS .2KLC_FERstcelesHGIHnehW.1KLC_FERstcelesWOLnehW .slevelecafretniLTTVL/SOMCVL
01ADDVrewoP.V3.3ottcennoC.nipylppusrewopLLP
23,11IDDVrewoP.V3.3ottcennoC.nipylppusrewoperocdnatupnI
212KLC_FERtupnInwodlluP.slevelecafretniSOMCVL.tupnikcolcecnerefeR
,51,41 91,81 ,1AQ,0AQ 3AQ,2AQ tuptuO .stuptuokcolcAknaB7Ω.ecnadepmituptuolacipyt
.slevelecafretniSOMCVL
,02,61 52,12 ODDVrewoP.V3.3ottcennoC.snipylppusrewoptuptuO
,32,22 72,62 ,1BQ,0BQ 3BQ,2BQ tuptuO .stuptuokcolcBknaB7Ω.ecnadepmituptuolacipyt
.slevelecafretniSOMCVL
03cndesunU.nipdesunU
13LES_LLPtupnIpulluP ehtottupniehtsakcolcecnereferehtdnaLLPehtneewtebstceleS .kcolcecnereferstcelesWOLnehW.LLPtcelesHGIHnehW.sredivid .slevelecafretniLTTVL/SOMCVL
23IDDVrewoP.V3.3ottcennoC.nipylppusrewoptupnI
8752 www.icst.com REV. A FEBRUARY 20, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PRELIMINARY
TABLE 2. PIN CHARACTERISTICS
TABLE 3. CONTROL INPUTS FUNCTION TABLE
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
NIC tupnI ecnaticapaC
,1KLC_FER 2KLC_FER DBTFp
,LES_LLP ,NI_BF LES_FER ,1ALES_VID ,0ALES_VID ,1BLES_VID 0BLES_VID
DBTFp
PULLUPR tupnI rotsiseRpulluP 15KΩ
NWODLLUPR tupnI nwodlluP rotsiseR 15KΩ
DPC noitapissiDrewoP ecnaticapaC )tuptuorep( V74.3=ODDV,IDDV,ADDVDBTFp
TUOR tuptuO ecnadepmI 7Ω
STUPNISTUPTUO
LES_LLPLES_FER1ALES_VID0ALES_VID1BLES_VID0BLES_VIDxAQxBQ
XX X X X X Z-iHZ-iH
1X 0 0 0 0 2/OCVf4/OCVf
1X 0 1 0 1 4/OCVf6/OCVf
1X 1 0 1 0 6/OCVf8/OCVf
1X 1 1 1 1 8/OCVf21/OCVf
00 0 0 0 0 2/1KLC_FERf4/1KLC_FERf
00 0 1 0 1 4/1KLC_FERf6/1KLC_FERf
00 1 0 1 0 6/1KLC_FERf8/1KLC_FERf
00 1 1 1 1 8/1KLC_FERf21/1KLC_FERf
01 0 0 0 0 2/2KLC_FERf4/2KLC_FERf
01 0 1 0 1 4/2KLC_FERf6/2KLC_FERf
01 1 0 1 0 6/2KLC_FERf8/2KLC_FERf
01 1 1 1 1 8/2KLC_FERf21/2KLC_FERf
.delbasiderastupuollaHGIHsiEOn/RMnehW.WOLsiEOn/RMnoitarepolamronroF:ETON
8752 www.icst.com REV. A FEBRUARY 20, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PRELIMINARY
TABLE 4A. QA OUTPUT FREQUENCY W/FB_IN = QB
STUPNITUPTUO
NI_BF1BLES_VID0BLES_VID
BQ TUPUO REDIVID EDOM
,1KLC_FER 2KLC_FER )zHM( 1ALES_VID0ALES_VID
AQ TUPUO REDIVID EDOM
AQ reilpitluM )1ETON(
NIMXAM
BQ0 0 ÷45.26521
00
÷22
01
÷41
10
÷6766.0
11
÷85.0
BQ0 1÷676.1433.38
00
÷23
01
÷45.1
10
÷61
11
÷857.0
BQ1 0÷852.135.26
00
÷24
01
÷42
10
÷633.1
11
÷81
BQ1 1
÷21 38.0276.14
01
÷26
01
÷43
10
÷62
11
÷85.1
.zHM005otzHM052siegnarycneuqerfOCV:1ETON:1ETON ;reilpitlumehtsemitycneuqerfkcolcecnereferotlauqeycneuqerftuptuoAQ:2ETON .kcolcecnereferotlauqeycneuqerftuptuoBQ
8752 www.icst.com REV. A FEBRUARY 20, 2001
5
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PRELIMINARY
TABLE 4B. QB OUTPUT FREQUENCY W/FB_IN = QA
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDI=VDDA=3.3V±5%, TA=0°C TO 70°C
STUPNITUPTUO
NI_BF1ALES_VID0ALES_VID
AQ TUPUO REDIVID EDOM
,1KLC_FER 2KLC_FER )zHM( 1BLES_VID0BLES_VID
BQ TUPUO REDIVID EDOM
BQ reilpitluM )2ETON(
NIMXAM
AQ0 0÷2521052
00
÷45.0
01
÷6333.0
10
÷852.0
11
÷21 380.0
AQ0 1÷45.26521
00
÷41
01
÷6766.0
10
÷85.0
11
÷21 333.0
AQ1 0÷676.1433.38
00
÷45.1
01
÷61
10
÷857.0
11
÷21 5.0
AQ1 1÷852.135.26
01
÷42
01
÷6333.1
10
÷81
11
÷21 766.0
.zHM005otzHM052siegnarycneuqerfOCV:1ETON ;reilpitlumehtsemitycneuqerfkcolcecnereferotlauqeycneuqerftuptuoBQ:2ETON .kcolcecnereferotlauqeycneuqerftuptuoAQ
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
FERfycneuqerFecnerefeRtupnI02052zHM
RtemiTesiRtupnIstniop%08ot%02taderusaeMDBTsn
FtemiTllaFtupnItniop%08ot%02taderusaeMDBTsn
CDtelcyCytuDecnerefeRtupnIDBTDBT%
8752 www.icst.com REV. A FEBRUARY 20, 2001
6
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PRELIMINARY
TABLE 6B. LVCMOS/LVTTL DC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V±5%, TA=0°C TO 70°C
TABLE 6A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V±5%, TA=0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
IDDVegatloVylppuSrewoPtupnI 531.33.3564.3V
ADDVegatloVylppuSrewoPgolanA 531.33.3564.3V
ODDVegatloVylppuSrewoPtuptuO 531.33.3564.3V
DDItnerruCylppuSrewoPtupnI Am
ABSOLUTE MAXIMUM RATINGS
Supply V oltage 4.6V
Inputs -0.5V to VDD+0.5 V
Outputs -0.5V to VDD+0.5V
Ambient Operating Temperature 0°C to 70°C
Storage T emperature -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any conditions beyond those listed in the
DC Character-
istics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
HIVegatloVhgiHtupnI 2KLC_FER,1KLC_FER NI_BF 2567.3V
,LES_FER,LES_LLP ,0ALES_VID,1ALES_VID ,0BLES_VID,1BLES_VID EOn/RM
LIVegatloVwoLtupnI 2KLC_FER,1KLC_FER NI_BF 3.0-8.0V
,LES_FER,LES_LLP ,0ALES_VID,1ALES_VID ,0BLES_VID,1BLES_VID EOn/RM
HIItnerruChgiHtupnI
2KLC_FER,1KLC_FER ,LES_FER,NI_BF ,0ALES_VID,1ALES_VID ,0BLES_VID,1BLES_VID EOn/RM
V564.3=NIV051Aµ
LES_LLPV564.3=NIV5Aµ
LIItnerruCwoLtupnI
2KLC_FER,1KLC_FER ,LES_FER,NI_BF ,0ALES_VID,1ALES_VID ,0BLES_VID,1BLES_VID EOn/RM
V0=NIV5-Aµ
LES_LLPV0=NIV051-Aµ
HOVegatloVhgiHtuptuO V531.3=ODDV Am63-=HOI 6.2V
LOVegatloVwoLtuptuO V531.3-ODDV Am63=LOI 5.0V
8752 www.icst.com REV. A FEBRUARY 20, 2001
7
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PRELIMINARY
TABLE 7. AC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V±5%, TA=0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
XAMfycneuqerFtuptuOmumixaM 052zHM
HLpthgiH-ot-woL,yaleDnoitagaporP ,V0=LES_LLPzHM0 ≤f≤zHM052 DBTDBTsn
LHptwoL-ot-hgiH,yaleDnoitagaporP ,V0=LES_LLPzHM0 ≤f≤zHM052 DBTDBTsn
)Ø(t ;yaleDoreZecnerefeRLLP 2ETON ,DBT=FERf,V3.3=LES_LLP DBT=OCVf 001-DBT001sp
)b(kst3ETON;wekSknaB taegdegnisirnoderusaeM 2/ODDV 053sp
)o(kst4ETON;wekStuptuO taegdegnisirnoderusaeM 2/ODDV 054sp
(kstw) ;wekSycneuqerFelpitluM 5ETON taegdegnisirnoderusaeM 2/ODDV 055sp
)cc(tijtrettiJelcyC-ot-elcyC taegdegnisirnoderusaeM 2/ODDV 001±sp
LtemiTkcoLLLP DBT
RtemiTesiRtuptuODBTDBTsp
FtemiTllaFtuptuODBTDBTsp
WPthtdiWesluPtuptuO zHM0 ≤f≤zHM052 2/ELCYCt DBT- 2/ELCYCt 2/ELCYCt DBT+ sn
zHM052=fDBT80.2DBTsn
NEtemiTelbanEtuptuO DBTsn
SIDtemiTelbasiDtuptuO DBTsn
05htiwdetanimretstuptuollA.esiwrehtodetonsselnuXAMftaderusaemsretemarapllA:1ETON Ω.2/ODDVot langistupnikcabdeefdegarevaehtdnakcolcecnerefertupniehtneewtebecnereffidemitehtsadenifeD:2ETON .elbatssiycneuqerfecnerefertupniehtdnadekcolsiLLPehtnehw .snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofoknabanihtiwwekssadenifeD:3ETON .snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofosknabssorcawekssadenifeD:4ETON segatlovylppusemasehthtiwycneuqerftnereffidtagnitarepostuptuofosknabssorcawekssadenifeD:5ETON .snoitidnocdaollauqedna tnecajdafoelpmasmodnararevo,selcyctnecajdaneewteblangisafoemitelcycninoitairavehtsadenifeD:6ETON .selcycfosriap
8752 www.icst.com REV. A FEBRUARY 20, 2001
8
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PRELIMINARY
PACKAGE OUTLINE - Y SUFFIX
EE1
D1
D
ccc C
SEATING
PLANE
D2
-C-
E2
e
A
N
A1
A2
bc
L
θ
916
1
2
3
817
24
32 25
TABLE 8. PACKAGE DIMENSIONS
NOITAIRAVCEDEJ SRETEMILLIMNISNOISNEMIDLLA
LOBMYS ABB
MUMINIMLANIMONMUMIXAM
N23
A06.1
1A 50.051.0
2A 53.104.154.1
b03.073.054.0
c90.002.0
DCISAB00.9
1D CISAB00.7
2D 06.5
ECISAB00.9
1E CISAB00.7
2E 06.5
eCISAB08.0
L54.006.057.0
q
0
°
7
°
ccc 01.0
Reference Document: JEDEC Publication 95, MS-026
8752 www.icst.com REV. A FEBRUARY 20, 2001
9
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PRELIMINARY
TABLE 9. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
Y2578SCIY2578SCIPFQLdaeL23yartrep052C°07otC°0
TY2578SCIY2578SCIleeRdnaepaTnoPFQLdaeL230002C°07otC°0
