OCTOBER 2008
DSC-3104/06
1
©2005 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆32K x 32 memory configuration
◆◆
◆◆
◆Supports high-performance system speed:
Commercial and Industrial:
— 5ns Clock-to-Data Access (100MHz)
— 6ns Clock-to-Data Access (83MHz)
— 7ns Clock-to-Data Access (66MHz)
◆◆
◆◆
◆Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC32K32D7LG-XX)
◆◆
◆◆
◆LBO input selects interleaved or linear burst mode
◆◆
◆◆
◆Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆Operates with a single 3.3V power supply (+10/-5%)
◆◆
◆◆
◆Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
Description
The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM
organized as 32K x 32 with full support of the Pentium™ and PowerPC™
Pin Description Summary
CacheRAM is a trademark of Integrated Device Technology.
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
32K x 32 CacheRAM™
3.3V Synchronous SRAM
Burst Counter
Single Cycle Deselect
IDT71V432
processor interfaces. The pipelined burst architecture provides cost-
effective 3-1-1-1 secondary cache performance for processors up to
100 MHz.
The IDT71V432 CacheRAM contains write, data, address, and
control registers. Internal logic allows the CacheRAM to generate a self-
timed write based upon a decision which can be left until the extreme end
of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V432 can provide four cycles of data for
a single address presented to the CacheRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses will be defined by the internal burst counter
and the LBO input pin.
The IDT71V432 CacheRAM utilizes IDT's high-performance, high-
volume 3.3V CMOS process, and is packaged in a JEDEC Standard
14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board
density in both desktop and notebook applications.
A0–A14 Address Inputs Input Synchronous
CE Chip Enable I nput Sync hronous
CS0, CS1Chips Selects Input Synchronous
OE Output Enable Input Asyn chronous
GW Global Write Enable Input Synchronous
BWE B y te Write Enable I nput Sync hronous
BW1, BW2, BW3, BW4Ind iv idual Byte Write Selects Input Synchronous
CLK Clock Input N/A
ADV Burst A ddress Adv ance I nput Sync hronous
ADSC Address St at us (Cache C ontroller) I nput Sync hronous
ADSP A ddress St atus (Pro cessor) I nput Sync hronous
LBO Linear / Interleaved Burst Order Input DC
ZZ Sleep Mode Input Asynchronous
I/O0–I/O31 Data Input/ Output I/O Synchronous
VDD 3.3V Pow er Pow er DC
VSS Ground Ground DC
3104 tbl 01
6.42
2
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Sym bol Pi n Fun ction I /O Active Descri pti on
A
0
–A
14
Address Inputs I N/A Synchronous Address inputs. The address re gister is triggered by a combination
of the rising edge of CLK and ADSC Lo w o r ADSP Lo w and CE Low.
ADSC Address Status
(Cac he Controller) I LOW Sync h ronous A ddre ss S tatus from Cac h e Controller. ADSC is an ac tiv e LOW
input that is used to load the add ress registers with new addresses. ADSC is
NOT GA TE D b y CE.
ADSP Address Status
(Processor) I LOW Synchronous Ad dress Status from Processor. ADSP is an activ e LOW i np ut that is
used to load the address registers with new addresses. ADSP is gate d by CE.
ADV Burst Address Advance I LOW Synchro nous Address Advance . ADV is an acti ve LOW i np ut that is use d to
ad vanc e the inte rnal burs t co unte r, contro lling b urs t ac ce s s afte r the initial
address is loaded. When this input is HIGH the burst counter is not incremented;
that is, there is no add re ss advance.
BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW
1
–BW
4
. If BWE is
LOW at the rising edge of CLK then BW
X
inputs are passed to the next stage in
the circuit. A byte write can still be blocked if ADSP is LOW at the rising ed ge of
CLK . If ADSP is HIGH and BW
X
is LOW at the rising edge of CLK then data will
b e written to the SRAM. If BWE is HIGH then the byte write inputs are blocked
and o nly GW can initiate a write cycle.
BW
1
- BW
4
In d iv i d ual B y te
Wri te E na b l e s I LOW Synchro nou s byte write e nab les. BW
1
co ntro ls I/O(7:0), BW
2
co ntro ls I/O(15 :8),
etc. Any active byte write causes all outputs to be disabled. ADSP LOW
disables all byte writes. BW
1
–BW
4
must meet specified setup and hold times
with re s p e ct to C LK .
CE Chip Enab le I LOW Sy nc hro nous chi p e nab le . CE is used with CS
0
and CS
1
to e nab le the
IDT71V432. CE als o g ate s ADSP.
CLK C lo ck I N/ A This i s th e cl o c k in p ut to the ID T7 1V4 32. A ll ti mi ng re ference s fo r th e d e v i c e are
m ade wi th re s p ec t to thi s i np u t.
CS
0
Chip Select 0 I HIGH Synchronous active HIGH chip select. CS
0
is used with CE and CS
1
to en abl e
the chip .
CS
1
Chip Se le ct 1 I LOW Sync hro no us act iv e LOW c hip s ele c t. CS
1
is use d with CE and CS
0
to enabl e
the chip .
GW Glo b al Write Enab le I LOW Sy nc hro no us g lo b al write e nab le . This inp ut will wri te a ll fo ur 8-b it d ata b yte s
when LOW on the rising edge of CLK. GW supercedes individual byte write
enables.
I/O
0
–I/O
31
Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data o utput
path are registered and triggered by the rising edg e of CLK.
LBO Li nea r Burs t Ord er I LOW As ync hro no us b urs t o rd e r s e lec tio n DC inp ut. When LBO i s HIG H th e Interl e av e d
(Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst
seq ue nce is s ele cted . LBO is a static DC inp ut and mus t no t chang e state while
the device is o perating.
OE Outp ut Enab le I LOW As ync hro no us o utput e nab le . Whe n OE is LOW the data output drivers are
enabled on the I/O pins. OE is gated internally b y a d e lay c ircuit driv en b y CE,
CS
0
, and CS
1
. In dual-bank mode, when the user is utilizing two banks of
IDT71V432 and tog g ling b ack and fo rth be twe en the m us ing CE, the in te rn al
de lay circuit delays the OE activation of the data o utput drivers by one cycle to
prevent bus contention between the banks. When used in single bank mode CE,
CS
0
, and CS
1
are all tie d ac ti ve and there is no outp ut e nab le d elay. Whe n OE is
HIGH the I/ O p ins are in a hig h-imp e de nce state .
V
DD
Power Supply N/A N/A 3.3V power supply inputs.
V
SS
Gro und N/A N/A Gro und p ins .
ZZ Sleep Mode I HIGH Asynchronous sleep mode inp ut. ZZ HIGH will g ate the CLK internally and po wer
d o wn the IDT71V432 to its l owe st p o we r c ons umptio n le ve l. Data re te ntio n is
guaranteed in Sleep Mode.
3104 tbl 02
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Functional Block Diagram
A
0
–A
14
ADDRESS
REGISTER
CLR
A
1
*
A
0
*15
2
15
A
2
–A
14
32K x 32
BIT
MEMORY
ARRAY
INTERNAL
ADDRESS
A
0
,A
1
BW
4
BW
3
BW
2
BW
1
Byte 1
Write Register
32 32
ADSP
ADV
CLK
ADSC
CS
0
CS
1
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
8
8
8
8
GW
CE
BWE
L
B
O
I/O
0
–I/O
31
OE
DATA INPUT
REGISTER
32
OUTPUT
BUFFER
OUTPUT
REGISTER
Powerdown
ZZ
DQ
DQ
Enable
Register
Enable
Delay
Register
Burst
Sequence
CE
CLK EN
CLK EN
2
Burst
Logic
Binary
Counter
3104 drw 01
.
15
6.42
4
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 6 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
3104 tbl 06
Absolute Maximum Ratings(1)
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD and Input terminals only.
3. I/O terminals.
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
Symbol Rating Value Unit
V
TERM
(2)
Term inal Volt age w it h
Respect to GND –0.5 to +4.6 V
V
TERM
(3)
Term inal Volt age w it h
Respect to GND –0.5 to V
DD
+0.5 V
T
A
Operating Tem perature 0 to +70
o
C
T
BIAS
Tem perat ure Under Bias –55 to +125
o
C
T
STG
St orage Tem perat ure –55 t o +125
o
C
P
T
Pow er Dissipation 1.0 W
I
OUT
DC Output Current 50 m A
3104 tbl 05
Recommended DC Operating
Conditions
NOTES:
1. VIL (min) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
DD
Sup ply Vol tag e 3.135 3.3 3.63 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage — Inputs 2.0 — 4.6
(2)
V
V
IH
Input High Voltage — I/O 2.0 — V
DD
+0.3 V
V
IL
Inpu t Lo w Vo l tage – 0. 5
(1)
—0.8V
3104 tb l 04
Recommended Operating
Temperature and Supply Voltage
Grade Temperature V
SS
V
DD
Com m ercial 0° C to +70° C 0V 3.3V+ 10/-5%
Industrial –40°C to +85° C 0V 3.3V+10/-5%
3104 tbl 03
6.42
5
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration
Top View TQFP
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
NC
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
I/O
31
I/O
30
V
DD
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DD
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DD
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DD
I/O
17
I/O
16
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O
14
V
DD
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DD
I/O
9
I/O
8
V
SS
NC
V
DD
ZZ
(2)
I/O
7
I/O
6
V
DD
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DD
I/O
1
I/O
0
NC
PK100-1
3104 drw 0
2
V
DD/NC
(1)
I/O
15
NC
NOTES:
1. Pin 14 can either be directly connected to VDD or not connected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,2)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2 . ZZ = LOW for this table.
3. OE is an asynchronous input.
Operation Address
Used CE CS
0
CS
1
ADSP ADSC ADV GW BWE BW
X
OE
(3)
CLK I/O
Deselected Cycle, Power Down None H X X X L X X X X X ↑Hi-Z
Deselected Cycle, Power Down NoneLXHLXXXXXX↑Hi-Z
Deselected Cycle, Power Down NoneL LX LXXXXXX↑Hi-Z
Deselected Cycle, Power Down None L X H X L X X X X X ↑Hi-Z
Deselected Cycle, Power Down None L L X X L X X X X X ↑Hi-Z
Read Cycle, Begin Burst ExternalLHL LXXXXX L↑D
OUT
Read Cycle, Begin Burst ExternalLHL LXXXXXH↑Hi-Z
Read Cycle, Begin Burst External L H L H L X H H X L ↑D
OUT
Read Cycle, Begin Burst External L H L H L X H L H L ↑D
OUT
Read Cycle, Begin Burst External L H L H L X H L H H ↑Hi-Z
Write Cycle, Begin Burst External L H L H L X H L L X ↑D
IN
Write Cycle, Begin Burst External L H L H L X L X X X ↑D
IN
Re ad Cycl e, Co ntinue Burst Ne xt X X X H H L H H X L ↑D
OUT
Re ad Cycl e, Co ntinue Burst Ne xt X X X H H L H H X H ↑Hi-Z
Re ad Cycl e, Co ntinue Burst Ne xt X X X H H L H X H L ↑D
OUT
Re ad Cycl e, Co ntinue Burst Ne xt X X X H H L H X H H ↑Hi-Z
Re ad Cycl e, Co ntinue Burst Ne xt H X X X H L H H X L ↑D
OUT
Re ad Cycl e, Co ntinue Burst Ne xt H X X X H L H H X H ↑Hi-Z
Re ad Cycl e, Co ntinue Burst Ne xt H X X X H L H X H L ↑D
OUT
Re ad Cycl e, Co ntinue Burst Ne xt H X X X H L H X H H ↑Hi-Z
Wri te Cyc le , Co ntinue Burst Ne xt X X X H H L H L L X ↑D
IN
Wri te Cyc le , Co ntinue Burst Ne xt X X X H H L L X X X ↑D
IN
Wri te Cyc le , Co ntinue Burst Ne xt H X X X H L H L L X ↑D
IN
Wri te Cyc le , Co ntinue Burst Ne xt H X X X H L L X X X ↑D
IN
Read Cycle, Suspend Burst CurrentXXX HHHHHXL↑D
OUT
Read Cycle, Suspend Burst CurrentXXX HHHHHXH↑Hi-Z
Read Cycle, Suspend Burst CurrentXXX HHHHXHL ↑D
OUT
Read Cycle, Suspend Burst CurrentXXX HHHHXHH↑Hi-Z
Read Cycle, Suspend Burst CurrentHXXX HHHHXL↑D
OUT
Read Cycle, Suspend Burst CurrentHXXX HHHHXH↑Hi-Z
Read Cycle, Suspend Burst Current H X X X H H H X H L ↑D
OUT
Read Cycle, Suspend Burst Current H X X X H H H X H H ↑Hi-Z
Write Cycle, Suspend Burst CurrentXX XHHHHLL X↑D
IN
Write Cycle, Suspend Burst Current X X X H H H L X X X ↑D
IN
Write Cycle, Suspend Burst Current H X X X H H H L L X ↑D
IN
Write Cycle, Suspend Burst Current H X X X H H L X X X ↑D
IN
3104 t bl 07
6.42
7
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Operation
(2)
OE ZZ I/O Status Power
Read L L Data Out (I/O
0
- I/O
31
)Active
Read H L High-Z Active
Write X L High-Z — Data In (I/O
0
- I/O
31
)Active
Deselected X L High-Z Standby
Sleep X H High-Z Sleep
3104 tbl 09
Operation GW BWE BW
1
BW
2
BW
3
BW
4
Read HHXXXX
Read HLHHHH
Write all Bytes LXXXXX
Write all Bytes HLLLLL
Write B y t e 1
(2)
HLLHHH
Write B y t e 2
(2)
HLHLHH
Write B y t e 3
(2)
HLHHLH
Write B y t e 4
(2)
HLHHHL
3104 tbl 08
Linear Burst Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table (LBO=VDD)
Asynchronous Truth Table(1)
Synchronous Write Function Truth Table(1)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11 10 01 00
3104 tbl 10
Sequence 1 S equence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11 00 01 10
3104 tbl 11
6.42
8
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
+1.5V
50Ω
I/O Z
0
=50Ω
3104drw 03
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(1) (VDD = 3.3V +10/-5%, VHD = VDD–0.2V, VLD = 0.2V)
Figure 3. Lumped Capacitive Load, Typical Derating
* Including scope and jig capacitance.
Figure 2. AC Test Load
(for tOHZ, tCHZ, tOLZ, and tDC1)
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
AC Test Loads
1
2
3
4
20 30 50 100 200
∆t
CD
(Typical, ns)
Capacitance (pF)
80
5
6
3104 drw 0
5
351Ω
+3.3V
317Ω
5pF*
I
/O
3104 drw 04
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| I nput L eakage Current V
DD
= M ax., V
IN
=
0V to V
DD
—5µA
|I
LI
| ZZ and LBO Input Leakage Current
(1)
V
DD
= M ax., V
IN
=
0V to V
DD
—30µA
|I
LO|
O ut put Leakage Current CE > V
IH
or OE > V
IH
, V
OUT
= 0V to V
DD
, V
DD
= Max. —5µA
V
OL
O ut put Low Voltage (I / O
1
–I/O
31
)I
OL
= 5m A, V
DD
= Min. — 0.4 V
V
OH
O utput H igh Volt age (I/O
1
–I/O
31
)I
OH
= –5m A, V
DD
= M in. 2.4 — V
3104 tbl 12
IDT71V432S5 IDT71V432S6 IDT71V432S7
Symbol Parameter Test Conditions Com'l. Ind. Com' l. Ind. Com'l. Ind. Uni
t
I
DD
Op era t ing P ow er Su pply Current Dev ice Sele cted, Ou tput s O pen, V
DD
= M ax.,
V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
200 200 180 180 160 160 mA
I
SB
St andby Power Supply Current Device Deselect ed, Outputs Open, V
DD
= M ax.,
V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
65 65 60 60 55 55 mA
I
SB1
Full Standby Pow er Supply Curren t Dev ice Deselect ed, Outputs Open, V
DD
= M ax.,
V
IN
> V
HD
or < V
LD
, f = 0
(2)
15 15 15 15 15 15 mA
I
ZZ
Full Sleep M ode Pow er Supply Current ZZ > V
HD
, V
DD
= M ax. 10 10 10 10 10 10 m A
3104 tbl 13
Figure 1. AC Test Load
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Tim ing Reference Levels
Output Tim ing Ref erence Levels
AC Test Load
0 to 3.0V
2ns
1.5V
1.5V
See Figures 1 and 2
3104 tbl 14
6.42
9
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Symbol Parameter
71V432S5 71V432S6 71V432S7
Unit
Min. Max. Min. Max. Min. Max.
CLO CK PARAMETERS
t
CYC
Clock Cy cle Tim e 10
____
12
____
15
____
ns
t
CH
(1) Clock High Pulse Width 4
____
4.5
____
5
____
ns
t
CL
(1) Clock Low Pulse Width 4
____
4.5
____
5
____
ns
OUTPUT PARAMETERS
t
CD
Clock High to Valid Data
____
5
____
6
____
7ns
t
CDC
Clock High to D ata Change 1.5
____
2
____
2
____
ns
t
CLZ
(2) Clo ck High to Output Active 0
____
0
____
0
____
ns
t
CHZ
(2) C lock High to Data High-Z 1.5 5 2 5 2 6 ns
t
OE
Ou tput Enable Access Tim e
____
5
____
5
____
6ns
t
OLZ
(2) Out put E nable Low to Data Active 0
____
0
____
0
____
ns
t
OHZ
(2) Out put En able High t o Data High-Z
____
4
____
5
____
6ns
SETUP TIMES
t
SA
Address Setup Tim e 2.5
____
2.5
____
2.5
____
ns
t
SS
Ad dress S tat us S etup Tim e 2. 5
____
2.5
____
2.5
____
ns
t
SD
Data in Set up Time 2.5
____
2.5
____
2.5
____
ns
t
SW
Write Set up Time 2.5
____
2.5
____
2.5
____
ns
t
SAV
Addr ess Adv ance Setup Tim e 2.5
____
2.5
____
2.5
____
ns
t
SC
Chip E nable/ Select Set up Tim e 2. 5
____
2.5
____
2.5
____
ns
HOLD TIMES
t
HA
Address Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HS
A ddress S tat us H old Tim e 0. 5
____
0.5
____
0.5
____
ns
t
HD
Data In Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HW
Write H old Tim e 0. 5
____
0.5
____
0.5
____
ns
t
HAV
Add ress A dv ance H old Tim e 0. 5
____
0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.5
____
0.5
____
0.5
____
ns
SLEEP MODE AND CONFIGU RATION PARAMETERS
t
ZZPW
ZZ Pulse Width 100 — 100
____
100
____
ns
t
ZZR
(3) ZZ Recov ery Tim e 100 — 100
____
100
____
ns
t
CFG
(4) C onfiguration Set-up Time 40 — 50
____
50
____
ns
3104 tbl 15
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
AC Electrical Characteristics
(VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
6.42
10
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Pipelined Read Cycle(1,2)
NOTES:
1 . O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base
address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don’t Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
t
CHZ
t
SA
t
SC
t
HS
GW,BWE,BWx
t
SW
t
CL
t
SAV
t
HW
t
HAV
CLK
ADSP
ADSC
(1)
ADDRESS
t
CYC
t
CH
t
HA
t
HC
t
OE
t
OHZ
OEt
CD
t
OLZ
O1(Ax)
DATA
OUT
t
CDC
O1(Ay)O3(Ay)O2(Ay)
O2(Ay)
t
CLZ
ADV
ADVinsertsawait-state
CE,CS
1
(Note3)
3104drw06
Pipelined
ReadBurstPipelinedRead
Output
Disabled
AxAy
t
SS
O1(Ay)
(Burstwrapsaround
toitsinitialstate)
O4(Ay)
6.42
11
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don’t Care for this cycle.
3 . O1(Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay. O1(Az) represents the first output from the external addresss Az; O2(Az)
represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
CLK
ADSP
ADDRESS
GW
ADV
OE
DATA
OUT
t
CYC
t
CH
t
CL
t
HA
t
SW
t
HW
t
CLZ
AxAyAz
t
HS
I1(Ay)
t
SD
t
HD
t
OLZ
t
CD
t
CDC
DATA
IN
(2)
t
OE
O1(Az)
O1(Az)
3104drw07
SingleReadPipelinedBurstRead
Pipelined
Write
O1(Ax)
t
OHZ
t
SS
t
SA
O3(Az)
O2(Az)
6.42
12
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
ADDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAyAz
ADV
DATA
OUT
OE
t
HC
t
SD
I1(Ax)I1(Az)
I2(Ay)
tHD
t
OHZ
DATA
IN
t
HAV
O3(Aw)O4(Aw)
CE,CS
1
GWt
SW
(Note3)
I2(Az)
BurstWrite
BurstRead
3104drw08
BurstWrite
Single
Write
I3(Az)
I4(Ay)
I3(Ay)
I2(Ay)
t
SAV
(ADVsuspendsburst)
I1(Ay)
BWEisignoredwhenADSPinitiatesburs
t
t
SC
.
t
HW
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)
NOTES:
1. ZZ input is LOW, BWE is HIGH, and LBO is Don’t Care for this cycle.
2 . O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
13
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 — Byte Controlled(1,2,3)
NOTES:
1. ZZ input is LOW, GW is HIGH, and LBO is Don’t Care for this cycle.
2 . O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address
Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
ADDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAy
BWx
ADV
DATA
OUT
OE
t
HC
t
SD
Single
WriteBurstWrite
I1(Ax)I2(Ay)I2(Ay)
(ADVsuspendsburst)
I2(Az)
tHD
Burst
ReadExtended
BurstWrite
t
OHZ
DATA
IN
t
SAV
t
SW
O4(Aw)
CE,CS
1
BWEt
SW
(Note3)
I1(Az)
Az
I4(Ay)
I1(Ay)
3104drw09
I4(Ay)
I3(Ay)
t
SC
BWEisignoredwhenADSPinitiatesburs
t
BWxisignoredwhenADSPinitiatesburs
t
I3(Az)
O3(Aw)
t
HW
t
HW
6.42
14
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
NOTES:
1. Device must power up in deselected Mode.
2. LBO input is Don’t Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
t
CYC
t
SS
t
CL
t
CH
t
HA
t
SA
t
SC
t
HC
t
OE
t
OLZ
t
HS
CLK
ADSP
ADSC
ADDRESS
GW
CE,CS
1
ADV
DATA
OUT
OE
ZZ
SingleReadSnoozeMode
t
ZZPW
3104drw10
O1(Ax)
Ax
(Note4)
t
ZZR
Az
6.42
15
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
CLK
A
DSP or ADSC
ADDRESS
DATA
OUT
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
3104 drw 1
1
Non-Burst Read Cycle Timing Waveform(1,2,3,4)
NOTES:
1. ZZ, CE, CS1, and OE are LOW for this cycle.
2. ADV, GW, BWE, BWx, and CS0 are HIGH for this cycle.
3. (Ax) represents the data for address Ax, etc.
4. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
CLK
ADSP
GW or
BWE and BWx
ADDRESS
ADSC
DATA
IN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
3104 drw 1
2
Non-Burst Write Cycle Timing Waveform(1,2,3,4)
NOTES:
1. ZZ, CE and CS1 are LOW for this cycle.
2. ADV, OE and CS0 are HIGH for this cycle.
3. (AX) represents the data for address AX, etc.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
16
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
100-pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline
6.42
17
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Ordering Information
Plastic Thin Quad Flatpack, 100 pin (PK100-1)
S
Power X
Speed PF
Package
PF
71V432
5
6
7Speed in nanoseconds
3104 drw 13
Device
Type
PART NUMBER SPEED IN MEGAHERTZ t
CD
PARAMETER CLOCK CYCLE TIME
71V432S5PF
71V432S6PF
71V432S7PF
100 MHz
83 MHz
66 MHz
5ns
6ns
7ns
10 ns
12 ns
15 ns
X
Process/
Temperature
Range
Blank
ICommercial (0°Cto+70°C)
Industrial (–40°Cto+85°C)
GRestricted hazardous substance device
X
6.42
18
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Datasheet Document History
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
9/10/99 Updated to new format
Pg. 3–5 Adjusted page layout, added extra page
Pg. 5 Added notes to pin configuration
Pg. 11–14 Revised notes
Pg. 17 Added Datasheet Document History
03/09/00 Pg. 1, 4, 8, 9, 16 Added Industrial temperature range offerings
04/04/00 Pg. 16 Added 100pinTQFP package Diagram Outline
08/09/00 Not recommended for new designs
08/17/01 Removed “Not recommended for new designs” from the background on the datasheet
03/31/05 Pg.17 Added “Restricted hazardous substance device” to ordering information.
10/18/08 Pg.17 Removed "IDT" from orderable part number
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
