6.42
2
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Sym bol Pi n Fun ction I /O Active Descri pti on
A
0
–A
14
Address Inputs I N/A Synchronous Address inputs. The address re gister is triggered by a combination
of the rising edge of CLK and ADSC Lo w o r ADSP Lo w and CE Low.
ADSC Address Status
(Cac he Controller) I LOW Sync h ronous A ddre ss S tatus from Cac h e Controller. ADSC is an ac tiv e LOW
input that is used to load the add ress registers with new addresses. ADSC is
NOT GA TE D b y CE.
ADSP Address Status
(Processor) I LOW Synchronous Ad dress Status from Processor. ADSP is an activ e LOW i np ut that is
used to load the address registers with new addresses. ADSP is gate d by CE.
ADV Burst Address Advance I LOW Synchro nous Address Advance . ADV is an acti ve LOW i np ut that is use d to
ad vanc e the inte rnal burs t co unte r, contro lling b urs t ac ce s s afte r the initial
address is loaded. When this input is HIGH the burst counter is not incremented;
that is, there is no add re ss advance.
BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW
1
–BW
4
. If BWE is
LOW at the rising edge of CLK then BW
X
inputs are passed to the next stage in
the circuit. A byte write can still be blocked if ADSP is LOW at the rising ed ge of
CLK . If ADSP is HIGH and BW
X
is LOW at the rising edge of CLK then data will
b e written to the SRAM. If BWE is HIGH then the byte write inputs are blocked
and o nly GW can initiate a write cycle.
BW
1
- BW
4
In d iv i d ual B y te
Wri te E na b l e s I LOW Synchro nou s byte write e nab les. BW
1
co ntro ls I/O(7:0), BW
2
co ntro ls I/O(15 :8),
etc. Any active byte write causes all outputs to be disabled. ADSP LOW
disables all byte writes. BW
1
–BW
4
must meet specified setup and hold times
with re s p e ct to C LK .
CE Chip Enab le I LOW Sy nc hro nous chi p e nab le . CE is used with CS
0
and CS
1
to e nab le the
IDT71V432. CE als o g ate s ADSP.
CLK C lo ck I N/ A This i s th e cl o c k in p ut to the ID T7 1V4 32. A ll ti mi ng re ference s fo r th e d e v i c e are
m ade wi th re s p ec t to thi s i np u t.
CS
0
Chip Select 0 I HIGH Synchronous active HIGH chip select. CS
0
is used with CE and CS
1
to en abl e
the chip .
CS
1
Chip Se le ct 1 I LOW Sync hro no us act iv e LOW c hip s ele c t. CS
1
is use d with CE and CS
0
to enabl e
the chip .
GW Glo b al Write Enab le I LOW Sy nc hro no us g lo b al write e nab le . This inp ut will wri te a ll fo ur 8-b it d ata b yte s
when LOW on the rising edge of CLK. GW supercedes individual byte write
enables.
I/O
0
–I/O
31
Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data o utput
path are registered and triggered by the rising edg e of CLK.
LBO Li nea r Burs t Ord er I LOW As ync hro no us b urs t o rd e r s e lec tio n DC inp ut. When LBO i s HIG H th e Interl e av e d
(Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst
seq ue nce is s ele cted . LBO is a static DC inp ut and mus t no t chang e state while
the device is o perating.
OE Outp ut Enab le I LOW As ync hro no us o utput e nab le . Whe n OE is LOW the data output drivers are
enabled on the I/O pins. OE is gated internally b y a d e lay c ircuit driv en b y CE,
CS
0
, and CS
1
. In dual-bank mode, when the user is utilizing two banks of
IDT71V432 and tog g ling b ack and fo rth be twe en the m us ing CE, the in te rn al
de lay circuit delays the OE activation of the data o utput drivers by one cycle to
prevent bus contention between the banks. When used in single bank mode CE,
CS
0
, and CS
1
are all tie d ac ti ve and there is no outp ut e nab le d elay. Whe n OE is
HIGH the I/ O p ins are in a hig h-imp e de nce state .
V
DD
Power Supply N/A N/A 3.3V power supply inputs.
V
SS
Gro und N/A N/A Gro und p ins .
ZZ Sleep Mode I HIGH Asynchronous sleep mode inp ut. ZZ HIGH will g ate the CLK internally and po wer
d o wn the IDT71V432 to its l owe st p o we r c ons umptio n le ve l. Data re te ntio n is
guaranteed in Sleep Mode.
3104 tbl 02
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.