SN54ALS114A, SN74ALS114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET,COMMON CLEAR,AND COMMON CLOCK SDAS201 - D2661, DECEMBER 1982 - REVISED MAY 1986 * * * * * Fully Buffered to Offer Maximum isolation from External Disturbance Package Options include Plastic Small Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Typical Maximum Clock Frequency 30 MHz Typical Power Dissipation per Flip-Flop 6 mW Dependable Texas Instruments Quality and Reliability SN54ALS114A . . . J PACKAGE SN74ALS114A . . . D OR N PACKAGE (TOP VIEW) CLR 1K 1J 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC CLK 2K 2J 2PRE 2Q 2Q SN54ALS114A . . . FK PACKAGE description The SN54ALS114A is characterized for operation over the full military temperature range of - 55C to 125C. The SN74ALS114A is characterized for operation from 0C to 70C. 1J NC 1PRE NC 1Q OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L L X X X L H H H H H L L Q0 Q0 H H H L H L H H L H L H H H H H TOGGLE H H H X X Q0 Q0 The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at Preset and Clear are near VIL maximum. Furthermore, this configuration is nonstable; that is, it will not persist when either Preset or Clear returns to its inactive (high) level. 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2K NC 2J NC 2PRE NC-No internal connection logic symbol CLR CLK FUNCTION TABLE INPUTS 4 1Q GND NC 2Q 2Q These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs. When Preset and Clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. 1K 1CLR NC VCC CLK (TOP VIEW) 1PRE 1J 1K 2PRE 2J 2K 1 13 R C1 4 S 3 5 1Q 1J 2 6 1Q 1K 10 9 11 8 2Q 2Q 12 This symbol is in accordance with ANSI/IEEE Std 911-1984 and IEC Publication 617-12. Pin numbers are for D, J, and N packages. Copyright 1986, Texas Instruments Incorporated 5BASIC PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54ALS114A, SN74ALS114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET,COMMON CLEAR,AND COMMON CLOCK SDAS201 - D2661, DECEMBER 1982 - REVISED MAY 1986 logic diagram (positive logic) Q Q PRE CLR K J CLK To Other Flip-Flop absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range: SN54ALS114A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C SN74ALS114A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C recommended operating conditions SN54ALS114A VCC VIH Supply voltage VIL IOH Low-level input voltage IOL fclock Low-level output current tw Pulse duration High-level input voltage MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 th TA Hold time, data after CLK 2 0 0.7 0.8 - 0.4 25 0 PRE or CLR low 20 10 CLK high 20 16.5 CLK low 20 16.5 Data 25 22 PRE or CLR inactive 25 20 0 Operating free-air temperature - 55 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 0 V V mA 8 mA 30 mHz ns ns 0 125 UNIT V - 0.4 4 Clock frequency Setup time before CLK 2 NOM High-level output current tsu SN74ALS114A MIN ns 70 C SN54ALS114A, SN74ALS114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET,COMMON CLEAR,AND COMMON CLOCK SDAS201 - D2661, DECEMBER 1982 - REVISED MAY 1986 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54ALS114A TYP MAX TEST CONDITIONS MIN VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = - 18 mA IOH = - 0.4 mA VOL VCC = 4.5 V, VCC = 4.5 V, IOL = 4 mA IOL = 8 mA VCC = 5.5 V, VI = 7 V VCC = 5.5 V, VI = 2.7 V VCC = 5.5 V, VI = 0.4 V J, K, or CLK II PRE or CLR IIH IIL J, K, or CLK PRE or CLR J, K, or CLK PRE or CLR SN74ALS114A TYP MAX MIN - 1.5 VCC - 2 - 1.5 VCC - 2 0.25 UNIT V V 0.4 0.35 0.5 0.1 0.1 0.2 0.2 20 20 40 40 - 0.2 - 0.2 - 0.4 - 0.4 V mA A mA IO VCC = 5.5 V, VO = 2.25 V - 30 - 112 - 30 - 112 mA ICC VCC = 5.5 V, See Note 1 2.5 4.5 2.5 4.5 mA All typical values are at VCC = 5 V, TA = 25C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded. switching characteristics (see Note 2) VCC = 4.5 V to 5.5 V, CL = 50 pF, PARAMETER FROM TO (INPUT) (OUTPUT) RL = 500 , MIN fmax tPLH MAX 25 PRE or CLR Q or Q tPHL tPLH CLK tPHL NOTE 2: Load circuit and Voltage waveforms are shown in Section 1. POST OFFICE BOX 655303 Q or Q * DALLAS, TEXAS 75265 UNIT TA = MIN to MAX SN54ALS114A SN74ALS114A MIN MAX 30 MHz 3 29 3 15 4 30 4 18 3 28 3 15 5 31 5 19 ns ns 3 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated