SN54ALS114A, SN74ALS114A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET,COMMON CLEAR,AND COMMON CLOCK
SDAS201 – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1986, Texas Instruments Incorporated
5BASIC
1
•Fully Buffered to Offer Maximum isolation
from External Disturbance
•Package Options include Plastic Small
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
•Typical Maximum Clock Frequency
30 MHz
•Typical Power Dissipation per Flip-Flop
6 mW
•Dependable Texas Instruments Quality and
Reliability
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the Preset or Clear inputs sets or resets the
outputs regardless of the levels of the other inputs.
When Preset and Clear are inactive (high), data at
the J and K inputs meeting the setup time
requirements are transferred to the outputs on the
negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the fall time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by tying J and K high.
The SN54ALS1 14A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS1 14A is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK J K Q Q
L H X X X H L
HLXXXLH
LL X XXH
†H
†
H H ↓LLQ
0
Q
0
H H ↓HL H L
H H ↓LH L H
H H ↓H H TOGGLE
H H H X X Q0Q0
†The output levels in this configuration are not guaranteed to
meet the minimum levels for VOH if the lows at Preset and
Clear are near VIL maximum. Furthermore, this configuration
is nonstable; that is, it will not persist when either Preset or
Clear returns to its inactive (high) level.
logic symbol‡
Pin numbers are for D, J, and N packages.
1Q
1Q
2Q
2Q
8
9
6
5
R
1K
C1
1J
S
12
2K
10
2PRE
13
CLK
11
2J
2
1K
1
CLR
3
1J
1PRE 4
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CLR
1K
1J
1PRE
1Q
1Q
GND
VCC
CLK
2K
2J
2PRE
2Q
2Q
SN54ALS114A ...J PACKAGE
SN74ALS114A ...D OR N PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
2K
NC
2J
NC
2PRE
1J
NC
1PRE
NC
1Q
SN54ALS114A . . . FK PACKAGE
(TOP VIEW)
1K
1CLR
NC
2Q
2Q CLK
1Q
GND
NC VCC
NC–No internal connection
‡This symbol is in accordance with ANSI/IEEE Std 911-1984 and
IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
UNIT
tsu Setup time before CLK↓ns
SN54ALS114A, SN74ALS114A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET,COMMON CLEAR,AND COMMON CLOCK
SDAS201 – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
logic diagram (positive logic)
To Other Flip-Flop
J
CLR
Q
CLK
K
PRE
Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54ALS114A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS114A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
SN54ALS114A SN74ALS114A
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current –0.4 –0.4 mA
IOL Low-level output current 4 8 mA
fclock Clock frequency 0 25 0 30 mHz
PRE or CLR low 20 10
twPulse duration CLK high 20 16.5 ns
CLK low 20 16.5
Data 25 22
PRE or CLR inactive 25 20
thHold time, data after CLK↓0 0 ns
TAOperating free-air temperature –55 125 0 70 °C
UNIT
VOL V
TEST CONDITIONSPARAMETER
II
IIH
IIL
VCC = 5.5 V, VI = 7 V
VI = 2.7 V
VI = 0.4 V
mA
µA
mA
VCC = 5.5 V,
VCC = 5.5 V,
PARAMETER UNIT
CLK
Q or Q ns
nsQ or Q
PRE or CLR
SN54ALS114A, SN74ALS114A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET,COMMON CLEAR,AND COMMON CLOCK
SDAS201 – D2661, DECEMBER 1982 – REVISED MAY 1986
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS114A SN74ALS114A
MIN TYP†MAX MIN TYP†MAX
VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
VOH VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2 VCC–2 V
VCC = 4.5 V, IOL = 4 mA 0.25 0.4
VCC = 4.5 V, IOL = 8 mA 0.35 0.5
J, K, or CLK 0.1 0.1
PRE or CLR 0.2 0.2
J, K, or CLK 20 20
PRE or CLR 40 40
J, K, or CLK –0.2 –0.2
PRE or CLR –0.4 –0.4
IO‡VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
ICC VCC = 5.5 V, See Note 1 2.5 4.5 2.5 4.5 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded.
switching characteristics (see Note 2)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
FROM TO RL = 500 Ω,
(INPUT) (OUTPUT) TA = MIN to MAX
SN54ALS114A SN74ALS114A
MIN MAX MIN MAX
fmax 25 30 MHz
tPLH 329 3 15
tPHL 4 30 4 18
tPLH 328 3 15
tPHL 5 31 5 19
NOTE 2: Load circuit and Voltage waveforms are shown in Section 1.
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
