CAT522WI - ON Semiconductor

CAT522

Characteristics subject to change without notice

Configured Digitally Programmable Potentiometer (DPP):

Programmable Voltage Applications

FEATURES

 Two 8-bit DPPs configured as programmable

voltage sources in DAC-like applications

 Independent reference inputs

 Non-volatile NVRAM memory wiper storage

 Output voltage range includes both supply rails

 2 independently addressable buffered

output wipers

 1 LSB accuracy, high resolution

 Serial Microwire-like interface

 Single supply operation: 2.7V - 5.5V

 Setting read-back without effecting outputs

For Ordering Information details, see page 14.

APPLICATIONS

 Automated product calibration.

 Remote control adjustment of equipment

 Offset, gain and zero adjustments in self-

calibrating and adaptive control systems.

 Tamper-proof calibrations.

 DAC (with memory) substitute.

PIN CONFIGURATION

PDIP 14-Lead (L)

SOIC 14-Lead (W)

VDD 1

14

VREFH1

CLK 2

13

VREFH1

RDY/BSY

¯¯¯¯ 3

12

VOUT1

CS 4

11

VOUT2

DI 5

10

VREFL2

DO 6

8 VREFL1

PROG 7

8 GND

CAT522

DESCRIPTION

The CAT522 is a dual, 8-bit digitally-programmable

potentiometer (DPP) configured for programmable

voltage and DAC-like applications. Intended for final

calibration of products such as camcorders, fax

machines and cellular telephones on automated high

volume production lines, it is also well suited for self-

calibrating systems and for applications where

equipment which requires periodic adjustment is either

difficult to access or in a hazardous environment.

The CAT522 offers two independently programmable

DPPs each having its own reference inputs and each

capable of rail to rail output swing. The wipers are

buffered by rail to rail opamps. Wiper settings, stored

in non-volatile NVRAM memory, are not lost when the

device is powered down and are automatically

reinstated when power is returned. Each wiper can

be dithered to test new output values without effecting

the stored settings and stored settings can be read

back without disturbing the DPP's output.

The CAT522 is controlled with a simple 3-wire,

microwire-like serial interface. A Chip Select pin

allows several devices to share a common serial

interface. Communication back to the host controller is

via a single serial data line thanks to the CAT522 Tri-

Stated Data Output pin. A RDY/BSY

¯¯¯¯ output working

in concert with an internal low voltage detector signals

proper operation of the non-volatile NVRAM memory

Erase/Write cycle.

The CAT522 is available in the 0°C to 70°C

commercial and -40°C to 85°C industrial operating

temperature ranges. Both 14-pin plastic DIP and

surface mount packages are available.

Not Recommended for New Design

CAT522 Not Recommended for New Design

Characteristics subject to change without notice

FUNCTIONAL DIAGRAM

SERIAL

DATA

OUTPUT

REGISTER

CAT522

VREFL2

GND

VDD VREFH2

VREFH1

12

6DO

VOUT1

PROG PROGRAM

CONTROL

3

DI

CLK

5

2

4

7

13141

109

24kΩ

WIPER CONTROL REGISTERS

AND NVRAM

CS

RDY/BSY

+

–

SERIAL

CONTROL

VREFL1

8

11 VOUT2

+

–

Not Recommended for New Design CAT522

Characteristics subject to change without notice

ABSOLUTE MAXIMUM RATINGS (1)

Parameters Ratings Units

Supply Voltage

V

DD to GND -0.5 to +7 V

Inputs

CLK to GND -0.5 to VDD +0.5 V

CS to GND -0.5 to VDD +0.5 V

DI to GND -0.5 to VDD +0.5 V

RDY/BSY

¯¯¯¯ to GND -0.5 to VDD +0.5 V

PROG to GND -0.5 to VDD +0.5 V

V

REFH to GND -0.5 to VDD +0.5 V

V

REFL to GND -0.5 to VDD +0.5 V

Parameters Ratings Units

Outputs

D

0 to GND -0.5 to VDD +0.5 V

V

OUT 1– 4 to GND -0.5 to VDD +0.5 V

Operating Ambient Temperature

Commercial

(‘C’ or Blank suffix) 0 to +70 °C

Industrial (‘I’ suffix) -40 to +85 °C

Junction Temperature +150 °C

Storage Temperature -65 to +150 °C

Lead Soldering (10s max) +300 °C

RELIABILITY CHARACTERISTICS

Symbol Parameter Test Method Min Max Units

VZAP(2) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 V

ILTH(2) (3) Latch-Up JEDEC Standard 17 100 mA

POWER SUPPLY

Symbol Parameter Conditions Min Typ Max Units

IDD1 Supply Current (Read) Normal Operating — 400 600 µA

IDD2 Supply Current (Write) Programming, VDD = 5V — 1600 2500 µA

V

DD = 3V — 1000 1600 µA

VDD Operating Voltage Range 2.7 — 5.5 V

LOGIC INPUTS

Symbol Parameter Conditions Min Typ Max Units

IIH Input Leakage Current VIN = VDD — — 10 µA

IIL Input Leakage Current VIN = 0V — — -10 µA

VIH High Level Input Voltage 2 — VDD V

VIL Low Level Input Voltage 0 — 0.8 V

LOGIC OUTPUTS

Symbol Parameter Conditions Min Typ Max Units

VOH High Level Output Voltage IOH = -40µA VDD -0.3 — — V

VIL Low Level Output Voltage IOL = 1mA, VDD = +5V — — 0.4 V

I

OL = 0.4mA, VDD = +3V — — 0.4 V

Notes:

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this

specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

(2) This parameter is tested initially and after a design or process change that affects the parameter.

(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.

CAT522 Not Recommended for New Design

Characteristics subject to change without notice

POTENTIOMETER CHARACTERISTICS

VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

Potentiometer Resistance 24 kΩ

RPOT to RPOT Match — ±0.5 ±1 %

Pot Resistance Tolerance ±20 %

Voltage on VREFH pin 2.7 VDD V

Voltage on VREFL pin 0 VDD - 2.7 V

RPOT

Resolution 0.4 %

INL Integral Linearity Error 0.5 1 LSB

DNL Differential Linearity Error 0.25 0.5 LSB

ROUT Buffer Output Resistance 10 Ω

IOUT Buffer Output Current 3 mA

TCRPOT TC of Pot Resistance 300 ppm/ºC

CH/CL Potentiometer Capacitances 8/8 pF

AC ELECTRICAL CHARACTERISTICS

VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

Digital

tCSMIN Minimum CS Low Time 150 — — ns

tCSS CS Setup Time 100 — — ns

tCSH CS Hold Time 0 — — ns

tDIS DI Setup Time 50 — — ns

tDIH DI Hold Time 50 — — ns

tDO1 Output Delay to 1 — — 150 ns

tDO0 Output Delay to 0

CL = 100pF(1)

— — 150 ns

tHZ Output Delay to High-Z — 400 — ns

tLZ Output Delay to Low-Z — 400 — ns

tBUSY Erase/Write Cycle Time — 4 5 ms

tPS PROG Setup Time 150 — — ns

tPROG Minimum Pulse Width 700 — — ns

tCLKH Minimum CLK High Time 500 — — ns

tCLKL Minimum CLK Low Time 300 — — ns

fC Clock Frequency DC — 1 MHz

Analog

tDS DPP Settling Time to 1 LSB CLOAD = 10pF, VDD = +5V — 3 10 µs

C

LOAD = 10pF, VDD = +3V — 6 10 µs

Notes:

(1) All timing measurements are defined at the point of signal crossing VDD / 2.

(2) These parameters are periodically sampled and are not 100% tested.

Not Recommended for New Design CAT522

Characteristics subject to change without notice

A.C. TIMING DIAGRAM

to1 2 3 4 5

CLK

CS

DI

DO

PROG

t H

CLK

tL

CLK tCSH

tCSS

tCSMIN

tDIS

tDIH

tDO0

tLZ

tDO1

tHZ

RDY/BSY

tPROG

tPS

to1 2 3 4 5

tBUSY

CAT522 Not Recommended for New Design

Characteristics subject to change without notice

PIN DESCRIPTION

Pin Name Function

1 VDD Power supply positive

2 CLK Clock input pin

3 RDY/BSY

¯¯¯¯ Ready/Busy output

4 CS Chip select

5 DI Serial data input pin

6 DO Serial data output pin

7 PROG

EEPROM Programming Enable

Input

8 GND Power supply ground

9 VREFL1 Minimum DPP1 output voltage

10 VREFL2 Minimum DPP2 output voltage

11 VOUT2 DPP2 output

12 VOUT1 DPP1 output

13 VREFH2 Maximum DPP2 output voltage

14 VREFH1 Maximum DPP1 output voltage

DPP addressing is as follows:

DPP OUTPUT A0 A1

VOUT1 0 1

VOUT2 1 1

DEVICE OPERATION

The CAT522 is a dual 8-bit configured digitally

programmable potentiometer (DPP) whose outputs

can be programmed to any one of 256 individual

voltage steps. Once programmed, these output

settings are retained in non-volatile memory and will

not be lost when power is removed from the chip.

Upon power up the DPPs return to the settings stored

in non-volatile memory. Each DPP can be written to

and read from independently without effecting the

output voltage during the read or write cycle. Each

output can also be adjusted without altering the

stored output setting, which is useful for testing new

output settings before storing them in memory.

DIGITAL INTERFACE

The CAT522 employs a 3 wire serial, Microwire-like

control interface consisting of Clock (CLK), Chip

Select (CS) and Data In (DI) inputs. For all

operations, address and data are shifted in LSB first.

In addition, all digital data must be preceded by a logic

“1” as a start bit. The DPP address and data are

clocked into the DI pin on the clock’s rising edge.

When sending multiple blocks of information a

minimum of two clock cycles is required between the

last block sent and the next start bit.

Multiple devices may share a common input data line

by selectively activating the CS control of the desired

IC. Data Outputs (DO) can also share a common line

because the DO pin is Tri-Stated and returns to a high

impedance when not in use.

CHIP SELECT

Chip Select (CS) enables and disables the CAT522’s

read and write operations. When CS is high data may

be read to or from the chip, and the Data Output (DO)

pin is active. Data loaded into the DPP control regis–

ters will remain in effect until CS goes low. Bringing

CS to a logic low returns all DPP outputs to the

settings stored in non-volatile memory and switches

DO to its high impedance Tri-State mode.

Because CS functions like a reset the CS pin has

been desensitized with a 30 ns to 90 ns filter circuit to

prevent noise spikes from causing unwanted resets

and the loss of volatile data.

CLOCK

The CAT522’s clock controls both data flow in and out

of the IC and non-volatile memory cell programming.

Serial data is shifted into the DI pin and out of the DO

pin on the clock’s rising edge. While it is not neces–

sary for the clock to be running between data

transfers, the clock must be operating in order to write

to non-volatile memory, even though the data being

saved may already be resident in the DPP wiper

control register.

Not Recommended for New Design CAT522

Characteristics subject to change without notice

No clock is necessary upon system power-up. The

CAT522’s internal power-on reset circuitry loads data

from non-volatile memory to the DPPs without using

the external clock.

As data transfers are edge triggered clean clock

transitions are necessary to avoid falsely clocking

data into the control registers. Standard CMOS and

TTL logic families work well in this regard and it is

recommended that any mechanical switches used for

breadboarding or device evaluation purposes be

debounced by a flip-flop or other suitable debouncing

circuit.

VREF

VREF, the voltage applied between pins VREFH & VREFL,

sets the DPP’s Zero to Full Scale output range where

VREFL = Zero and VREFH = Full Scale. VREF can span

the full power supply range or just a fraction of it. In

typical applications VREFH & VREFL are connected

across the power supply rails. When using less than

the full supply voltage be mindfull of the limits placed

on VREFH and VREFL as specified in the References

section of DC Electrical Characteristics.

READY/BUSY

¯¯¯¯¯

When saving data to non-volatile memory, the

Ready/Busy ouput (RDY/BSY

¯¯¯¯) signals the start and

duration of the erase/write cycle. Upon receiving a

command to store data (PROG goes high) RDY/BSY

¯¯¯¯

goes low and remains low until the programming cycle is

complete. During this time the CAT521 will ignore any

data appearing at DI and no data will be output on DO.

RDY/BSY

¯¯¯¯ is internally ANDed with a low voltage

detector circuit monitoring VDD. If VDD is below the

minimum value required for non-volatile programming,

RDY/BSY

¯¯¯¯ will remain high following the program

command indicating a failure to record the desired

data in non-volatile memory.

DATA OUTPUT

Data is output serially by the CAT522, LSB first, via

the Data Out (DO) pin following the reception of a

start bit and two address bits by the Data Input (DI).

DO becomes active whenever CS goes high and

resumes its high impedance Tri-State mode when CS

returns low. Tri-Stating the DO pin allows several

522s to share a single serial data line and simplifies

interfacing multiple 522s to a microprocessor.

WRITING TO MEMORY

Programming the CAT522’s non-volatile memory is

accomplished through the control signals: Chip Select

(CS) and Program (PROG). With CS high, a start bit

followed by a two bit DPP address and eight data bits

are clocked into the DPP wiper control register via the

DI pin. Data enters on the clock’s rising edge. The

DPP output changes to its new setting on the clock

cycle following D7, the last data bit.

Programming is accomplished by bringing PROG high

sometime after the start bit and at least 150 ns prior to

the rising edge of the clock cycle immediately following

the D7 bit. Two clock cycles after the D7 bit the DPP

wiper control register will be ready to receive the next

set of address and data bits. The clock must be kept

running throughout the programming cycle. Internal

control circuitry takes care of generating and ramping

up the programming voltage for data transfer to the

non-volatile cells. The CAT522’s non-volatile memory

cells will endure over 1,000,000 write cycles and will

retain data for a minimum of 100 years without being

refreshed.

Figure 1. Writing to Memory

D0 D1 D2 D3 D4 D5 D6 D7

A0 A1 D0 D1 D2 D3 D4 D5 D6 D71

NEW DPP DATA

CURRENT DPP DATA

CURRENT

DPP VALUE

NON-VOLATILE

DPP

OUTPUT

PROG

DO

DI

CS

NEW

DPP VALUE

VOLATILE

NEW

DPP VALUE

NON-VOLATILE

t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

o

RDY/BSY

CAT522 Not Recommended for New Design

Characteristics subject to change without notice

READING DATA

Each time data is transferred into a DPP control

register currently held data is shifted out via the D0

pin, thus in every data transaction a read cycle

occurs. Note, however, that the reading process is

destructive. Data must be removed from the register

in order to be read. Figure 2 depicts a Read Only

cycle in which no change occurs in the DPP’s output.

This feature allows µPs to poll DPPs for their current

setting without disturbing the output voltage but it

assumes that the setting being read is also stored in

non-volatile memory so that it can be restored at the

end of the read cycle. In Figure 2 CS returns low

before the 13th clock cycle completes. In doing so the

non-volatile memory setting is reloaded into the DPP

wiper control register. Since this value is the same as

that which had been there previously no change in the

DPP’s output is noticed. Had the value held in the

control register been different from that stored in non-

volatile memory then a change would occur at the

read cycle’s conclusion.

TEMPORARILY CHANGE OUTPUT

The CAT522 allows temporary changes in DPP’s

output to be made without disturbing the settings

retained in non-volatile memory. This feature is parti–

cularly useful when testing for a new output setting

and allows for user adjustment of preset or default

values without losing the original factory settings.

Figure 3 shows the control and data signals needed

to effect a temporary output change. DPP wiper

settings may be changed as many times as required

and can be made to any of the two DPPs in any order

or sequence. The temporary setting(s) remain in

effect long as CS remains high. When CS returns low

all two DPPs will return to the output values stored in

non-volatile memory.

When it is desired to save a new setting acquired

using this feature, the new value must be reloaded

into the DPP wiper control register prior to

programming. This is because the CAT522’s internal

control circuitry discards from the programming

register the new data two clock cycles after receiving

it if no PROG signal is received.

Figure 2. Reading from Memory

Figure 3. Temporary Change in Output

A0 A11

DO

DI

CS

PROG

DPP

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12

o

CURRENT

DPP VALUE

NON-VOLATILE

D0 D1 D2 D3 D4 D5 D6 D7

CURRENT DPP DATA

RDY/BSY

D0 D1 D2 D3 D4 D5 D6 D7

A0 A1 D0 D1 D2 D3 D4 D5 D6 D71

NEW DPP DATA

CURRENT DPP DATA

DO

DI

CS

PROG

DPP

OUTPUT

t 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

o

CURRENT

DPP VALUE

NON-VOLATILE

NEW

DPP VALUE

VOLATILE

CURRENT

DPP VALUE

NON-VOLATILE

R

DY/BSY

Not Recommended for New Design CAT522

Characteristics subject to change without notice

+

–

LM 324

CAT522

GND

V

DD

V

REFH

5.1V

1N5231B

10µF

35V

10kΩ

28 - 32V

OUTPU

T

MPT3055EL

0 - 25V

@ 1A

4.02kΩ

15kΩ

1.00kΩ

V

REFL

CONTR

O

L

& DATA

APPLICATION CIRCUITS

CAT522

GND

V

DD

V

REFH

V

REFL

CONTROL

& DATA OP 07

V = ( ) - V

OUT

R

F

R +

I

-15V

+15V

+5V

R

I

R

F

V

DPP

For R =

I

R

F

V = 2V - V

OUT IDPP

V

I

R

I

R

F

V

OUT

+

–

DPP INPUT DPP OUTPUT ANALOG OUTPUT

MSB LSB

1111 1111

1000 0000

0111 1111

0000 0001

0000 0000

REFREFREF

V990.0=V01.0+V98.0×

255

REFREFREF

V502.0=V01.0+V98.0×

255

128

REFREFREF

V498.0=V01.0+V98.0×

255

127

REFREFREF

V014.0=V01.0+V98.0×

255

1

REFREFREF

V010.0=V01.0+V98.0×

255

0

V90.4+=VOUT

V02.0+=VOUT

V02.-0=V

OUT

V86.4-=V

OUT

V90.4-=V

OUT

DPP

255

CODE

=V

REFFS V99.0=V

REFZERO

V01.0=V

V5=V

REF

FI

R=R

x (V

FS

- V

ZERO

) + V

ZERO

V

DPP

Bipolar DPP Output

Amplified DPP Output

Digitally Trimmed Voltage Reference

Digitally Controlled Voltage Reference

CAT522

GND

VDD VREFH

VREF

= 5.00V

I > 2mA

LT 1029

V+

V

REFL

CONTROL

& DATA

CAT522

GND

V

DD

V

REFH

V

REFL

CONTR

O

L

& DATA OP 07

-15V

+15V

+5V R

I

R

F

V

OUT

+

–

V

OUT

= (1 + ) V

DPP

R

F

R

I

CAT522 Not Recommended for New Design

Characteristics subject to change without notice

Coarse-Fine Offset Control by Averaging DPP

Outputs for Single Power Supply Systems

Coarse-Fine Offset Control by Averaging DPP

Outputs for Dual Power Supply Systems

Current Sink with 4 Decades of Resolution

GND

V

OFFSET

FINE ADJUST

DPP

CAT522

COARSE ADJUST

DPP

V

DD

+5V

V

REFH

V

REF

+V

V

REFL

R

C

127R

C

+

–

R

C

= V

REF

256 x 1µA

Fine adjust gives ±1 LSB change in V

OFFSET

when V

OFFSET

= V

REF

/2

GND

V

OFFSET

FINE ADJUST

DPP

CAT522

COARSE ADJUST

DPP

V

DD

+5V

V

REFH

+V

REF

+V

-V

V

REFL

R

C

R

0

127R

C

+

–

-V

REF

R

C

= (+V

REF

) - (V

OFFSET+

)

1µA

R

0

= (-V

REF

) + (V

OFFSET+

)

1µA

CONTROL

&DATA

GND

V

REFL

V

DD

+5V

I

SINK

= 2 - 255mA

1mA steps

5µA steps

TIP30

-15V

V

REFH

4.7µF LM385-2.5

DPP1

CAT522

DPP2

+15V

39Ω 1W10kΩ

2.2kΩ

10kΩ

39Ω 1W

2N7000

+

–

3.9kΩ5MΩ5MΩ

10kΩ

+

–

+

–

+5V

Not Recommended for New Design CAT522

Characteristics subject to change without notice

Current Source with 4 Decades of Resolution

ISOURCE = 2 ÷ 255mA

VDD

+5V

VREFH

LM385-2.5

BS170P 5µA steps

1mA steps

BS170P

10kΩ10kΩ

51kΩ

TIP29

+15V

+

–

-15V

39Ω 1W

5MΩ5MΩ

CONTROL

&DATA

GND

VREFL

DPP1

CAT522

DPP2

+

–

3.9kΩ5MΩ5MΩ

+

–

CAT522 Not Recommended for New Design

Characteristics subject to change without notice

PACKAGE OUTLINE DRAWINGS

PDIP 14-LEAD (L)(1)(2)

E1

E

eB

A1

eb

b1

D

c

A

A2

TOP VIEW

SIDE VIEW END VIEW

L

SYMBOL MIN NOM MAX

A3.56 5.33

A1 0.38

A2 2.92 3.30 4.95

b0.360.450.55

b1 1.15 1.52 1.77

c0.210.260.35

D 18.67 19.05 19.68

E7.627.878.25

E1 6.10 6.35 7.11

e2.54 BSC

eB 7.88 10.92

L2.993.303.81

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-001.

Not Recommended for New Design CAT522

Characteristics subject to change without notice

SOIC 14-LEAD (W)(1)(2)

TOP VIEW

PIN#1 IDENTIFICATION

E

D

A

eb

A1

L

h

c

E1

SIDE VIEW END VIEW

θ

SYMBOL MIN NOM MAX

A 1.35 1.75

A1 0.10 0.25

b 0.33 0.51

c 0.19 0.25

D 8.55 8.65 8.75

E 5.80 6.00 6.20

E1 3.80 3.90 4.00

e 1.27 BSC

h 0.25 0.50

L 0.40 1.27

θ0º 8º

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

CAT522 Not Recommended for New Design

Characteristics subject to change without notice

EXAMPLE OF ORDERING INFORMATION(1)

ORDERING PART NUMBER

CAT522LI

CAT522WI

Notes:

(1) All packages are RoHS-compliant (Lead-free, Halogen-free).

(2) The standard lead finish is Matte-Tin.

(3) The device used in the above example is a CAT522WI-T2 (SOIC, Industrial Temperature, Tape & Reel, 2000).

Prefix Device # Suffix

CAT 522 W I

–

T2

Optional

Company ID

Package

L: PDIP

W: SOIC

Temperature Range

I = Industrial (-40ºC to 85ºC)

Product

Number

522

Tape & Reel

T: Tape & Reel

2: 2000/Reel

Not Recommended for New Design CAT522

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any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights

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with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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REVISION HISTORY

Date Revision Description

16-Mar-04 D Updated Potentiometer Characteristics

12-Jul-04 E

Updated Functional Diagram

Updated Potentiometer Characteristics

26-Jul-07 F

Add Package Outline Drawings

Update Example of Ordering Information

Updated Ordering Information

Added MD- to document number

31-Oct-07 G Update Example of Ordering Information

14-Jul-08 H Add “Not Recommended for New Design” to the top of all pages.

24-Nov-08 I Change logo and fine print to ON Semiconductor