AMC1306E05DWVR - TEXAS INSTRUMENTS

December, 2018 − Rev. 6

1Publication Order Number:

NCP186/D

NCP186

Fast Transient Response

Low Voltage 1 A LDO

The NCP186x series are CMOS LDO regulators featuring 1 A

output current. The input voltage is as low as 1.8 V and the output

voltage can be set from 0.8 V.

Features

•Operating Input Voltage Range: 1.8 V to 5.5 V

•Output Voltage Range: 0.8 to 3.9 V

•Fixed or Adjustable Output Voltage Applications

•Quiescent Current typ. 90 mA

•Low Dropout: 100 mV typ. at 1 A, VOUT = 3.0 V

•High Output Voltage Accuracy ±1%

•Stable with Small 1 mF Ceramic Capacitors

•Over−current Protection

•Built−in Soft Start Circuit to Suppress Inrush Current

•Thermal Shutdown Protection: 165°C

•With (NCP186A) and Without (NCP186B) Output Discharge

Function

•Available in XDFN8 1.2x1.6mm & DFN12 4x4mm Packages

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

•Battery Powered Equipment

•Portable Communication Equipment

•Cameras, Image Sensors and Camcorders

Figure 1. Typical Application Schematic

Set IR1, IR2 in range from 10 mA to 100 mA

VOUT−ADJ +VOUT−NOM @ǒ1)R1

R2Ǔ+0.8 @ǒ1)R1

R2Ǔ

NCP186 0.8V

OUT

FB/

ADJ

GND

COUTCIN

OFF

VIN VOUT=0.8V

NCP186 0.8V

OUT

FB/

ADJ

GND

COUTCIN

OFF

VIN VOUT−ADJ=1.2V

5k1

10k

Fixed Output Voltage Application

Adjustable Output Voltage Application

0.8V

1 nF

1 mF1 mF

This document contains information on some products that are still under development.

ON Semiconductor reserves the right to change or discontinue these products without

notice.

ORDERING INFORMATION

XDFN8

MX SUFFIX

CASE 711AS

PIN CONNECTIONS

See detailed ordering and shipping information on page 12 of

this data sheet.

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(Top View)

MARKING

DIAGRAMS

XX = Specific Device Code

M = Date Code

G= Pb−Free Package

XXMG

(Note: Microdot may be in either location)

GND

OUT

N/C

FB/ADJ

XXXXXX

ALYWG

DFN12

MU SUFFIX

CASE 506CE

XXXXXX = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

(Note: Microdot may be in either location)

(Top View)

N/C

OUT

N/C

GND

N/C

FB/ADJ

N/C

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Figure 2. Internal Block Diagram

OUT

GND

PROG. VOLTAGE

REFERENCE AND

SOFT−START

FB/ADJ

0.7 V

THERMAL

SHUTDOWN

NCP186A (with output active discharge) NCP186B (without output active discharge)

OUT

GND

PROG. VOLTAGE

REFERENCE AND

SOFT−START

FB/ADJ

0.7 V

THERMAL

SHUTDOWN

Table 1. PIN FUNCTION DESCRIPTION

Pin No.

XDFN8

Pin No.

DFN12

Name Description

1, 2 2, 3 OUT LDO output pin

3 1,4,6,7,12 N/C Tune the space here, this line is not horizontally aligned with others. Not internally connected.

This pin can be tied to the ground plane to improve thermal dissipation.

4 5 FB/ADJ Feedback / adjustable input pin (connect this pin directly to the OUT pin or to the resistor di-

vider)

5 8 GND Ground pin

6 9 EN Chip enable input pin (active “H”)

7, 8 10, 11 IN Power supply input pin

EPAD EPAD EPAD It’s recommended to connect the EPAD to GND, but leaving it open is also acceptable

Table 2. ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

Input Voltage (Note 1) IN −0.3 to 6.0 V

Output Voltage OUT −0.3 to VIN + 0.3 V

Chip Enable Input EN −0.3 to 6.0 V

Output Current IOUT Internally Limited mA

Maximum Junction Temperature TJ(MAX) 150 °C

Storage Temperature TSTG −55 to 150 °C

ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V

ESD Capability, Charged Device Model (Note 2) ESDCDM 1000 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

2. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD Charged Device Model tested per JS−002−2014

Latchup Current Maximum Rating tested per JEDEC standard: JESD78

Table 3. THERMAL CHARACTERISTICS

Rating Symbol Value Unit

Thermal Resistance, Junction−to−Air, XDFN8 1.2 mm x 1.6 mm (Note 3) RqJA 111 °C/W

Thermal Resistance, Junction−to−Air, DFN12 4 mm x 4 mm (Note 3) RqJA 44 °C/W

3. Measured according to JEDEC board specification. Detailed description of the board can be found in JESD51−7.

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Table 4. ELECTRICAL CHARACTERISTICS

VIN = VOUT_NOM + 0.5 V or VIN = 1.8 V whichever is greater; IOUT = 1 mA; CIN = COUT = 1.0 mF (effective capacitance) (Note 4);

VEN = 1.2 V; TJ = 25°C (Note 5); FB/ADJ pin connected to OUT; unless otherwise noted. The specifications in bold are guaranteed at

−40°C ≤ TJ ≤ 125°C.

Parameter Test Conditions Symbol Min Typ Max Unit

Operating Input Voltage VIN 1.8 5.5 V

Output Voltage Accuracy VOUT_NOM + 0.5 V ≤ VIN ≤ 5.5 V, VIN ≥ 1.8 V

IOUT = 0 to 1 A, −40°C ≤ TJ ≤ 85°C

VOUT−NOM −1.0 1.0 %

VOUT_NOM + 0.5 V ≤ VIN ≤ 5.5 V, VIN ≥ 1.8 V

IOUT = 0 to 1 A, −40°C ≤ TJ ≤ 125°C

VOUT_NOM ≥ 1.2 V

−2.0 1.0

VOUT_NOM + 0.5 V ≤ VIN ≤ 5.5 V, VIN ≥ 1.8 V

IOUT = 0 to 1 A, −40°C ≤ TJ ≤ 125°C

VOUT_NOM < 1.2 V

−2.5 1.0

Load Regulation IOUT = 1 mA to 1000 mA LoadReg 0.7 5.0 mV

Line Regulation VIN = VOUT_NOM + 0.5 V to 5.0 V, VIN ≥ 1.8 V LineReg 0.002 0.1 %/V

Dropout Voltage XDFN8 1.2x1.6

IOUT = 1 A

When VOUT falls to

VOUT_NOM – 100 mV

VOUT_NOM = 1.2 V VDO 405 585 mV

VOUT_NOM = 1.75 V 180 295

VOUT_NOM = 1.8 V 175 285

VOUT_NOM = 1.85 V 170 280

VOUT_NOM = 2.5 V 120 190

VOUT_NOM = 2.8 V 110 170

VOUT_NOM = 2.95 V 102 163

VOUT_NOM = 3.0 V 100 160

VOUT_NOM = 3.3 V 95 145

VOUT_NOM = 3.5 V 92 135

VOUT_NOM = 3.9 V 86 130

Quiescent Current IOUT = 0 mA IQ90 140 mA

Standby Current VEN = 0 V ISTBY 0.1 1.5 mA

FB/ADJ Pin Input Current IFB/ADJ 10 nA

Output Current Limit VOUT = 90% of VOUT_NOM IOCL 1100 1400 mA

Output Short Circuit Current VOUT = 0 V IOSC 1100 1400 mA

Enable Input Current IEN 0.15 0.6 mA

Enable Threshold Voltage EN Input Voltage “H” VENH 1.0 V

EN Input Voltage “L” VENL 0.4

Power Supply Rejection Ratio VIN = VOUT_NOM + 1.0 V, Ripple 0.2 Vp−p,

IOUT = 30 mA, f = 1 kHz

PSRR 75 dB

Output Noise f = 10 Hz to 100 kHz VN48 mVRMS

Output Discharge Resistance

(NCP186A option only)

VIN = 5.5 V, VEN = 0 V, VOUT = 1.8 V RAD 34 W

Thermal Shutdown

Temperature

Temperature rising from TJ = +25°C TSD 165 °C

Thermal Shutdown Hysteresis Temperature falling from TSD TSDH 20 °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Effective capacitance, including the effect of DC bias, tolerance and temperature. See the Application Information section for more

information.

5. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C.

Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.

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TYPICAL CHARACTERISTICS

VIN = VOUT−NOM + 0.5 V or VIN = 1.8 V, whichever is greater, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF, TJ = 25°C.

Figure 3. Output Voltage vs. Temperature Figure 4. Output Voltage vs. Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

1206040200−20−40

1.176

1.179

1.182

1.191

1.203

1.206

1.212

806040200−20−40

1.764

1.769

1.784

1.789

1.794

Figure 5. Output Voltage vs. Temperature

TEMPERATURE (°C)

806040200−20−40

3.234

3.244

3.264

3.274

3.284

3.324

OUTPUT VOLTAGE (V)

1.185

1.188

1.200

1.209

VOUT−NOM = 1.2 V VOUT−NOM = 1.8 V

1.774

1.799

1.804

1.814

3.254

3.294

3.304

3.314

VOUT−NOM = 3.3 V

Figure 6. Output Voltage vs. Temperature

TEMPERATURE (°C)

806040200−20−40

3.822

3.832

3.852

3.872

3.882

3.922

3.932

OUTPUT VOLTAGE (V)

3.842

3.892

3.902

3.912

VOUT−NOM = 3.9 V

Figure 7. Line Regulation vs. Temperature

TEMPERATURE (°C)

806040200−20−40

−0.10

−0.08

−0.04

−0.02

0.02

0.04

0.10

LINE REGULATION (%/V)

−0.06

0.06

0.08

VIN = VOUT−NOM + 0.5 V to 5.0 V, VIN ≥ 1.8 V

VOUT−NOM = 1.2 V

VOUT−NOM = 1.8 V

VOUT−NOM = 3.3 V

VOUT−NOM = 3.9 V

Figure 8. Load Regulation vs. Temperature

TEMPERATURE (°C)

806040200−20−40

−5

−4

−2

−1

LOAD REGULATION (mV)

−3

IOUT = 1 mA to 1000 mA

80 100

1.194

1.197

100 120

1.779

1.809

100 120 100 120

3.862

100 120

VOUT−NOM = 1.2 V

VOUT−NOM = 1.8 V

VOUT−NOM = 3.3 V

VOUT−NOM = 3.9 V

100 120

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TYPICAL CHARACTERISTICS

VIN = VOUT−NOM + 0.5 V or VIN = 1.8 V, whichever is greater, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF, TJ = 25°C.

Figure 9. Dropout Voltage vs. Output Current Figure 10. Dropout Voltage vs. Temperature

OUTPUT CURRENT (mA) TEMPERATURE (°C)

10008006004002000

125

150

200

225

275

806040200−20−40

100

150

275

Figure 11. Dropout Voltage vs. Output Current Figure 12. Dropout Voltage vs. Temperature

OUTPUT CURRENT (mA) TEMPERATURE (°C)

10008006004002000

140

806040200−20−40

100

Figure 13. Ground Current vs. Output Current

OUTPUT CURRENT (mA)

10008006004002000

100

150

250

300

400

450

DROPOUT VOLTAGE (mV)

GROUND CURRENT (mA)

100

175

250 VOUT−NOM = 1.8 V VOUT−NOM = 1.8 V

175

200

225

100

120 120

140

200

350

TJ = 125°C

TJ = 25°C

TJ = −40°C

125

250

VOUT−NOM = 3.3 V

TJ = 25°C

TJ = −40°C

VOUT−NOM = 3.3 V

IOUT = 10 mA

IOUT = 200 mA

IOUT = 500 mA

IOUT = 1000 mA

IOUT = 10 mA

IOUT = 200 mA

IOUT = 500 mA

IOUT = 1000 mA

100 120

Figure 14. Quiescent Current vs. Temperature

TEMPERATURE (°C)

806040200−20−40

100

110

120

QUIESCENT CURRENT (mA)

IOUT = 0 mA

TJ = 125°C

100 120

VOUT−NOM = 1.8 V

TJ = 25°C

TJ = −40°C

TJ = 125°C

100 120

VOUT−NOM = 1.2 V

VOUT−NOM = 1.8 V

VOUT−NOM = 3.3 V

VOUT−NOM = 3.9 V

XDFN8 (AMX/BMX) XDFN8 (AMX/BMX)

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TYPICAL CHARACTERISTICS

VIN = VOUT−NOM + 0.5 V or VIN = 1.8 V, whichever is greater, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF, TJ = 25°C.

Figure 15. Quiescent Current vs. Input Voltage Figure 16. Standby Current vs. Temperature

INPUT VOLTAGE (V) TEMPERATURE (°C)

5.55.04.03.53.02.52.0

100

110

120

8060 12040200−20−40

0.1

0.2

0.4

0.6

0.7

0.8

1.0

Figure 17. Short Circuit Current vs.

Temperature

Figure 18. Output Current Limit vs.

Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

12080400−20−40

1.1

1.2

1.4

1.5

1.7

1.9

2.0

806040200−20−40

1.1

1.2

1.4

1.6

1.7

1.8

2.0

Figure 19. Enable Threshold Voltage vs.

Temperature

Figure 20. Enable Input Current vs.

Temperature

TEMPERATURE (°C) TEMPERATURE (°C)

806040200−20−40

0.4

0.6

0.8

1.0

806040200−20−40

0.1

0.2

0.3

0.4

0.5

0.6

QUIESCENT CURRENT (mA)

STANDBY CURRENT (mA)

SHORT CIRCUIT CURRENT (A)

OUTPUT CURRENT LIMIT (A)

ENABLE THRESHOLD VOLTAGE (V)

ENABLE INPUT CURRENT (mA)

0.5

1.3

1.5

1.9

VOUT−FORCED = 0 V

0.5

0.7

0.9

VOUT−FORCED = 90% of VOUT−NOM

VOUT−NOM = 1.2 V

VOUT−NOM = 3.3 V

VOUT−NOM = 1.8 V

OFF −> ON

ON −> OFF

VOUT−NOM = 1.8 V

IOUT = 0 mA

VOUT−NOM = 1.2 V

VOUT−NOM = 1.8 V

VOUT−NOM = 3.3 V

VOUT−NOM = 3.9 V

4.5

TJ = 125°C

TJ = 25°C

TJ = −40°C

VEN = 0 V

100

0.3

0.9

20 60 100

1.3

1.6

1.8

VOUT−NOM = 3.9 V

100 120

VOUT−NOM = 1.2 V

VOUT−NOM = 3.3 V

VOUT−NOM = 1.8 V

VOUT−NOM = 3.9 V

VOUT−NOM = 1.2 V

VOUT−NOM = 1.8 V

VOUT−NOM = 3.3 V

VOUT−NOM = 3.9 V

100 120 100 120

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TYPICAL CHARACTERISTICS

VIN = VOUT−NOM + 0.5 V or VIN = 1.8 V, whichever is greater, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF, TJ = 25°C.

Figure 21. Output Discharge Resistance vs.

Temperature (NCP186A option only)

Figure 22. Power Supply Rejection Ratio

TEMPERATURE (°C) FREQUENCY (Hz)

806040200−20−40

10M1M100k10k1k10010

Figure 23. Output Voltage Noise Spectral

Density

FREQUENCY (Hz)

1M100K10K1K10010

Figure 24. Turn−ON/OFF − VIN driven (slow) Figure 25. Turn−ON − VIN driven (fast)

1 ms/div 20 ms/div

OUTPUT DISCHARGE RESISTANCE (W)

PSRR (dB)

OUTPUT VOLTAGE NOISE (mV/√Hz)

50 mA/div

VOUT−NOM = 1.2 V VOUT−NOM = 1.2 V

1 V/div

1 V/div 100 mA/div

IIN

VIN

VOUT

IIN

VIN

VOUT

100 120

VOUT−NOM = 1.8 V, VIN = 2.8 V

VOUT−NOM = 3.3 V, VIN = 4.3 V

COUT = 1 mF X7R 0805

VOUT−NOM = 1.2 V

VOUT−NOM = 3.3 V

VOUT−FORCED = VOUT−NOM

VIN = 5.5 V

VEN = 0 V

VOUT−NOM = 1.8 V, VIN = 2.8 V

VOUT−NOM = 3.9 V, VIN = 4.9 V

COUT = 1 mF X7R 0805

Integral Noise:

VOUT−NOM = 1.8 V

10 Hz − 100 kHz: 45 mVrms

10 Hz − 1 MHz: 61 mVrms

VOUT−NOM = 3.9 V

10 Hz − 100 kHz: 52 mVrms

10 Hz − 1 MHz: 68 mVrms

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TYPICAL CHARACTERISTICS

VIN = VOUT−NOM + 0.5 V or VIN = 1.8 V, whichever is greater, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF, TJ = 25°C.

Figure 26. Turn−ON/OFF − VIN driven (slow) Figure 27. Turn−ON − VIN driven (fast)

1 ms/div 20 ms/div

Figure 28. Turn−ON/OFF − EN driven Figure 29. Turn−ON/OFF − EN driven

200 ms/div 200 ms/div

Figure 30. Line Transient Response

10 ms/div

50 mA/div

500 mV/div10 mV/div

VOUT−NOM = 3.9 V

IIN

VIN

VOUT

1 V/div

VOUT−NOM = 3.9 V

100 mA/div1 V/div

VIN

VOUT

VOUT−NOM = 1.2 V

Device with output discharge

VEN

VOUT

50 mA/div 500 mV/div

VOUT−NOM = 1.2 V

VIN

VOUT

1.2 V

tR = tF = 1 ms

Figure 31. Line Transient Response

10 ms/div

500 mV/div10 mV/div

IIN

1 V/div

IIN

50 mA/div 500 mV/div 1 V/div

VOUT−NOM = 1.8 V

Device without output discharge

VEN

VOUT

IIN

1.8 V

2.8 V

VOUT−NOM = 3.9 V

VIN

VOUT

3.9 V

tR = tF = 1 ms

4.4 V

5.4 V

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TYPICAL CHARACTERISTICS

VIN = VOUT−NOM + 0.5 V or VIN = 1.8 V, whichever is greater, VEN = 1.2 V, IOUT = 1 mA, CIN = COUT = 1.0 mF, TJ = 25°C.

Figure 32. Load Transient Response Figure 33. Load Transient Response

10 ms/div 10 ms/div

Figure 34. qJA and PD(MAX) vs. Copper Area

PCB COPPER AREA (mm2)

6005004003002001000

100

120

140

180

200

220

qJA, JUNCTION−TO−AMBIENT

THERMAL RESISTANCE (°C/W)

160

0.2

0.4

0.6

0.8

1.2

1.0

PD(MAX), MAXIMUM POWER DISSIPATION (W)

VOUT−NOM = 1.2 V

VIN

VOUT

1000 mA

1 mA

1.2 V

tR = tF = 1 ms

50 mV/div 500 mA/div

50 mV/div 500 mA/div 1 V/div

VIN

VOUT

1000 mA

3.9 V

tR = tF = 1 ms

IOUT 1 mA

PD(MAX), 2 oz Cu

PD(MAX), 1 oz Cu

qJA, 1 oz Cu

qJA, 2 oz Cu

1 V/div

IOUT

VOUT−NOM = 3.9 V

XDFN8 (AMX/BMX)

TA = 25°C

TJ = 125°C (PD(MAX))

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APPLICATIONS INFORMATION

General

The NCP186 is a high performance 1 A low dropout linear

regulator (LDO) delivering excellent noise and dynamic

performance. Thanks to its adaptive ground current

behavior the device consumes only 90 mA typ. of quiescent

current (no−load condition).

The regulator features low noise of 48 mVRMS, PSRR of

75 dB at 1 kHz and very good line/load transient

performance. Such excellent dynamic parameters, small

dropout voltage and small package size make the device an

ideal choice for powering the precision noise sensitive

circuitry in portable applications.

A logic EN input provides ON/OFF control of the output

voltage. When the EN is low the device consumes as low as

100 nA typ. from the IN pin.

The device is fully protected in case of output overload,

output short circuit condition or overheating, assuring a very

robust design.

Input Capacitor Selection (CIN)

Input capacitor connected as close as possible is necessary

to ensure device stability. The X7R or X5R capacitor should

be used for reliable performance over temperature range.

The value of the input capacitor should be 1 mF or greater for

the best dynamic performance. This capacitor will provide

a low impedance path for unwanted AC signals or noise

modulated onto the input voltage.

There is no requirement for the ESR of the input capacitor

but it is recommended to use ceramic capacitor for its low

ESR and ESL. A good input capacitor will limit the

influence of input trace inductance and source resistance

during load current changes.

Output Capacitor Selection (COUT)

The LDO requires an output capacitor connected as close

as possible to the output and ground pins. The recommended

capacitor value is 1 mF, ceramic X7R or X5R type due to its

low capacitance variations over the specified temperature

range. The LDO is designed to remain stable with minimum

effective capacitance of 0.8 mF. When selecting the capacitor

the changes with temperature, DC bias and package size

needs to be taken into account. Especially for small package

size capacitors such as 0201 the effective capacitance drops

rapidly with the applied DC bias voltage (refer the

capacitor’s datasheet for details).

There is no requirement for the minimum value of

equivalent series resistance (ESR) for the COUT but the

maximum value of ESR should be less than 0.5 W. Larger

capacitance and lower ESR improves the load transient

response and high frequency PSRR. Only ceramic

capacitors are recommended, the other types like tantalum

capacitors not due to their large ESR.

Enable Operation

The LDO uses the EN pin to enable/disable its operation

and to deactivate/activate the output discharge function

(A−version only).

If the EN pin voltage is < 0.4 V the device is disabled and

the pass transistor is turned off so there is no current flow

between the IN and OUT pins. On A−version the active

discharge transistor is active so the output voltage is pulled

to GND through 34 W (typ.) resistor.

If the EN pin voltage is > 1.0 V the device is enabled and

regulates the output voltage. The active discharge transistor

is turned off.

The EN pin has internal pull−down current source with

value of 150 nA typ. which assures the device is turned off

when the EN pin is unconnected. In case when the EN

function isn’t required the EN pin should be tied directly to

IN pin.

Output Voltage

FB/ADJ pin could be connected to the output pin directly

to compensate voltage drop across the internal bond wiring

and PCB traces or to the middle point of the output resistor

divider to adjust the output voltage.

When connected to the output pin the output voltage of the

circuit is simply the same as the nominal output voltage of

the LDO.

When connected to the resistor divider the output voltage

is the nominal output voltage multiplied by the resistors

divider ratio, see following equation. Corresponding

schematic is shown at Figure 1.

VOUT−ADJ +VOUT−NOM @ǒ1)

R2Ǔ(eq. 1)

Where:

•VOUT−ADJ is output voltage of the circuit with resistor

divider

•VOUT−NOM is the LDO’s nominal output voltage

For good stability and fast transient response chose the R1

and R2 values to have their currents IR1 and IR2 in range from

10 to 100 mA. The capacitor C1 = 1 nF improves the stability

and transient response as well.

Output Current Limit

Output current is internally limited to a 1.4 A typ. The

LDO will source this current when the output voltage drops

down from the nominal output voltage (test condition is

VOUT−NOM – 100 mV). If the output voltage is shorted to

ground, the short circuit protection will limit the output

current to 1.4 A typ. The current limit and short circuit

protection will work properly over the whole temperature

and input voltage ranges. There is no limitation for the short

circuit duration.

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Thermal Shutdown

When the LDO’s die temperature exceeds the thermal

shutdown threshold value the device is internally disabled.

The IC will remain in this state until the die temperature

decreases by value called thermal shutdown hysteresis.

Once the IC temperature falls this way the LDO is back

enabled. The thermal shutdown feature provides the

protection against overheating due to some application

failure and it is not intended to be used as a normal working

function.

Power Dissipation

Power dissipation caused by voltage drop across the LDO

and by the output current flowing through the device needs

to be dissipated out from the chip. The maximum power

dissipation is dependent on the PCB layout, number of used

Cu layers, Cu layers thickness and the ambient temperature.

The maximum power dissipation can be computed by

following equation:

PD(MAX) +TJ*TA

qJA

[W] (eq. 2)

Where (TJ − TA) is the temperature difference between the

junction and ambient temperatures and θJA is the thermal

resistance (dependent on the PCB as mentioned above).

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The power dissipated by the LDO for given application

conditions can be calculated by the next equation:

PD+VIN @IGND )ǒVIN *VOUTǓ@IOUT [W] (eq. 3)

Where IGND is the LDO’s ground current, dependent on

the output load current.

Connecting the exposed pad and N/C pin to a large ground

planes helps to dissipate the heat from the chip.

The relation of θJA and PD(MAX) to PCB copper area and

Cu layer thickness could be seen on the Figure 34.

Reverse Current

The PMOS pass transistor has an inherent body diode

which will be forward biased in the case when VOUT > VIN.

Due to this fact in cases, where the extended reverse current

condition can be anticipated the device may require

additional external protection.

Power Supply Rejection Ratio

The LDO features very high power supply rejection ratio.

The PSRR at higher frequencies (in the range above

100 kHz) can be tuned by the selection of COUT capacitor

and proper PCB layout. A simple LC filter could be added

to the LDO’s IN pin for further PSRR improvement.

Enable Turn−On Time

The enable turn−on time is defined as the time from EN

assertion to the point in which VOUT will reach 98% of its

nominal value. This time is dependent on various

application conditions such as VOUT−NOM, COUT and TA.

PCB Layout Recommendations

To obtain good transient performance and good regulation

characteristics place CIN and COUT capacitors as close as

possible to the device pins and make the PCB traces wide.

In order to minimize the solution size, use 0402 or 0201

capacitors size with appropriate effective capacitance.

Larger copper area connected to the pins will also improve

the device thermal resistance. The actual power dissipation

can be calculated from the equation above (Power

Dissipation section). Exposed pad and N/C pin should be

tied to the ground plane for good power dissipation.

ORDERING INFORMATION TABLE

Part Number

Voltage

Option

(VOUT−NOM)Marking Option Package Shipping

NCP186AMX120TAG 1.2 V FA

With active discharge XDFN8

(Pb−Free) 3000 / Tape&Reel

NCP186AMX150TAG 1.5 V FN

NCP186AMX175TAG 1.75 V FC

NCP186AMX180TAG 1.8 V FD

NCP186AMX185TAG 1.85 V FL

NCP186AMX250TAG 2.5 V FE

NCP186AMX280TAG 2.8 V FF

NCP186AMX295TAG 2.95 V FP

NCP186AMX300TAG 3.0 V FG

NCP186AMX330TAG 3.3 V FH

NCP186AMX350TAG 3.5 V FJ

NCP186AMX390TAG 3.9 V FK

NCP186BMX120TAG 1.2 V HA

Without active discharge XDFN8

(Pb−Free) 3000 / Tape&Reel

NCP186BMX150TAG 1.5 V HN

NCP186BMX175TAG 1.75 V HC

NCP186BMX180TAG 1.8 V HD

NCP186BMX185TAG 1.85 V HL

NCP186BMX250TAG 2.5 V HE

NCP186BMX280TAG 2.8 V HF

NCP186BMX300TAG 3.0 V HG

NCP186BMX330TAG 3.3 V HH

NCP186BMX350TAG 3.5 V HJ

NCP186BMX390TAG 3.9 V HK

NCP186AMN080TBG

(In Development) 0.8 V ADJ With active discharge DFN12

(Pb−Free) 3000 / Tape&Reel

NCP186

www.onsemi.com

PACKAGE DIMENSIONS

XDFN8 1.6x1.2, 0.4P

CASE 711AS

ISSUE D

ÍÍÍÍ

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

SEATING

PLANE

DIM

MIN NOM

MILLIMETERS

0.300 0.375

A1 0.000 0.025

b0.130 0.180

PIN ONE

IDENTIFIER

0.08 C

0.10 C

A0.10 C

88X

0.05 C

MOUNTING FOOTPRINT*

1.200 1.300

0.200 0.300

BOTTOM VIEW

8X DIMENSIONS: MILLIMETERS

0.35

8X 0.26

1.40

0.40

PITCH

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

NOTE 3

L0.150 0.200

TOP VIEW

SIDE VIEW RECOMMENDED

0.44

e/2

1.44

PACKAGE

OUTLINE

DETAIL B

DETAIL A

OPTIONAL

CONSTRUCTION

ÉÉ

ÇÇ

DETAIL B

MOLD CMPDEXPOSED Cu

OPTIONAL

CONSTRUCTION

e0.40 BSC

1.500 1.600

1.100 1.200

0.000 0.050

MAX

0.450

0.050

0.230

1.400

0.400

0.250

1.700

1.300

0.100

NCP186

www.onsemi.com

PACKAGE DIMENSIONS

DFN12, 4x4, 0.65P

CASE 506CE

ISSUE O

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ÇÇÇ

PIN ONE

REFERENCE

A B

C0.15

TOP VIEW

C0.15

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMESNION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

BOTTOM VIEW

0.10

12X

0.05

CAB

12 7

12X

(A3) C

C0.08

NOTE 4

C0.10

SIDE VIEW A1

SEATING

PLANE

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.25 0.35

D4.00 BSC

D2 3.30 3.50

E4.00 BSC

E2 2.40 2.60

e0.65 BSC

K0.20 −−−

L0.30 0.50

NOTE 3

4.30

3.54

2.64

0.65

0.63

12X

0.36

12X

DIMENSIONS: MILLIMETERS

PITCH

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

ÉÉÉ

ÇÇÇ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTION

DETAIL B

DETAIL A

0.10 BC

L1 −−− 0.15

NCP186

www.onsemi.com

NCP186/D

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