ICS1562BM-201-4 - Integrated Circuit Systems, Inc.

16-Pin SOIC

Integrated

Circuit

S y stem s, In c.

ICS1562B

Description

The ICS1562B is a very high performance monolithic phase-

locked loop (PLL) frequency synthesizer. Utilizing ICS’s ad-

vanced CMOS mixed-mode technology, the ICS1562B

pro vid es a low cost solution for high-end vide o cloc k ge ne ra-

tion.

The ICS1562B has differential video clock outputs (CLK+ and

CLK-) t hat are com patibl e with indu stry sta ndar d vide o DAC.

Anot her c lo ck output , LOAD, is p rovi de d wh ose fre quenc y is

derived from the main clock by a progra mmable divider. An

addit ional clock output is available, LD/N2, which is derived

from the LOAD frequency and whose modulus may also be

programmed.

Operating frequencies are fully programmable with direct con-

tr ol provi de d for re fere nc e divide r , pre sca ler , fe edba ck di vi der

and post -scaler.

Reset of the pipeline delay on Brooktree RAMDACs may

be performed under register control. Outputs may also be set

to desired states to facilitate circuit board testing.

User Programmable Differential Output Graphics Clock Generator

Features

•Two prog ra mm ing options:

ICS1562B-001 (Parallel Programming)

ICS1562B-201 (Serial Programming )

•Supports high-resolution graphics - CLK output to

26 0 MHz, wit h 400 MHz optio ns ava i labl e

•Eliminate s need fo r multip le ECL output cry stal oscillato rs

•Fully programmable synthesizer capability - not just a

cl ock mult ip lier

•Circuitry included for reset of Brooktree R AMDAC pipe -

line delay

•VRAM shift clock ge nera t ion ca pabi lity

(- 201 op tion only)

•Line-loc ked cloc k genera t ion ca pabili ty

•External feedback l oop ca pabili ty (- 201 op ti on onl y)

•Com pac t - 16-pi n 0.150” skinn y SOIC pa cka ge

•Fully bac kwa rd com pati ble to ICS15 62

CRYSTAL

OSCILLATOR / R PHASE-

FREQUENCY

DETECTOR

CHARGE

PUMP

LOOP

FILTER

VCO

PRESCALER

/ A

/ M

MUX

/ 2

/ 4

/ N1 MUX DRIVER

DIFF.

OUTPUT

DRIVER

/ N2

PROGRAMMING

INTERFACE

CLK+

CLK−

LOAD

LD/N2

XTAL1

XTAL2

ICS1562B - 001 Pinout

ICS1562B - 201 Pinout

Simplified Block Diagram - ICS1562B

FEEDBACK DIVIDER

EXTFBK

BLANK 





(-201 only )

Figure 1

1562 B Rev A 02/2/601

RAMDAC is a trademark of Brooktree Corporati on.

AD0 1 16 AD1

XTAL1 2 15 AD2

XTAL2 3 14 AD3

STROBE 4 13 VDD

VSS 5 12 VDDO

VSS 6 11 IPRG

LOAD 7 10 CLK+

LD/N2 8 9 CLK-

16-Pin SOIC

EXTFBK 1 16 DATA

XTAL1 2 15 HOLD

XTAL2 3 14 BLANK

DATCLK 4 13 VDD

VSS 5 12 VDDO

VSS 6 11 IPRG

LOAD 7 10 CLK+

LD/N2 8 9 CLK-

Overview

The ICS1562B is ideally sui ted to provide the gr aphics system

clock signals required by high-performance video DACs.

Ful ly pr ogram m able fe edba ck a nd r efer en ce di vi de r cap ab ilit y

allow virtually any frequency to be generated, not just simpl e

multiples of the reference frequency. The ICS1562B uses the

latest generati on of frequenc y sy nthesis techniques develope d

by ICS and is completely suitable for the most demanding

vi de o applic at ions.

PLL Synthesizer Description -

Ratiometric Mode

The ICS1562B generates its output frequencies using phase-

locked loop techniques. The phase-locked loop (or PLL) is a

closed-loop feedback system that drives the output frequency

to be ratiometrically related to the reference frequency pro-

vided to the PLL (see Figure 1). The reference frequency is

generated by an on-chip crystal oscillator or the reference

frequency may be appli ed to the ICS1562B from an externa l

frequency source.

The phase-frequency detector shown in the block diagram

drives the voltage-controlled oscillator , or VCO, to a frequency

that will cause the two inputs to the phase-frequency detector

to be ma tc hed in fre quency a nd pha s e . This occurs whe n:

F(XTAL1) . F eedback Di vider

F(VCO): = Reference Divider

This expression is exact; that is, the accuracy of the output

fre quen cy de pends sole ly on t he re fere nce freq uenc y provi de d

to the part (assuming correctly programmed divi ders).

The VCO gain is programmable, which permits the ICS1562B

to be optimized for best performance at all operating frequencies.

The reference divider may be programmed for any modulus

fro m 1 to 128 i n steps of one .

The feedback divider may be programmed for any modulus

fro m 37 throug h 448 in steps of one. Any even mo dul us from

448 through 896 can also be achieved by setting the “double”

bit whic h dou bles th e fe edba ck di vider modul us. The fee dback

divider makes use of a dual-modulus prescaler t echnique that

allows the programmable counters to operate at low speed

without sacrificing resolution. This is an improvement over

conventional fixed prescaler architectures that typically im-

pose a facto r -of- four penal ty (or lar ger) in this respect .

T able 1 permits the derivator of “A” & “M” converter program-

ming d ire c tl y fr o m de si r ed modulus.

PLL Post-Scaler

A programmable post-scaler may be inserted between the VCO

and the CLK+ and CLK- outputs of the ICS1562B. This is

us efu l in ge nera ti ng l ow er fr eque nc ies , as th e VCO has been

opt imi zed fo r hig h-fr eq ue nc y ope ra tion.

The post-scaler allows th e selection of :

•VCO fre que nc y

•VCO fre que nc y di vi ded by 2

•VCO fre que nc y di vi ded by 4

•Inter na l regi ster bit (AUXCL K) va lue

Load Clock Divider

The ICS1562B has an additional programmable divider (re-

fe rred to in Figure 1 a s the N1 divider) that is used to generate

th e LOAD clo ck frequenc y for th e vi de o DAC. The m odul u s

of t hi s d ivide r ma y be s e t to 3, 4, 5, 6 , 8, 10, 1 2, 16 or 2 0 un de r

duty factor to be 50/50, even when an odd mod ulus is selected.

The input frequency to this divider is the output of the PLL

post -sca ler desc rib ed abov e. Addit ion al ly, this di vid er ca n be

di sabl e d unde r re gister cont rol.

Digital Inputs - ICS1562B-001 Option

The AD0-AD3 pins and the STROBE pin are used to load all

control registers of the ICS1562B (-001 option). The AD0-

AD3 and ST ROBE pin s are each e qui ppe d wit h a pull-up an d

will be at a logic HIGH level when not conn ected. They may

be dri ve n wit h standa rd T T L or CMOS logic famili es.

The address of the register to be loaded is latched from the

AD0-AD3 pins by a negative edge on the STROBE p in. The

data for that r egister is l atched from the AD0-AD3 pins by a

positive edge on the STROBE pin. See Figure 2 for a timing

diagram. After power-up, the ICS1562B-001 requires 32 reg-

ister writes for new programming to become effective. Since

onl y 13 re giste rs are used a t present, t he pr ogram m ing system

can perform 19 “dummy” writes to address 13 or 14 to com-

p lete th e se q ue nce.

ICS1562B

Digital Inputs - ICS1562B-201 Option

The program ming of the ICS1562B-201 is performed seria ll y

by using the DATCLK, DATA, and HOLD~pins to load an

internal shift register.

DATA is shifted into the register on the rising edge of

DATCL K. T he l ogi c val ue on the HOLD~pi n i s latc hed a t the

same time. When HOLD~ is low, the shift register may be

loaded without disturbing the operation of the ICS1562B.

When high, the shift register outputs are transferred to the

control registers, and the new programming information be-

comes active. Ordinarily, a high level should be placed on the

HOLD~ pin when the last data bit is presented. See Figure 3

for th e programming sequence.

An addi tiona l con trol pin on the ICS1562B-201, BLANK c a n

perform e ither of two functions. It may be used to disable the

pha se -fre quency det ec t or in line-loc ke d ap plications. Al t e rna-

ti vely, the B LANK pin may be used as a synch ronous enable

for VRAM shift clock generation. See sections on Line-Locked

Operations and VRAM shift clock generation for details.

Output Description

The differential output drivers, CLK+ and CLK, are current-

mode and are designed to drive resistive terminations in a

complementa ry fa sh ion. The outpu ts are current -sinking onl y,

with the amount of sink current programmable via the IPRG

pin. The sink current , which is steered to eith er CL K+or CLK-,

is four times the current supplied to the IPRG pin. For most

applications, a resistor from VDDO to IPRG will set the current

to the necessary precision . Additionally, minor adjustment to

th e duty factor ca n be ach ie ve d und er reg iste r c ont rol.

The LOAD output is a high-current CMOS type drive whose

frequency is controlled by a programmable divider that may be

sel e cted for a modulus of 3, 4, 5, 6, 8, 10, 12, 16 or 20. It may

also be suppressed under register control. The load output may

be p rogramm ed to output the VCO frequ ency di vided b y 2 (see

AUX_N1 description in Register Mapping section), inde-

pendent of the differential output and N1 divider modulus.

The LD/N2 output is high-current CMOS type drive whose

frequ ency is derived from the LOAD output. The programma-

bl e modu lus m ay ran ge from 1 to 512 in steps of on e.

DATA VALIDADDRESS VALID

AD0-AD3

STROBE

ICS1562B-001 Register Loading

Figure 2

DATCLK

DATA

HOLD

DATA_1 DATA_2 DATA_56

ICS1562B-201 Register Loading

Figure 3

This a l lows the synt he siz e r to b e c om plet ely pr ogra m med fo r

the desired frequency before it is made active. Once the part

has bee n “u nlo ck ed ” by the 32 write s, progr am min g be co me s

effect iv e i mm e di at e ly.

ALL registers identified in the data sheet (0-9, 11, 12 & 15)

MUST be written upon initial programming. The programming

registers are not initialized upon power-up, but the latched

outputs of those registers are. The latch is made transparent

afte r 32 register writes. If any registe r has not been written, the

state upon power-up (random) will become effective. Registers

13 & 14 physic a ll y do not exi st . Regi ste r 10 doe s exi st , but is

reserved for future expansion. To insure compatibility with

possible future modifications to the database, ICS recommends

that all thre e unuse d loc ati ons be writte n wi th zero.

ICS1562B

Pipeline Delay Reset Function

The ICS1562B implements the clocking sequence required to

reset the pipeline delay on Brooktree RAMDACs when the

LOAD output is programmed for a modulus of either 3, 4, 5,

6, 8 or 10. This sequence can be generated by setting the

appro priat e registe r bit (DACRST ) to a logi c 1 and then reset -

ting t o log ic 0.

When changing frequencies, it is advisable to allow 500 mi-

croseconds after the new fr equen cy is selected to activate the

re set func tion. The out put freque ncy o f the sy nthesiz er shoul d

be stab le enough at that point for the video DAC to correctly

execute its reset sequence. See Figure 4 for a diagram of the

pipeline delay reset sequence.

Reference Oscillator and Crystal

Selection

The ICS1562B h as c i rc uitry on -b o ar d t o imp le ment a P i er ce

osc il la tor with t he ad dit io n of only one external co mp one nt, a

quartz crystal. Pierce oscillators operate the crystal in anti-

(also called parallel-) resonant mode. See the AC Charac-

teristics for the effective capacitive loading to specify when

or dering cr ystals.

Serie s-resona nt cryst als m ay a lso be use d wit h the ICS1562B.

Be aware that the oscilla tion frequency will be sli ghtly higher

than the frequency that is stamped on the can (typically 0.025-

0.05%).

As th e e nt ire op erat io n o f t he ph ase -lo cked l oop d epen ds on

having a stable referenc e frequency, we recommend that the

crystal be mounted as closely as possible to the package. Avoid

rou ting di gita l signa ls or th e ICS1562B outp uts unde rne ath or

near these traces. It is also desirable to ground the crystal can

to the ground plan e, if po s sible.

If an e xt ernal r efer en ce fr eque ncy source is to be used with t he

ICS1562B. it is important that it be jitter-free. The rising a nd

fall ing edges of tha t signal should be fa st a nd free of noise fo r

be st re sult s.

The loop phase is locked to the falling edges of the XTAL1

input signals if the RE FPOL bit is set to logic 0.

Line-Locked Operation

The ICS1562B supports line-locked clock applications by

allowing the LOAD (N1) and N2 divider chains to act as the

fe e dba c k div ide r fo r the PL L.

The N1 and N2 divi der cha ins all ow a muc h la rge r modulus t o

be achieved than the PLL’s own feedback divider . Additionally ,

the output of the N2 counter is accessible off-chip for perform-

ing horizontal reset of the graphics system, where necessary.

This mode is set under regis ter control (ALTLOOP bit). The

refere nce divi der (R cou nter) will ordina rily be set to divide by

1 i n this mode, and the HSYNC signal of t he ex ternal v ideo

wil l be supplied to the XTAL1 input. Th e ou tput fre qu ency o f

the synt hesizer will then be:

F(CLK) : = F (XTAL1) . N1 . N2.

By using the phase-detector hardware disable mode, the PLL

can be ma de to fr ee-r un at th e be gin nin g o f the ve rti cal i n t e rv al

of the external video, and can be reactivated at its com ple tion.

ICS1562B-001 The ICS1562B-001 supports phase detector

disable via a spec ial control mode. When the

PDRSTE N (pha se dete ctor rese t enable ) bit is

set and the last address latched is 15 (0Fh), a

hi gh l ev el on AD3 wil l disable PL L loc ki ng.

ICS1562B-201 The ICS1562B-201 supports phase detector

disable via the BLANK pin. When the

PDRSTEN bit is set, a high level on the

BLANK inp ut wi ll disa ble PL L locking.

Pipeline Delay Reset Timing

STROBE

DATCLK

CLK+

LOAD

9 11

TCLK

Figure 4

ICS1562B

External Feedback Operation

The ICS1562B-201 option also supports the inclusion of an

exte rnal counte r as the feedback divi der of the PLL. This m ode

is useful in graphic systems that must be “genlocked” to

external vid eo sourc es.

Whe n the EXTFB EN bit i s set to logic 1, t he ph ase-fr equenc y

detector will use the EXTFBK pin as its feedback input. The

loop phase will be locked to the rising edges of the signal applied

to the EXTFBK input if the FBKPOL bit is set to logic 0.

VRAM Shift Clock Generation

The ICS1562B-201 option supports VRAM shift clock gen-

eration and interruption. By programming the N2 counter to

divide by 1, the LD/N2 output becomes a duplicate of the

LOAD output. When the SCEN bit is set, the LD/N2 output

may be synchronously started and stopped via the blank pin.

Whe n BL ANK is high, t he LD/N2 wi ll be free-running and in

phase with LOAD. When BLANK is taken low, the LD/N2

out put is stopp ed a t a low le vel. See Figure 5 f or a diagram o f

the sequence. Note that this use of the BLANK pin precludes its

use for phase c ompa rator disa ble (see Line- Locked Operation ).

Power-On Initialization

The ICS1562B has an internal power-on reset circuit that

performs the foll owing fun ctions:

1) Set s the mu lt iplexe r to pa s s the re fe re nce fr eq uency

to the C LK+ and CL K- outputs.

2) Sele ct s the mo dul us of the N1 di vid er (for t he

LOAD clo ck) to be four.

These functions should allow initialization of most graphics

system s that cannot immedia tely provide for re giste r program-

ming upon system power-up.

Bec ause the powe r -o n reset circ uit is on the VDD suppl y, and

be cau se that suppl y is filtered, c are must be taken to allow the

reset to de-assert before programming. A safe guideline is to

all ow 20 mic rose c onds a fter the VDD supply r eac he s 4 vol ts.

Programming Notes

•VCO Frequ en cy Range : Use the post-d ivide r to kee p the

VCO frequency as high as possible within its operating

range.

•Div ide r Ra nge : For best resul ts in normal situation s (i.e ,

pi xel cloc k gene ra ti on for hi -res displ ay s) , kee p the re fer-

enc e di vi der m od ulus as short a s p os sibl e (f or a fre que ncy

at the output of the referenc e divider in the few hundred

kHz to several MHz range). If you need to go to a lower

phase comparator reference frequency (usually required

for in crea sed frequency accu racy ), that is ac c eptable, but

jit ter perfo rm an ce wil l suffer some wha t.

•VCO Gain Programming: Use the minimum gain which

can reliably achi eve the VCO frequ ency desired, a s shown

on the following page:

VRAM Shift Clock Control

BLANK

LOAD

LD/N2

Figure 5

ICS1562B

Figure 6

VCO GAIN MAX FREQUENCY

4 1 20 MH z

5 2 00 MH z

6 2 60 MH z

*SPECIAL APPL ICATION. Contact factory for custom produ ct above

260 MHz.

•Pha se Detec tor Gain : For most gra phics appl ica tions an d

divider ranges, s et P[1, 0 ] = 10 and set P[2] = 1. Under

some circumstances, setting the P[2] bit “on” can reduce

jitter. During 1562 operation at exact multiples of the

crystal fre quency, P[2] bit = 0 may provide the best jitter

performance.

Board Test Support

It is ofte n desirabl e to statically control the leve ls of the output

pins for circuit board test. The ICS1562B supports this through

a register programmable mode, AUXEN. When this mode is

set, two register bits directly control the logic levels of the

CLK+/CLK- pins and the LOAD pin. This mode is activated

when the S[0] and S[1] bits are both set to logic 1. See Register

Ma ppi ng for deta il s.

Power Supplies and Decoupling

The ICS1562B has two VSS pins to reduce the effects of

package inductance. Both pins are connected to the same

potential on the die (the ground bus). BOTH of these pins

shoul d conne ct to the ground pl ane of the video board as c lose

t o th e package as is possible.

The ICS1562B has a VDDO pin which is the supply of +5 volt

power to all output drivers. This pin should be connected to the

power plane (or bus) using standard high-frequency decou-

pling practice. That is, capacitors should have low series induc-

ta nc e an d be mounted c lose to the ICS1562B.

The VDD pin is the po wer suppl y pin for the PLL synthesiz e r

circuitry and other lower c urrent digital func tions. We recom -

mend that RC decoupling or zener regulation be provided for

t his pin (as sh own in the r ec ommen ded applica tio n ci rcu itry).

This will allow the PLL to “track” through power supply

fluctuations without visible effects. See Figure 6 for typical

external circuitry.

ICS1562B







1AD0 AD1 16

2 XTAL1 AD2 15

3 XTAL2 AD3 14

4 STROBE VDD 13

5 VSS VDDO 12

6VSS IPRG 11

7 LOAD CLK+ 10

8 LD/N2 CLK- 9

+5V

RAMDAC

ICS1562B-001 Typical Interface

820

DATA B US











SELECT LOGIC

1 EXTFBK DATA 16

2XTAL1 HOLD 15

3XTAL2 BLANK14

4 DATCLK VDD 13

5 VSS VDDO 12

6 VSS IPRG 11

7LOAD CLK+ 10

8 LD/N2 CLK- 9

+5V

RAMDAC

ICS1562B-201 Typical Interface

GRAPHICS

CONTROLLER

PROGRAMMING

INTERFACE 





8282

820 820

0.1µF

22µF

0.1µF

510







0.1µF

22µF

0.1µF

510 +5V

0.1µF

+5V







Figure 7

ICS1562B

NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1562B. PC SOFTWARE IS AVAILABLE

FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.

REG# BIT(S) BIT REF. DESCRIPTION

0 0-3 R[0] ..R[ 3] Refe re nc e divi de r modul us con tro l bits

1 0-2 R[4]..R[ 6] Modul us = value + 1

1 3 REFPOL PLL locks to the risin g edge o f XTAL1 input when REFPOL = 1 and

to the fal ling e dge of XTAL1 when REFPOL = 0.

2 0-3 A[0]..A[3] Controls A counter. When set to zer o, modul us=7. Other wise,

mo dul us=7 for “ va lue ” underflows of the pre sca le r, and mo dulus=6

there a fter until M count e r unde rf lows.

3 0-3 M[0]..M[3] M cou nter control bit s

4 0-1 M[4]..M[5] Modul us = value + 1

4 2 FBKPOL Exte rnal f ee dback polarity control bit . The PL L will lock to the fall ing

edge of EXT FBK whe n FBKPOL= 1 and to the risi ng edge of

EXTFBK whe n FBKPOL = 0.

4 3 DBL FRE Q Doubl es modu lus of du al -m odu lus pre sc ale r (fro m 6/7 to 12/1 4).

5 0-3 N1[0]..N1[ 3] Sets N1 mo dulu s according to this tab le . The se bits are set to im ple-

ment a divide -by- four on power -up .

N1[3] N1[2] N1[1] N1[0] RATIO

00003

00014

00104

00115

01006

01018

01108

011110

1X0012

1X0116

1X1016

1X1120

X=Don’ t Care

ICS1562B

REG# BIT(S) BIT REF. DESCRIPTION

6 0-3 N2[0]..N2[ 3] Sets t he modulus of the N2 divid er.

7 0-3 N2[4] ..N2[ 7] The input of the N2 divi de r is the out put of the N1 divi de r in all cloc k

mode s except AUXEN.

8 3 N2[8]

8 0-2 V[0].. V[1] Sets the gain o f the VC O.

9 0-1 P[0]. .P[1] Set s the gain of the pha se de t ec t or acc or ding to this tabl e .

9 3 [P2] Phase de tec to r tuning bit. Norma lly shoul d be set to one .

V[2] V[1] V[0] VCO GAIN

(MHz/VOLT)

100 30

101 45

110 60

111 80

P[1] P[0] GAIN (uA/ra di a n)

00 0.05

01 0.15

10 0.5

11 1.5

10 1 LOADEN~ Load cl oc k divider ena bl e (acti ve low) . Whe n set to logic 1, the

LOAD and L D/N2 outp uts wil l ce ase tog gli ng.

10 2 SKEW- Diffe re nt ial output du ty facto r adjust .

10 3 SKEW + SKEW+ SKEW-

0 0 Default

0 1 Reduces THIGH by approximately

100 ps

1 0 Increases THIGH by approximately

100 ps

1 1 Do not use

ICS1562B

REG# BIT(S) BIT REF. DESCRIPTION

1 1 0-1 S[0]..S[1] PLL post-sc a ler/ test m ode sel ect b its

S[1] S[0] DESCRIPTION

0 0 Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider

drive s the LOAD outp ut whi ch, in tu rn, dri ve s the N2 divide r.

0 1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider

drive s the LOAD outp ut whi ch, in tu rn, dri ve s the N2 divide r.

1 0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divider

drive s the LOAD outp ut whi ch, in tu rn, dri ve s the N2 divide r.

1 1 AUXEN CL OCK MODE . The AUXCLK bit dr ives the di ffe rential

outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD

ou tpu t which, in tur n, d riv es th e N2 di vi der .

1 1 2 AUX_CL K When in the AUXEN cloc k mode, this bit control s the diffe rent ial

outputs.

1 1 3 AUX_N1 When in the AUXEN c lo ck mo de, thi s bit contr ols t he LOAD o utp ut

(and c onse que nt ly t he N2 output ac co rdi ng to its pro gramming) .

When not in the AUXEN cloc k mode, this bit, if set to one, will over -

rid e the N1 divi de r m odul us and out put the VCO fr eq uency di vid ed

by two [F(PLL)/2] at the LOAD output.

12 0 RESERVED Must be set to z ero.

12 1 JAMPLL Trista te s p hase de te c tor output s; resets phase de tector logi c , a nd

resets R, A, M, and N2 counters.

12 2 DACRST Set to zero for norm al ope ra tion. Whe n set to one , th e CLK+ ou tput

is ke pt hi gh a nd t he CLK- outp ut i s kept low. (Al l ot he r de vic e func -

tions ar e un af f ec t ed .) Whe n re tu rne d to ze ro, th e CLK+ a nd CL K-

out puts will resume toggling on a ri si ng edge of the LD output

(+/- 1 CLK pe ri od). To initiate a RAMDAC reset sequ ence,

sim ply writ e a one to this re gi ste r bit fol lowe d by a z er o.

12 3 SEL XTAL When set to log ic 1, passe s the ref er ence fre qu en cy to the post-scale r.

15 0 ALTLO O P Cont rol s substit ut ion o f N1 and N2 div iders into fee dba c k lo op of PL L .

When this bit is a logic 1, the N1 and N2 dividers are used.

15 3 PDRST EN Phase-det ector r eset ena ble co ntrol b it . When this bit is set, the AD3

pin becomes a transparent reset input to the phase detector .

See LINE-LOCKED CLOCK GENERATION section for more

de ta ils o n the ope ra t ion of thi s function.

ICS1562B

NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1562B. PC SOFTWARE IS AVAILABLE

FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.

BIT(S) BIT REF. DESCRIPTION

1-4 N1[0] ..N1[ 3] Sets N1 mod ulus acco rdi ng to thi s tab le. The se bits a re set to im plem e nt

a divi de -by- four on power -up .

N1[3] N1[2] N1[1] N1[0] RATIO

00003

00014

00104

00115

01006

01018

01108

011110

1X0012

1X0116

1X1016

1X1120

5 RESERVED Must be set to zero.

6 JAMPLL Trista tes p ha se de te c tor output s, resets pha se de tec tor logic, and resets

R, A, M, and N2 c ounters.

7 DACRST Set to zero for norm al ope rations. Wh en set to one, the CLK+ output is

ke pt hi gh a nd t he CLK- outp ut i s kept low. (Al l ot he r de vic e func t ion s are

unaffected.) When returned to zero, the CLK+ and CLK- outputs will

resu me to ggl ing on a rising edg e of the LD ou tpu t (+/ −1 CL K p er i od).

To initi ate a RAMDAC rese t sequence , simpl y write a one to this registe r

bit followed by a zero.

8 SEL XTAL When set to log ic 1, passe s the ref eren ce frequency to the post -sc ale r.

9 ALTLO OP Cont rol s substit ut ion o f N1 and N2 div iders into fee dba c k lo op of PL L .

When this bit is a logic 1, the N1 and N2 dividers are used.

10 SCEN VRAM shift cloc k ena ble bit. Whe n logi c 1, the BLANK pi n can be used

to disable the LD/N2 outpu t.

11 EXTFBKEN Exte rna l PLL fee dba c k sel ect . Whe n logic 1, the EXTFB K pin is used for

the phase-frequ en cy d et ect or feedba ck in put.

12 PDRSTEN Phase de tec to r reset ena bl e con tro l bit. Whe n this bi t is set , a high leve l

on the BLANK in put will disabl e PLL locking . See LINE -L OCKE D

CL OCK GENE RAT ION se ct io n for m ore de tai ls on th e op er at io n of

this function.

ICS1562B

BIT(S) BIT REF. DESCRIPTION

13-14 S[0]..S[1] PLL post-scaler/test mode select bits.

S[1] S[0] DESCRIPTION

0 0 Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider

dri ves the LOAD ou tpu t whi ch, in tur n, d riv es th e N2 divi de r.

0 1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider

dri ves the LOAD ou tpu t whi ch, in tur n, d riv es th e N2 divi de r.

1 0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divder

dri ves the LOAD ou tpu t whi ch, in tur n, d riv es th e N2 divi de r.

1 1 AUXEN CLOCK MODE. The AUXCLK bit drives the differential

outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD

out put which, in t urn, drives the N2 di vider.

15 AUX_CL K Wh en in the AUXEN c lock m ode, this bit controls the differential outpu ts.

16 AUX_N1 When in th e AUXEN clo ck mode , this bit contr ols t he N1 output (a nd

co nseq ue ntl y th e N2 ou tpu t acc or ding to its prog ra mm ing). Whe n not in

the AUXE N cloc k mo de , this bit, if set to one , wil l over rid e the N1 divi de r

mo dul us and outp ut t he VCO fre que ncy di vid ed by two [ F(PL L) /2] at the

LOAD output.



17-24 N2[0]..N2[7] Set s the mo dul us of the N2 di vid er. The in put o f the N2 di vi de r is t he

28 N2[8] output of the N1 divid er in all clock mode s except AUXEN.

25-2 7 V[0]. .V[2] Set s t he ga in of VCO ac c ordi ng to t his t able .

V[2] V[1] V[0] VCO GAIN

(MHz/VOLT)

100 30

101 45

110 60

111 80

29-3 0 P[0]. .P[1] Set s the gain of t he phase detect or a ccor ding to this tabl e .

P[1] P[0] GAIN (u A/ra dia n)

00 0.05

01 0.15

10 0.5

11 1.5

31 RESERVED Set to zero.

32 P[2] Phase de tec to r tuning bit. Should norm ally be set to one .

ICS1562B

BIT(S) BIT REF. DESCRIPTION

33-38 M[0]..M[5] M counter control bits

Modulus = val ue +1

39 FBKPOL Exte rna l fee db ac k pola ri ty cont rol bit. The PLL will lock t o the fall ing

edge of EXT FBK whe n FBKPOL= 1 and to the risi ng edge of EXTFB K

when FBKPOL =0.

40 DBL FRE Q Doubl es modu lus of du al -m odu lus pre sc ale r (fro m 6/7 to 12/1 4).

41-44 A[0].. A[3] Controls A coun te r. Whe n se t to zero, m odu lus= 7. Otherwise,

mo dul us=7 for “ va lue ” underflows of the pre sca le r, and mo dulus=6

there a fter until M count e r unde rf lows.

45 RESERVED Set to zero.

46 LOADEN~ Lo ad cloc k div ider ena bl e (active low) . Whe n set to lo gic 1, the LOAD

an d LD/N2 outputs will cea se toggling.

47 SKEW- Diffe re nt ial output du ty facto r adjust .

48 SKEW+

49-5 5 R[0] ..R[ 6] Refere nc e divi de r modul us control bits

Modulus = val ue + 1

56 REFPOL PLL loc ks to the risin g edge of XTAL1 in put when R EFPOL =1 a nd to

the fallin g edge of XTAL1 when REFPOL =0 .

SKEW+ SKEW-

0 0 Default

0 1 Reduc e s T HIGH by approxim ately

100 ps

1 0 Inc reases THIGH by app roxim at e ly

100 ps

1 1 Do not use

ICS1562B

Table 1 - “A” & “M” Divider Programming

Feedback Di vider Modulus Table

A[2]..A[0]- 001 010 011 100 101 110 111 000

M[5]..M[0]

000000 7

000001 13 14

000010 19 20 21

000011 25 26 27 28

000100 31 32 33 34 35

000101 37 38 39 40 41 42

000110 43 44 45 46 47 48 49

000111 49 50 51 52 53 54 55 56

001000 55 56 57 58 59 60 61 63

001001 61 62 63 64 65 66 67 70

001010 67 68 69 70 71 72 73 77

001011 73 74 75 76 77 78 79 84

001100 79 80 81 82 83 84 85 91

001101 85 86 87 88 89 90 91 98

001110 91 92 93 94 95 96 97 105

001111 97 98 99 100 101 102 103 112

010000 103 104 105 106 107 108 109 119

010001 109 110 111 112 113 114 115 126

010010 115 116 117 118 119 120 121 133

010011 121 122 123 124 125 126 127 140

010100 127 128 129 130 131 132 133 147

010101 133 134 135 136 137 138 139 154

010110 139 140 141 142 143 144 145 161

010111 145 146 147 148 149 150 151 168

011000 151 152 153 154 155 156 157 175

011001 157 158 159 160 161 162 163 182

011010 163 164 165 166 167 168 169 189

011011 169 170 171 172 173 174 175 196

011100 175 176 177 178 179 180 181 203

011101 181 182 183 184 185 186 187 210

011110 187 188 189 190 191 192 193 217

011111 193 194 195 196 197 198 199 224

A[2]..A[0]- 001 010 011 100 101 110 111 000

M[5]..M[0]

100000 199 200 201 202 203 204 205 231

100001 205 206 207 208 209 210 211 238

100010 211 212 213 214 215 216 217 245

100011 217 218 219 220 221 222 223 252

100100 223 224 225 226 227 228 229 259

100101 229 230 231 232 233 234 235 266

100110 235 236 237 238 239 240 241 273

100111 241 242 243 244 245 246 247 280

101000 247 248 249 250 251 252 253 287

101001 253 254 255 256 257 258 259 294

101010 259 260 261 262 263 264 265 301

101011 265 266 267 268 269 270 271 308

101100 271 272 273 274 275 276 277 315

101101 277 278 279 280 281 282 283 322

101110 283 284 285 286 287 288 289 329

101111 289 290 291 292 293 294 295 336

110000 295 296 297 298 299 300 301 343

110001 301 302 303 304 305 306 307 350

110010 307 308 309 310 311 312 313 357

110011 313 314 315 316 317 318 319 364

110100 319 320 321 322 323 324 325 371

110101 325 326 327 328 329 330 331 378

110110 331 332 333 334 335 336 337 385

110111 337 338 339 340 341 342 343 392

111000 343 344 345 346 347 348 349 399

111001 349 350 351 352 353 354 355 406

111010 355 356 357 358 359 360 361 413

111011 361 362 363 364 365 366 367 420

111100 367 368 369 370 371 372 373 427

111101 373 374 375 376 377 378 379 434

111110 379 380 381 382 383 384 385 441

111111 385 386 387 388 389 390 391 448

Notes:

To use t hi s tab le, find t he desi re d modulus in the table. Fol low the colu mn up t o fi nd t he A di vi de r prog ra mm i ng va lu es.

Fol low the r ow to the le ft t o find the M div ide r pr ogra m m ing . Some feedback di vi so rs ca n be achi e ve d wit h two or thre e

com bin at ions of di vi de r set tings. Any are ac cept a ble for use .

The formula for the e f fe ct iv e fe e dba c k m odul us is: N =[(M +1) . 6] +A

exc ept whe n A=0, then : N=(M +1) . 7

Unde r all circ um sta nc e s: A ≤ M

ICS1562B

Pin Descriptions - ICS1562B-001

PIN# NAME DESCRIPTION

10 CLK+ Clock ou t (non-inverted)

9CLK

−Clock out (inverted)

7 LOAD Load outp ut. This output is norma lly at the CLK frequenc y d ivided by N1.

2 XTAL 1 Qua rtz crystal con ne ct io n 1/e xt e rnal refe re nc e fre que ncy input

3 XTAL2 Quartz crystal connection 2

1 AD0 Address/Da ta Bit 0 (LSB)

16 AD1 Addre ss/Data Bi t 1

15 AD2 Addre ss/Data Bi t 2

14 AD3 Addre ss/Da ta Bit 3 (MSB)

8 LD/N2 Divi de d L OAD outp ut. See text.

4 STROBE Control for address/data latch

13 VD D PLL system power (+ 5 V. See appli catio n dia gram. )

12 VDDO Output stage powe r (+5V)

11 IPRG Output stage curre nt set

5,6 VSS Devic e groun d. Both pins mu st be conne cte d to the same ground potent ial .

Pin Descriptions - ICS1562B-201

PIN# NAME DESCRIPTION

10 CLK+ Clock ou t (non-inverted)

9CLK

−Clock out (inverted)

7 LOAD Load outp ut. This output is norma lly at the CLK frequenc y d ivided by N1.

2 XTAL 1 Qua rtz crystal con ne ct io n 1/e xt e rnal refe re nc e fre que ncy input

3 XTAL2 Quartz crystal connection 2

4 DATCLK Data Clock (Input)

16 DATA Ser ial Regi ste r Da ta (Input)

15 HOLD~ HOLD (Input)

14 BLA N K Blank ing (Inpu t). See Text.

8 LD/N2 Divi de d L OAD outp ut/ shift cloc k. See text.

1 EXTFBK External feedback connection for PLL (input) . See text.

13 VD D PLL system power (+ 5 V. See appli catio n dia gram. )

12 VDDO Output stage powe r (+5V)

11 IPRG Output stage curre nt set

5,6 VS S Device ground. Both pins mu st be con nect ed.

ICS1562B

Absolute Maximum Ratings

VDD, VDDO (me asu red to V SS). . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Digit al Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS-0.5 to VDD + 0.5 V

Digit al Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS-0.5 to VDDO + +0.5 V

Am bie nt Ope ra ti ng T empe ra t ure. . . . . . . . . . . . . . . . . . . . . . . -55 to 125°C

Sto ra ge T em pe ra ture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C

Junc tion T e mper at ure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C

Soldering Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Recommended Operating Conditions

VDD, VDDO (me asu red to V SS). . . . . . . . . . . . . . . . . . . . . . . 4.75 to 5.25 V

Ope rating Tem perat u r e (Ambient) . . . . . . . . . . . . . . . . . . . . . 0 to 7 0°C

DC Characteristics

TTL-Compatible Inputs

001 Option - (AD0-AD3, STROBE),

201 Option - (DATCLK, DATA, HOL D, BL ANK, EXT FBK)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

Input Hi gh Volta ge Vih 2.0 VDD+0.5 V

Input Low Vol tage Vil VSS-0.5 0.8 V

Input Hig h Curren t Iih Vih=VDD - 10 uA

Input Low Curr en t Iil Vil=0.0 - 200 uA

Input Capa c itan ce Cin -8pf

Hystere sis (ST ROBE /DATCLK) Vhys VDD=5V .20 .60 V

XTAL1 Inp ut

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

Input Hi gh Volta ge Vxh 3.75 VDD+0.5 V

Input Low Vol tage V xl VSS-0.5 1.25

CLK+, CLK- Outputs

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

Different ia l Output Voltag e 0.6 - V

LOAD, LD/N2 Outputs

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

Output Hi gh Volta ge (Ioh = 4.0mA) 2.4 - V

Outp ut L ow Volt a ge (Iol = 8.0mA) - 0.4 V

ICS1562B

AC Characteristics

SYMBOL PARAMETER MIN TYP MAX UNITS

Fvco VCO Frequenc y (se e Note 1) 40 260 MHz

Fxtal Crystal Frequency 5 20 MHz

Cpar Cryst al O scillator L oadi ng Capa cit ance 20 pf

Fload LOAD Fre qu ency 80 MHz

Txhi XTAL1 High Time (whe n driv en ex terna l ly) 8 ns

Txlo XTAL1 Low Time (whe n driven ex terna l ly) 8 ns

Tlock PLL Acquire Time (to within 1%) 500 µs

Idd VDD Supply Current 15 t.b.d. mA

Iddo VDDO Supply Curren t (excludin g CLK+/ −

termination) 20 t.b.d. mA

Thigh Differential Clock Output Duty Cycle

(see Note 2) 45 55 %

Jclk Differe ntia l Clock Out put Cum ul at iv e Jit te r

(see Note 3) <0.06 pixel

DIGITAL INPUTS - ICS1562B-001

1 Addre ss Set up Time 10 ns

2 Address Hold Time 10 ns

3 Dat a Set up T im e 10 ns

4 Data Hold Time 10 ns

5 STROBE Pulse Width (Thi or Tlo)20 ns

DIGITAL INPUTS - ICS1562B-201

6 DATA/HOLD~ Se tup Ti me 10 ns

7 DATA/HOLD~ Hold Time 10 ns

8 DATCLK Pu lse Width (Thi or Tlo)20 ns

PI PELINE DELAY RE SET

9 Reset Activation T ime 2*Tclk ns

10 Reset Duration 4*Tload ns

11 Re sta rt D e la y 2 *T load ns

12 Restart Ma tchi ng -1*Tclk +1.5 *Tclk ns

DIGITAL OUTPUTS

13 CLK+/CLK− Cl ock Ra te 260 MHz

14 LOAD To LD/N2 Skew (Shif t Cloc k Mode) -2 0 +2 ns

Note 1: Use of the post-divider is required for frequencies lower than 40 MHz on CLK+ & CLK- outputs. Use of the post-divider

is recommended for output frequencies lower than 65 MHz.

Note 2: Using load circui t of Figur e 6. Duty cycle measured a t zero crossings of d iffere nce volta ge between CLK+ a n d CLK-.

Note 3: Cumulative jitter is defined as the maximum error (in the domain) if any CLK edge, at any point in time, compared with

th e equivale nt ed ge g en erat e d by a n ide a l fr equenc y so urce.

ICS labora tor y te stin g indi c at e s that the ty pic a l va lue shown ab ove can be tr eat ed as a m a xim um ji tt er sp ec i fic a ti on i n

virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register

programming.

ICS1562B

ICS1562B App licati on Info rmation

Output Circuit Considerations for the ICS1562B

Output Circuitry

The dot cloc k signa ls CLK a nd CLK- a re typic ally the hig hest

frequency signals present in the workstation. To minimize

problems with EMI, crosstalk, and capacitive loading extra

ca re shou l d be tak en in lay in g ou t t his are a of th e P C bo ard .

The ICS1562B is packa ged in a 0.2 ”-wide 16-pi n SOIC pa ck-

age. This permits the clock generator, crystal, and related

components to be laid out in an area the size of a postage stamp.

The ICS1562B should be placed as close as possible to the

RAMDAC. The CLK and CLK- pins are running at VHF

frequencies; one should minimize the length of PCB trace

connecting them to the RAMDAC s o that they don’t become

radi at ors of RF ene r gy.

At t he frequenci es that th e ICS1562B is capable of, P C board

traces may be long enough to be a significant portion of a

wavelength of that frequency. PC traces for CLK and CLK-

should be treated as transmission lines, not just interconnecting

wires. T hese lines can ta ke two forms: micr ostrip and stri pline .

A micro stri p line is shown be low:

Essentially, the microstrip is a copper trace on a PCB over a

ground plane . Typically, the dielectric is G10 glass epoxy. It

differs from a standard PCB trace in that its width is calculated

to have a characteristic impedance. To calculate the charac-

teristic impedance of a microstrip line one must know the width

and thickness of the trace, and the thickness and dielectric

constant of the dielectric. For G10 glass epoxy, the dielectri c

consta nt (er) is abo ut 5. Propag atio n delay i s strictly a fun ctio n

of dielectric constant. For G10 propagation, delay is calculated

t o be 1.7 7 ns/ft.

Str ipl ine i s the ot her f orm a PCB tr an smi ssion l ine ca n take . A

buried trace between ground planes (or be tween a power plane

and a groun d plane ) is com m on in mul ti-la ye r bo ar ds.

Attempting to create a workstation design without the use of

multi-layer boards would be adventurous to say the least, the

issue would more likely be whether to place the interconnect

on the surface or between layers. The between layer approach

would work better from an EMI standpoint, but would be more

di fficul t to l ay out. A stripline is shown bel ow:

Using 1 oz. coppe r ( 0. 0015 ” thi ck) a nd 0.040 ” thic kne s s G10,

a 0.010” trace will exhibit a characteristic impedance of 75Ω

in a stripline confi guration.

Typically, RAMDACs require a Vih of VAA-1.0 Volts as a

guaranteed logical “1” and a Vil of VAA-1.6 as a guaranteed

lo gic a l “0. ” Worst case in put c a pa c it an ce is 1 0 pF.

Output circuitry for the ICS1562B is shown in the following

diagram. It consists of a 4/1 curre nt mirror, and two open drain

out put FETs along wit h inv er ti ng buf f er s to a lt er na te ly enable

eac h c urr en t-si nking drive r. Both CL K an d CL K- outputs are

connected to the respective CLOCK and CLOCK input s of the

RAMDAC with transmission lines and terminated in their

eq uiv al ent i mpe danc es by the Thevenin equivalent impedances

of R1 a nd R2 or R1 ’ and R2 ’.

The ICS1562B is incapable of sourcing current, so Vih must

be se t b y the rati os of these re sistors for ea ch of th ese l ines. R 1

and R2 are electrically in parallel from an AC standpoint

beca use Vdd is bypassed to ground through bypass-capacitor

network Cb. If we p icke d a targ et im peda nce of 75Ω for our

trans mis sion lin e impe danc e, a v alue of 91Ω for R1 and R1’

and a value of 430Ω fo r R 2 a nd R2’ w ould yie ld a Th evin in

equivalent characteristic impedance of 75.1Ω and a Vih valu e

of VAA-.873 Volts, a margin of 0.127 Volts. This may be

adequate; however, at higher frequencies one must contend

with the 10 pF input capacitance of the RAMDAC. Values of

82Ω for R1 and R1’ and 820Ω for R 2 and R2 ’ would g ive us a

cha ract eristic impeda nce of 74.5 Ω and a Vih value of VAA-.45.

With a .55 Volt margin on Vih, this voltage level might be safer .

To set a value for Vil, we must det ermine a value for Iprg that

wil l cause the out put FET’s t o sink an appr opriate c urre nt. We

desire V il to be VAA-1.6 or greater . VAA-2 would seem to be a

saf e valu e. Set ting up a sin k cur rent of 25 m illi ampe res woul d

guarantee this through our 82Ω pull-up resistors. As this is

controlled by a 4/1 current mirror , 7 mA into Iprg should set this

curre nt pro perly. A 51 0Ω resistor fr om V dd to Iprg shoul d work

fine.

Resistors Rt and Rt’ are shown as s eries terminating resistors

at the ICS1562B end of the transmission lines. These are not

required for operation, but may be useful for meeting EMI

r equirem ents . Their int ent is to int erac t with the input capaci-

tance of the RAMDAC and the distributed capacitance of the

transmission line to soften up rise and fall times and conse-

quently cut some of the high-order harmonic content that is

more like ly to radiate RF energy. In actual usage they would

most li ke ly be 10 to 20Ω resistors or possibly ferrite beads.

Cb i s shown as multip le ca pac itors. Typicall y, a 22 µf ta ntal um

should be used with separate .1 µF and 220pf capacitors placed

as close to the pins as possible. This provides low series

inductance capacitors right at the source of high frequency

energy. Rd is used to isolate the circuitry from external

sources of noise. Five to ten ohm s shou ld be adequate.

Great care must be used when evaluating high frequency

circ ui ts to ach ieve me aning ful result s. The 10 p F in put c apac i-

tance and long ground lead of an ordinary scope probe will

make any measurements made with it meaningless. A low

capacitance FET probe with a ground connection directly

connected to the shield at the tip will be required. A 1GHz

bandwidth s cope will be barely adequate, try to find a faster

unit.

ICS1562B Output Circui try

ICS1562B App licati on Info rmation

16-Pin Skinny SOIC Package

Pack age Dimensions

Ordering Information

ICS1562BM-001 or ICS1562BM-201

Example:

ICS 1562B M -XXX

Pattern Number (3 digit number for parts with ROM code patterns)

Package Type

M=SOIC

Devic e Type

Prefix

ICS=Standard

ICS1562B