Am29DL800BB120EC - Advanced Micro Devices

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to hel p you e val uate this product. A MD reserves the right to change or discontin ue work on this proposed

product without notice.

Publicati on# 21519 Rev: AAmendment/+3

Issue Date: April 1998

Am29DL800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flas h Memory

DISTINCTIVE CHARACTERISTICS

■Simultaneous Read/Write operations

— Host system can program or er ase in one bank,

then immediately and simult aneously read from

the other bank

— Zero latency between read and write operations

— Read-while-erase

— Read-while-program

■Single power supply operation

— Full v olt age range : 2.7 to 3.6 volt read and write

operations for battery-powered applications

■Manufactured on 0.35 µm process technology

— Compatible with 0.5 µm Am29DL800 device

■High performan c e

— Access times as fast as 70 ns

■Low current consumption (typical values

at 5 MHz)

— 7 mA active read current

— 21 mA active read-while-program or read-while-

erase current

— 17 mA active program-while-erase-suspended

current

— 200 nA in standby mode

— 200 nA in automatic sleep mode

— Standard tCE chip enab le access time applies to

transition from automatic sleep mode to active

mode

■Flexible sector architecture

— Two 16 Kword, two 8 Kword, four 4 Kword, and

fourteen 32 Kword sectors in word mode

— Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and

fourteen 64 Kbyte sectors in byte mode

— Any combination of sectors can be erased

— Supports full chip erase

■Unlock Bypass Program Comm and

— Reduces overall progr amming time when

issuing multiple program command sequences

■Sector protection

— Hardware method of locking a sector to prevent

any program or erase operation within that

sector

— Sectors can be locked in-system or via

programming equipment

— Temporary Sector Unprotect feature allows code

changes in prev iously locked sectors

■Top or bottom boot block configurations

available

■Embe dded Algorithms

— Embedded Erase algorithm automatically

pre-programs and erases sectors or entire chip

— Embedded Program algorithm automatically

progr ams and verifies data at specified address

■Minimum 1,000,000 program/er ase cycles

guaranteed per sector

■Package options

— 44-pin SO

— 48-pin TSOP

— 48-ball FBGA

■Compatible with JEDEC standar ds

— Pinout and software compatible with

single-power-supply flash standard

— Superior inadvertent write protection

■Data# Polling and Toggle Bits

— Provides a software method of detecting

program or erase cycle completion

■Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or

erase cycle completi on

■Erase Suspend/Erase Resume

— Suspends or resumes erasing sectors to allow

reading and progr amming in other sectors

— No need to suspend if sector is in the other bank

■Hardware reset pin (RESET#)

— Hardware method of resetting the device to

reading array data

2 Am29DL800B

PRELIMINARY

GENERAL DESCRIPTION

The Am29DL800B is an 8 Mbit, 3.0 volt-only flash

memory device, organized as 524,288 words or

1,048,576 bytes. The device is offered in 44-pin SO,

48-pin TSOP, and 48-ball FBGA packages. The word-

wide (x16) data appears on DQ0–DQ15; t he b yte -wide

(x8) data appears on DQ0–DQ7. This device requires

only a single 3.0 volt VCC supply to perform read, pro-

gram, and erase operations. A standard EPROM pro-

grammer can also be used to program and erase the

device.

This device is manufactured using AMD’s 0.35 µm

process technolog y, and off ers all the f eatures and ben-

efits of the Am29DL800, which was manufactured

using a 0.5 µm technology.

The standard de vice offers access times of 70, 90, and

120 ns, allowing high-speed microprocessors to oper-

ate without wait states. Standard c ontrol pins—chip en-

able (CE#), write enable (WE#), and output enable

(OE#)—control read and write operations, and avoid

bus content ion issues.

The de vice requires only a single 3.0 volt power sup-

ply for both read and write functions. Inter nally gener-

ated and regulated voltages are provided for the

program and erase operations.

Sim ultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides si-

multaneous operation by dividing the memory space

into two banks. Bank 1 contains eight boot/parameter

sectors, and Bank 2 consists of four teen larger, code

sectors of unif orm size . The de vice can impro v e o ver all

system perfor mance by allowing a host system to pro-

gram or erase in one bank, then immediately and si-

multaneously read from the other bank, with zero

latency. This releases the system from waiting for the

completion of program or erase operations.

Am29DL800B Features

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

machine that controls the erase and programming

circuitry. Write cycles also internally latch addresses

and data needed for the programming and erase

operations. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprogr ams the arra y (i f it is not already prog rammed)

bef ore ex ecuting the er ase operation. During er ase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by obser ving the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits . After a program or erase cycle has

been completed, the device automatically returns to

reading array data.

The sector erase archite cture all ows m emory sect ors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector within that bank that is

not selected for erasure. True background erase can

thus be achieved. There is no need to suspend the

erase operation if the read data is in the other bank.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading arr a y data. The RESET# pin ma y be tied to the

system reset circuitr y. A system reset would thus also

reset the de vice to reading arra y data, enabling th e sys-

tem microprocessor to read the boot-up fir m ware from

the Flash memory.

The de vice off ers tw o power-saving features . When ad-

dresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also plac e the de v ice into the standby

mode. Power consumption is greatly reduced in both

these modes.

AMD’ s Flash technology combines years of Flash mem-

ory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The

device electrically erases all bits within a sector simulta-

neously via Fowler-Nordheim tunneling. The bytes are

programmed one byte or wo rd at a time using hot elec-

tron injection.

Am29DL800B 3

PRELIMINARY

PRODUCT SELECTOR GUIDE

Note: S ee “AC Characterist ics ” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29DL800B

Speed Option Full Voltage Range: VCC = 2.7 – 3.6 V 70 90 120

Max Access Time (ns) 70 90 120

CE# Access (ns) 70 90 120

OE# Access (ns) 30 35 50

VCC

VSS

Upper Bank Address

A0–A18

RESET#

WE#

CE#

BYTE#

DQ0–DQ15

STATE

CONTROL

COMMAND

RY/BY#

Upper Bank

X-Decoder

Y-Decoder

Latches and Control Logic

OE# BYTE#

DQ0–DQ15

Lower Bank

Y-Decoder

X-Decoder

Latches and

Control Logic

Lower Bank Address

Status

Control

A0–A18

A0–A18A0–A18

DQ0–DQ15 DQ0–DQ15

OE# BYTE# 21519A-1

4 Am29DL800B

PRELIMINARY

CONNECTION DIAGRAMS

A15

A18

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

A15

A18

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

Reverse TSOP

Standard TSOP

21519A-2

Am29DL800B 5

PRELIMINARY

CONNECTION DIAGRAMS

Special Handling Instructions for FBGA

Package

Special handling is required f or Flash Memory products

in FBGA packages.

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be

compromised if the package body is exposed to

temperatures above 150°C for prolonged periods of

time.

RY/BY#

A18

A17

CE#

VSS

OE#

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

RESET#

WE#

A10

A11

A12

A13

A14

A15

A16

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

A1 B1 C1 D1 E1 F1 G1 H1

A2 B2 C2 D2 E2 F2 G2 H2

A3 B3 C3 D3 E3 F3 G3 H3

A4 B4 C4 D4 E4 F4 G4 H4

A5 B5 C5 D5 E5 F5 G5 H5

A6 B6 C6 D6 E6 F6 G6 H6

DQ15/A-1 VSS

BYTE#A16A15A14A12A13

DQ13 DQ6DQ14DQ7A11A10A8A9

VCC DQ4DQ12DQ5NCNCRESET#WE#

DQ11 DQ3DQ10DQ2NCA18NCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# VSS

CE#A0A1A2A4A3

21519A-3

FBGA

Bump Side (Bottom) View

6 Am29DL800B

PRELIMINARY

PIN DESCRIPTION

A0-A18 = 19 Addresses

DQ0-DQ14= 15 Data Inputs/Outputs

DQ15/A-1 = DQ15 (Data Input/Output, word mode),

A-1 (LSB Address Input, byte mode)

CE# = Chip Enable

OE# = Ou tput Enable

WE# = Write Enable

BYTE# = Selects 8-bit or 16-bit mode

RESET# = Hardware Reset Pin, Activ e Low

RY/BY# = Ready/Busy Output

VCC = 3.0 v olt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

VSS = Device Ground

NC = Pin Not Connected Internally

LOGIC SYMBOL

21519A-4

19 16 or 8

DQ0–DQ15

(A-1)

A0–A18

CE#

OE#

WE#

RESET#

BYTE# RY/BY#

Am29DL800B 7

PRELIMINARY

ORDERING INFORMATION

Standard Pr o ducts

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in v olume for this device. Consult the local AMD sales

office to confirm a vailability of specific valid combinations and

to check on newly released combinations.

DEVICE NUM BE R/ DES CR IPT IO N

Am29DL800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Am29DL800B 70 E C

OPTIONAL PROCESSING

Blank = Standard Pro ces sin g

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

S = 44-Pin Small Outline Package (SO 044)

WB = 48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 9 mm package

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

Valid Combinations

Am29DL800BT70

Am29DL800BB70 EC, EI, FC, FI,

SC, SI, WBC, WBI

Am29DL800BT90

Am29DL800BB90 EC, EI, EE,

FC, FI, FE,

SC, SI, SE,

WBC, WBI, WBE

Am29DL800BT120

Am29DL800BB120

8 Am29DL800B
PRELIMINARY 
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is a latch used to store the
commands, along with the address and data infor ma-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels the y requ ire,  and t he resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29DL800B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 
± 
0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector 
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0-15 are active and controlled by CE#
and OE# .
If the BYTE# pin is set at logic ‘0’, the device is in byte
configurat ion, and only data I/O pins  DQ0–DQ7 are ac-
tive and controlled by CE# and OE#.  The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at VIH. The BYTE# pin determines whether the
device outputs array data in words or bytes.
The internal state machine is set for reading array
data upon de vic e po wer-up, or after a hardw are reset .
This ensures that no spur ious alteration of the me m-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert v alid addresses  on th e device  addres s input s pro-
duce v alid dat a on the de vice data  outputs.  EAch bank
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing spec-
ifications and to Figure 13 for the timing diagram. ICC1
in the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
Operation CE# OE# WE# RESET# Addresses
(Note 1) DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE# 
= VIL
Read L L H H AIN DOUT DOUT DQ8–DQ14 = High-Z, 
DQ15 = A-1
Write L H L H AIN DIN DIN
Standby VCC ± 
0.3 V XXV
CC ± 
0.3 V X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
Sector Protect (Note 2) L H L VID
Sector Ad dre ss, 
A6 = L, A1 = H, 
A0 = L DIN XX
Sector Unp rot ect  (Note 2) L H L VID
Sector Ad dre ss, 
A6 = H, A1 = H, 
A0 = L DIN XX
Temporary Sector Unprotect X X X VID AIN DIN DIN High-Z

Am29DL800B 9
PRELIMINARY
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether
the de vice acc epts progr am data in b ytes or words . Ref er to
“Wo rd/Byte Confi gurat ion” f or more inf ormation. 
The device features an Unlock Bypass m ode to facili-
tate f aster programming. Once a bank enters the Unlock
Bypass mode, only two write cycles are required to pro-
gram a word or byte, instead of four. The “Byte/Word
Program Command Sequence” section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.
An erase oper at ion can er ase  one sect or, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. The device
address space is divided into two banks: Bank 1 con-
tains the boot/parameter sectors, and Bank 2 contains
the larger, code sectors of uniform size. A “bank ad-
dress” is the address bits required to uniquely select a
bank. Similarly, a “sector address” is the address bits
required to uniquely select a sector.
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections f or more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The AC
Characteristics section contains timing specifica tion ta-
bles and timing diagrams for write operations.
Sim ultaneous Read/Write Operations with 
Zero Latency
This dev ice is capable of reading data from one bank of
memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank  (ex cept the s ector being er ased).
Figure 19 shows how read and write cycles may be in-
itiated for simultaneous operation with zero latency.
ICC6 and ICC7 in t he DC Charact erist ics table  represent
the current specifications for read-while-program and
read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the de vice,
it can place the device in the standby mode. In this
mode,  current  con sumption is g reat ly  reduced,  and  the
outputs are placed in the high impedance state, inde-
pendent of the OE# input. 
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) I f CE# and  RESET# are hel d at  VIH, b ut not within
VCC ± 0.3  V, the de vice will be in the stand by mode,  b ut
the standb y current will  be greater. The de vice requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification. 
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy  consumption. The dev ice automatically  enables
this mode when addresses remain stable f or tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE#  control signals. St andard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.

10 Am29DL800B

PRELIMINARY

RESET#: Hardware Reset Pin

The RESET# pin pro vides a har dware method of reset-

ting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of tRP

, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all read/

write commands for t he dur ation of t he RESET# pulse .

The device also resets the internal state machine to

reading array data. The operation that was interrupted

should be reinitiated once the de vice is ready to accept

another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC4). If RESET# is held

at VIL b ut not within VSS±0.3 V, the standby current will

be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up

firmware from the Flash memory.

If RESET# is ass erted during a progr am or er ase oper-

ation, the RY/BY# pin remains a “0” (busy) until the in-

ternal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor R Y/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during Embedded Algo-

rithms). The system can read data tRH after the RE-

SET# pin retur ns to VIH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the de vice is

disabled. The output pins are plac ed in the h igh imped-

ance state.

Am29DL800B 11

PRELIMINARY

Table 2. Am29DL800BT Top Boot Sector Architecture

Note: The address range is A18:A-1 if in byte mode (BYTE# = VIL). The address range is A18:A0 if in word mode (BYTE# = VIH).

Bank Sector

Sector Address Sector Size

(Kbytes/

Kwords) (x8)

Address Range (x16)

Address Range

Bank Address

A15 A14 A13 A12A18 A17 A16

Bank 2

SA0 0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh

SA1 0 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh

SA2 0 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh

SA3 0 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh

SA4 0 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh

SA5 0 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh

SA6 0 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh

SA7 0 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh

SA8 1 0 0 0 X X X 64/32 80000h–8FFFFh 40000h–47FFFh

SA9 1 0 0 1 X X X 64/32 90000h–9FFFFh 48000h–4FFFFh

SA10 1 0 1 0 X X X 64/32 A0000h–AFFFFh 50000h–57FFFh

SA11 1 0 1 1 X X X 64/32 B0000h–BFFFFh 58000h–5FFFFh

SA12 1 1 0 0 X X X 64/32 C0000h–CFFFFh 60000h–67FFFh

SA13 1 1 0 1 X X X 64/32 D0000h–DFFFFh 68000h–6FFFFh

Bank 1

SA14 1 1 1 0 0 0 X 16/8 E0000h–E3FFFh 70000h–71FFFh

SA15111001X 32/16 E4000h–E7FFFh,

E8000h–EBFFFh 72000h–73FFFh

74000h–75FFFh

10X

SA16 1 1 1 0 1 1 0 8/4 EC000h–EDFFFh 76000h–76FFFh

SA17 1 1 1 0 1 1 1 8/4 EE000h–EFFFFh 77000h–77FFFh

SA18 1 1 1 1 0 0 0 8/4 F0000h–F1FFFh 78000h–78FFFh

SA19 1 1 1 1 0 0 1 8/4 F2000h–F3FFFh 79000h–79FFFh

SA20111101X 32/16 F4000h–F7FFFh,

F8000h–FBFFFh 7A000h–7BFFFh

7C000h–7DFFFh

10X

SA21 1 1 1 1 1 1 X 16/8 FC000h–FFFFFh 7E000h–7FFFFh

12 Am29DL800B

PRELIMINARY

Table 3. Am29DL800BB Bottom Boot Sector Architecture

Note: The address range is A18:A-1 if in byte mode (BYTE# = VIL). The address range is A18:A0 if in word mode (BYTE# = VIH).

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended f or programming equipment

to automatically match a de vice to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

When using programming equipment, the autoselect

mode requires VID (11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Table 4. In addition, when verifying sector protection,

the sector address must appear on the appropriate

highest order address bits (see Tables 2 and 3). Table

4 shows the remaining address bits that are don’t ca re.

When all necessary bits ha ve been set as require d, the

programming equipment may then read the corre-

sponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 5. This method

does not require VID. Refer to the Autoselect Command

Sequence section for more information.

Bank Sector

Sector Address Sector Size

(Kbytes/

Kwords) (x8)

Address Range (x16)

Address Range

Bank Address

A15 A14 A13 A12A18 A17 A16

Bank 2

SA211111XXX 64/32 F0000h–FFFFFh 78000h–7FFFFh

SA20 1 1 1 0 X X X 64/32 E0000h–EFFFFh 70000h–77FFFh

SA19 1 1 0 1 X X X 64/32 D0000h–DFFFFh 68000h–6FFFFh

SA18 1 1 0 0 X X X 64/32 C0000h–CFFFFh 60000h–67FFFh

SA17 1 0 1 1 X X X 64/32 B0000h–BFFFFh 58000h–5FFFFh

SA16 1 0 1 0 X X X 64/32 A0000h–AFFFFh 50000h–57FFFh

SA15 1 0 0 1 X X X 64/32 90000h–9FFFFh 48000h–4FFFFh

SA14 1 0 0 0 X X X 64/32 80000h–8FFFFh 40000h–47FFFh

SA13 0 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh

SA12 0 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh

SA11 0 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh

SA10 0 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh

SA9 0 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh

SA8 0 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh

Bank 1

SA7 0 0 0 1 1 1 X 16/8 1C000h–1FFFFh 0E000h–0FFFFh

SA6 0 0 0 1 10X 32/16 18000h–1BFFFh

14000h–17FFFh 0C000h–0DFFFh

0A000h–0BFFFh

01X

SA5 0 0 0 1 0 0 1 8/4 12000h–13FFFh 09000h–09FFFh

SA4 0 0 0 1 0 0 0 8/4 10000h–11FFFh 08000h–08FFFh

SA3 0 0 0 0 1 1 1 8/4 0E000h–0FFFFh 07000h–07FFFh

SA2 0 0 0 0 1 1 0 8/4 0C000h–0DFFFh 06000h–06FFFh

SA1 0 0 0 0 10X 32/16 08000h–0BFFFh,

04000h–07FFFh 04000h–05FFFh,

02000h–03FFFh,

01X

SA0 0 0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh

Am29DL800B 13

PRELIMINARY

Table 4. Am29DL800B Autoselect Codes (High Voltage Method)

Note: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both

progr am and er ase opera tions in an y sect or. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

The primary method requires VID on the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 24 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must

first be prote cted prior to the firs t sector unprotec t write

cycle.

The alternate method intended only for programming

equipment requires VID on address pin A9 and OE#.

This method is compatible with programmer routines

written f or earlier 3.0 v olt-only AMD flash de vi ces. Pub-

lication number 21467 contains further details; contact

an AMD representative to request a copy.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possib le to determine whether a sector is protected

or unprotected. See the Autoselect Mode section for

details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sect ors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to VID (11.5 V – 12.5 V). During this mode,

formerly protected sectors can be programmed or

erased by selecting the sector addresses. Once VID is

removed from the RESET# pin, all the previously pro-

tected sectors are prot ected again. Figure 1 sho ws the

algorithm, and Figure 23 shows the timing diagrams,

for this feature.

Figure 1. Temporary Sector Unprotect Operation

Description Mode CE# OE# WE#

A18

A12

A11

A10 A9

A7 A6

A2 A1 A0

DQ8

DQ15

DQ7

DQ0

Manufacturer ID: AMD L L H BA X VID XLXLL X 01h

Device ID:

Am29DL800B

(Top Boot Block)

Word L L H BA X VID XLXLH22h 4Ah

Byte L L H X 4Ah

Device ID:

Am29DL800B

(Bottom Boot Block)

Word L L H BA X VID XLXLH22h CBh

Byte L L H X CBh

Sector Protection Verification L L H SA X VID XLXHL X01h

(protected)

X00h

(unprotected)

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

21519A-5

14 Am29DL800B

PRELIMINARY

Figure 2. In-System Sector Protect/Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode No

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

21519A-6

Am29DL800B 15
PRELIMINARY
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and
pow er-down transitions, or from system noise.
Low V CC Write Inhibit
When VCC is less than VLKO, the device does not  accept
any write cycles. This protects data during VCC
power-up and p ower-down. Th e comm and register and
all internal  program/erase circuits are disable d, and the
device  resets to reading array data. Subs equent writes
are ignore d until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to
prevent unintentional writes when VCC is greater than
VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical In hibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH  or WE# = VIH. To initiate a wr ite cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up , the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates de vice op-
erations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data. 
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Ref er to the appropriate t iming diagrams in the  A C
Cha ract eristi cs section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Er ase Suspend command,
the corresponding bank enters the erase-suspend-
read mode, after which the system can read data from
any non-erase-suspended sector within the same
bank. After comple ting a progr amming  operation in the
Erase Suspend mode, the system may once again
read arra y data with the same exception. See the Er ase
Suspend/Erase Resume Commands section for more
information.
The sys tem  
must
 issue the reset command to return a
bank to the  read  (or er ase-s uspend-read) mode  if  DQ5
goes high during an active pr ogram or erase oper ation,
or if the bank is in the autoselect mode. See the next
section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa-
rameters, and Figure 13 shows the timing  diagram.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the bank to which the sys-
tem was writing to reading array data. Once erasure
begins, however, the device ignores reset commands
until the operation is complete .
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the bank to
which the system was writing to the reading arr ay data.
If the progr am command sequence is written to a bank
that is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-sus pend-read
mode. Once prog r amming begins , ho wever, the dev ice
ignores reset commands until the operation is com-
plete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the aut oselect mode , the re set command mus t
be written to return to reading array data. If a bank en-
tered the autoselect mode while in the Erase Suspend
mode, writing the reset command retur ns that bank to
the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to reading
array data (or erase-suspend-read mode if that bank
was in Erase Suspend).

16 Am29DL800B

PRELIMINARY

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the man uf acture r and devices codes,

and determine whether or not a sector is protected.

Table 5 shows the address and data requirements . This

method is an alternativ e to that shown in Tabl e 4, which

is intended for PROM programmers and requires VID

on address pin A9. The autoselect command sequence

may be written to an address within a bank that is either

in the read or erase-suspend-read mode. The autose-

lect command may not be written while the device is

actively programming or erasing in the other bank.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

toselect command. The addressed bank then enters

the autoselect mode. The system may read at any ad-

dress within the same bank any number of times with-

out initiating another autos elect command sequence:

■A read cycle at address (BA)XX00h (where BA is

the bank address) returns the manufacturer code.

■A read cycle at address (BA)XX01h in word mode

(or (BA)XX02h in byte mode) returns the device

code.

■A read cycle to an address containing a sector ad-

dress (SA) within the same bank, and the address

02h on A7–A0 in word mode (or the addres s 04h on

A6–A-1 in byte mode) returns 01h if the sector is

protected, or 00h if it is unprotec ted. Refer to Tab les

2 and 3 for valid sector addresses.

The system may continue to read array data from the

other bank while a bank is in the autoselect mode. To

exit the autoselect mode, the system must write the

reset command to return both banks to reading array

data. If a bank enter s the autoselect mode while erase

suspended, a reset command returns that bank to the

erase-suspend-read mode. A subsequent Erase

Resume command returns the bank to the er ase oper-

ation.

Byte/Word Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by wr iting two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is

not

required to provide further controls or t im-

ings. The device automatically generates the program

pulses and verifies the programmed cell margin. Table

5 shows the address and data requirements for the

byte program command sequence.

When the Embedded Program algorithm is complete,

that bank then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation b y using DQ7,

DQ6, or RY/BY#. Note that while the Embedded Pro-

gram operation is in progress, the system can read

data from the non-programming bank. Refer to the

Write Opera tion Status section f or information on these

status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The prog ram command sequence should be

reinitiated once that b ank has returned to reading arra y

data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may cause

that bank to set DQ5 = 1, or cause the DQ7 and DQ6

status bits to indicate the operation was successful.

However, a succeeding read will show that the data is

still “0.” Only erase operations can conver t a “0” to a

“1.”

Unlock Bypass Command Sequen ce

The unlock bypass feature allows the system to pro-

gram bytes or words to a bank faster than using the

standard progr am command sequenc e. The un lock by-

pass command sequence is initiated b y first writing two

unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. That

bank then enters the unloc k b ypas s mode. A two-cycle

unlock bypass program command sequence is all that

is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program

command, A0h; the seco nd cycle contains the progr am

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time . Table 5 sho ws the re quirements for the com-

mand sequence.

During the unlock bypass mode, only the Unlock Bypass

Program and Unlock Bypass Reset commands are

valid. To exit the unlock bypass mode, the system must

issue the two-cycle unlock bypass reset command se-

quence. The first cycle must contain the bank address

and the data 90 h. The second cycle need only con tain

the data 00h. The bank then returns to reading array

data.

Am29DL800B 17
PRELIMINARY
Figure 3 illustrates the algorithm for the program oper-
ation. Ref er to the Erase and Prog ram Operation s tab le
in the AC Characteristics section for parameters, and
Figure 17 for timing diagrams.
Note: See Table 5 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six  b us cy cle oper ation.  The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles ar e then followed b y the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does 
not
 require the system to
preprogram prior  to erase. The Embedded Er ase  algo-
rithm automatically preprogr ams a nd v e rifies the entire
memor y for an all zero data pattern prior to electrical
erase. The  system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
When the Embedded Er ase algorithm is c omplete , that
bank returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the e rase operat ion b y using DQ7, DQ6,  DQ2, or
R Y/BY#. Refer to the Write Operation Status section for
information on these status  bits.
Any commands written during the chip er ase operation
are ignored. However, note that a hardware reset im -
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once that b ank has returned to reading arra y
data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Ref er to t he Erase and Prog ram Oper ations tab les
in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed
by t he address  of the s ector t o be er ased,  and t he sec-
tor erase command. Table 5 shows the address and
data requirements for the sector erase command se-
quence. 
The device does 
not
 require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations. 
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
ma y be done in any sequence ,  and the number of sec-
tors ma y be from one sector to al l sectors. The time be-
tween these additional cycl es must be less than 50 µs,
otherwise the last address and command may not be
accepted, and erasure may begin. It is recommended
that processor  interrupts be disab led during this time to
ensure all commands are accepted. The inte rrupts can
be re-enabled after the last Sector Erase command is
wr itten.  Any command other than Sector Erase or
Erase Suspend during the time-out period resets
that bank to reading array  data. The system must re-
write the command sequence and any additional ad-
dresses and commands.
The system can monitor DQ3 (in the erasing bank) to
deter mine if the sector erase time r has timed out (See
the section on DQ3: Sector Erase Timer.). The time-out
begins from the rising edge of the final WE# pulse in the
command sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase
operation is  in progress , the system can read  data from
START
Write Program
Command Sequence
Data Poll 
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
 Completed
Increment Address
Embedded 
Program
algorithm
 in progress
21519A-7

18 Am29DL800B
PRELIMINARY 
the non-erasing bank. The system can determine the
status of the erase operation by reading DQ7, DQ6,
DQ2, or R Y/BY# in the er asing bank. Ref er to the Write
Operation Status section for infor mation on these sta-
tus bits.
Once the sector erase operation has begun, only the
Erase Suspend command is v alid. All oth er commands
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the sector erase command sequence should be
reinitiated once that  bank has returned to reading ar ra y
data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Ref er to the Erase and Program Operation s tab les
in the AC Characteristics section for parameters, and
Figure 18 section for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then
read data f rom, or p rog r a m dat a to, any sect or no t se-
lected f or e rasure . The bank addres s is requ ired when
writing this c ommand. This command is v alid only d ur-
ing the sector erase operation, including the 50 µs
time-out period during the sector erase command se-
quence. The Erase Suspend command is ignored if
written during the chip erase operation or Embedded
Program algorithm. 
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and  suspends the
erase operation. 
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The sys-
tem can read data from  or program data to any sector
not selected f or eras ure. (The de v ice “erase suspends”
all sectors selected for erasure.) Reading at any ad-
dress within erase- suspended sectors produces status
information on DQ7–DQ0. The system can use DQ7,
or DQ6 and DQ2 together, to determine if a sector is
actively erasing or is erase-suspended. Refer to the
Write Operation  Status section f or inf ormation on these
status bits.
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The  system can de termine the status of t he pro-
gram operation using the DQ7 or DQ6 status bits, just
as in the standard  Byte Program oper ation. Ref er to the
Write Operation Status section for more information.
In the erase-suspend-read mode, the system can also
issue the autoselect command s equence. Refe r to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector  erase operation , the system  must
write the Erase Resume command. The  bank address
of the erase-suspended bank is  required when writing
this command. Further writes of the  Resume command
are ignored. Another Eras e Suspend command can be
written after the chip has resumed erasing. 
Notes:
1. See Table 5 for erase command sequence.
2. See the section on DQ3 for information on the sector 
erase timer.
Figure 4. Erase Operation
START
Write Erase 
Command Sequence
(Notes 1, 2)
Data Poll to Erasing 
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded 
Erase
algorithm
in progress
21519A-8

Am29DL800B 19
PRELIMINARY
Table 5. Am29DL800B Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read. 
RD = Data read from location RA during read op eration.
PA = Address of the me mory location to be programmed. 
Addresses latch on the falling edge of the WE# or CE# pulse, 
whichever happens later.
PD = Data to be progr ammed at location PA. Data latches on the 
rising edge of WE#  or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or 
erased. Address bits A18–A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect 
mode, is in bypass mode, or is being erased. Address bits A18–
A16 select a bank.
Notes:
1. See Table 1  for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles 
are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command 
cycles.
5. Address bits A18–A11 are don’t cares for unlock and 
command cycles, unless bank address (BA) is required.
6. No unlock or command cycles required when bank is in read 
mode.
7. The Reset command is requ ired to return to reading array 
data (or to the erase-suspend-read mode if previously in 
Erase Suspend) when a bank is in the autoselect mode, or if 
DQ5 is goes high (while the bank is providing status 
information).
8. The fourth cycle of the autoselect command sequence is a 
read cycle. The system must provide the bank address to 
obtain the ma nufacturer or device ID information.
9. The data is 00h for an unprotected sector and 01h for a 
protected sector. See the Autoselect Command Sequence 
section for more information.
10. The Unlock Bypass command is required prior to the Unlock 
Bypass Program command.
11. The Unlock Bypass Reset command is required to return to 
reading array data when the bank is in the unlock bypass 
mode.
12. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend mode. 
The Erase Suspend command is valid only during a sector 
erase operation, and requires the bank address.
13. The Erase Resume command is valid only during the Erase 
Suspend mode, and requires the bank address.
Command
Sequence
(Note 1)
Bus Cycles (Notes 2–5)
First Second Third  Fourth  Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Manufacturer ID Word 4555 AA 2AA 55 (BA)555 90 (BA)X00 01
Byte AAA 555 (BA)AAA
Device ID, 
Top Boot Block  Word 4555 AA 2AA 55 (BA)555 90 (BA)X01 224A
Byte AAA 555 (BA)AAA (BA)X02 4A
Device ID,
Bottom Boot Block Word 4555 AA 2AA 55 (BA)555 90 (BA)X01 22CB
Byte AAA 555 (BA)AAA (BA)X02 CB
Sector Protect 
Verify (Note 9)
Word 4555 AA 2AA 55 (BA)555 90
(SA)
X02 XX00
XX01
Byte AAA 555 (BA)AAA (SA)
X04 00
01
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program  (Not e 1 0) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2 BA 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 12) 1 BA B0
Erase Resume (Note 13) 1 BA 30
Cycles
Autoselect (Note 8)

20 Am29DL800B

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation in the bank where a progr am or

erase operation is in progress: DQ2, DQ3, DQ5, DQ6,

DQ7, and RY/BY#. Table 6 and the following subsec-

tions describe the func tion of thes e bits. DQ7, RY/BY#,

and DQ6 each offer a method for determining whether

a program or erase operation is complete or in

progress . These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Program or Erase algo-

rithm is in progress or completed, or whether a bank is

in Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the command sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is activ e f or ap-

proximately 1 µs, then that bank returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When t he Embedded Erase al-

gorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address w ithin any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

After an er ase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then the

bank returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected s ector ,

the status may not be valid.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is , the de v ice ma y change fr om pro viding sta-

tus information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ0–DQ6 may be still

inv alid. Valid data on DQ0–DQ7 will appear on succes-

siv e read cycles.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm. Figure 20

in the A C Characteristics sec tion shows the Dat a# P oll-

ing timing diagram.

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

21519A-9

Am29DL800B 21
PRELIMINARY
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output,  sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the outpu t is low (Busy ), the de vice is activ ely er asing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the de v ice is ready t o read array data, is in the standby
mode, or one of the banks is in the erase-suspend-read
mode.
Table 6 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Er ase algorithm is in prog ress or complete ,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address within
the progr amming  or er asing bank , and is  valid afte r the
rising edge of the final WE# pulse i n the command se-
quence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address within
the progr amming or eras ing bank cause DQ6 to tog gle.
The system may use either OE# or CE# to control the
read cycles. When the operation is complete, DQ6
stops toggling.
After an er ase command sequence is written,  if all sec-
tors selected f or er asing are protected , DQ6 toggles f or
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
protected. 
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When a bank is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When that bank enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then retur ns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 6 sho ws the out puts for Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm. Figure 21 in the
“AC Char acteristics” section sho ws the t oggle bit timing
diagrams. Figure 22 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is , the  Embedded Er ase algo rithm is in progr ess),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that  have been selected for eras-
ure. (The s ystem ma y use  either OE#  or CE# to  control
the read cycles.) But DQ2 cannot distinguish whether
the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot dis-
tinguish which sectors are selected for erasure. Thus,
both status bits are required for sector  and mode infor-
mation. Refer to Table 6 to compare outputs for DQ2
and DQ6. 
Figure 6 shows the toggle bit algorithm in flowchart
for m, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 21 shows the toggle bit timing diagram. Figure
22 shows the differences between DQ2 and DQ6 in
graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the follo wing discussion. Whene v er
the system initially begins reading toggle bit status, it
must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
first read. After the second read, the system would  com-
pare the new value of the toggle bit with the first. If the
toggle bit is not toggling , the device has comple ted  the
program or erase operation. The system can read arra y
data on DQ7–DQ0 on the follo wing  read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may  have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not

22 Am29DL800B

PRELIMINARY

completed the operation successfully, and the system

must write the reset command to return to reading

array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is togglin g and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successiv e read cycles , de-

termining the stat us as described in the previous par a-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it re turns to determine

the status of the operation (top of Figure 6).

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

Figure 6. Toggle Bit Algorithm

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1,” indicating that

the program or erase cycle was not successfully com-

pleted.

The de vi ce may output a “1” on DQ5 if the s yst em tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the oper at ion, and when t he t iming limi t has been

exceeded, DQ5 produces a “1”.

Under both these co nditions, th e system must write the

reset command to return to reading array data (or to the

erase-suspend-read mode if a bank was previously in

the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip eras e command.) If addit ional sectors

are selected for erasure, the entire time-out also ap-

plies after each additional sector erase command.

When the time-out period is complete, DQ3 switches

from a “0” to a “1”. If the system can guar antee the time

between additional sector erase commands to be less

than 50 µs, it need not monitor DQ3. See also the Sec-

tor Erase Command Sequence section.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence , an d then read DQ3. If DQ3 is

“1”, the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0”, the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase command.

If DQ3 is high on the second status check, the last com-

mand might not have been accepted.

Table 6 shows the status of DQ3 relative to the other

status bits.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Am29DL800B 23

PRELIMINARY

Table 6. Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. When reading write operation status bits, the system must alwa ys provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

Status DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2) RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Erase-Suspend-

Read

Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

24 Am29DL800B

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#,

and RESET# (Note 2). . . . . . . . .–0.5 V to +12.5 V

All other pins

(Note 1). . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may undershoot VSS

to –2.0 V for periods of up to 20 ns. Maximum DC voltage

on input or I/O pins is VCC +0.5 V. See Figure 7. During

voltage transitions, input or I/O pins may overshoot to VCC

+2.0 V for periods up to 20 ns. See Figure 8.

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

RESET# may undershoot VSS to –2.0 V for periods of up

to 20 ns. See Figure 7. Maximum DC input voltage on pin

A9 is +12.5 V which may overshoot to 14.0 V for periods

up to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these

or any other conditions above those indicated in the opera-

tional sections of this data sheet is not implied. Exposure of

the device to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

Figure 7. Maximum Negative

Overshoot Waveform

Figure 8. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°C

VCC Supply Voltages

VCC for full voltage range. . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

21519A-11

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

21519A-12

Am29DL800B 25
PRELIMINARY
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Erase or Embedded Program is in progress.
3. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode 
current is 200 nA.
4. Not 100% tested.
Parameter 
Symbol Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, 
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC, 
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current 
(Note 1)
CE# = VIL, OE# = VIH, 
Byte Mode 5 MHz 7 12 
mA
1 MHz 2 4
CE# = VIL, OE# = VIH, 
Word Mode 5 MHz 7 12
1 MHz 2 4
ICC2 VCC Active Write Current
(Note 2) CE# = VIL, OE# = VIH, WE# = VIL 15 30 mA
ICC3 VCC Standby Current
(CE# Contro lled ) VCC = VCC max; OE# = VIL;
CE#, RESET# = VCC ± 0.3 V 0.2 5 µA
ICC4 VCC Reset Current 
(RESET# Controlled) VCC = VCC max; 
RESET# = VSS ± 0.3 V 0.2 5 µA
ICC5 Automatic Sleep Mode (Note 3) VIH = VCC ± 0.3 V; 
VIL = VSS ± 0.3 V 0.2 5 µA
ICC6 VCC Active Read-While-
Program Current (Notes 1, 4) CE# = VIL, 
OE# = VIH
Byte 21 45 mA
Word 21 45
ICC7 VCC Active Read-While-Erase 
Current (Notes 1, 4) CE# = VIL, 
OE# = VIH
Byte 21 45 mA
Word 21 45
ICC8
VCC Active Program-While-
Erase-Suspended Current 
(Note 4)
CE# = VIL, 
OE# = VIH 17 35 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VID Voltage for Autoselect and 
Temporary Sector Unprotect VCC = 3.0 V ± 10% 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min  0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4 V
VLKO Low VCC Lock-Out Voltage 
(Note 4) 2.3 2.5 V

26 Am29DL800B

PRELIMINARY

DC CHARACTERISTICS

Zero-Power Flash

00 500 1000 1500 2000 2500 3000 3500 4000

Supply Curren t i n mA

Time in ns

Note: Addresses are switching at 1 MHz

21519A-13

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

12345

Frequency in MHz

Supply Current in mA

Note: T = 25

21519A-14

Figure 10. Typical ICC1 vs. Frequency

2.7 V

3.6 V

Am29DL800B 27

PRELIMINARY

TEST CONDITIONS

Table 7. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

3.3 V

Device

Under

Test

21519A-15

Figure 11. Test Setup

Note: Diodes are IN3064 or equivalent

Test Condition All Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement reference

levels 1.5 V

Output timing measurement

reference levels 1.5 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changi ng from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput

21519A-16

Figure 12. Input Waveforms and Measurement Levels

28 Am29DL800B

PRELIMINARY

AC CHARACTERISTICS

Read-Only Operations

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test specifications.

Parameter

Description Test Setup

Speed Options

JEDEC Std. 70 90 120 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 70 80 120 ns

tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 70 80 120 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 80 120 ns

tGLQV tOE Output Enable to Output Delay Max 30 35 50 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 25 30 30 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 25 30 30 ns

tAXQX tOH Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First Min 0 ns

tOEH Output Enable Hold

Time (Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tOH

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tRH

tOE

tRH

0 V

RY/BY#

RESET#

tDF

21519A-17

Figure 13. Read Operation Timings

Am29DL800B 29

PRELIMINARY

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Descri ptio n All Speed Optio ns UnitJEDEC Std

tReady RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note) Max 20 µs

tReady RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH Reset High Time Before Read (See Note) Min 50 ns

tRPD RESET# Low to Standby Mode Min 20 µs

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

21519A-18

Figure 14. Reset Timings

30 Am29DL800B

PRELIMINARY

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

70 90 120JEDEC Std. Description Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 25 30 30 ns

tFHQV BYTE# Switching High to Output Active Min 70 90 120 ns

DQ15

Output

Data Output

(DQ0–DQ7)

CE#

OE#

BYTE#

tELFL

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Output

(DQ0–DQ7)

BYTE#

tELFH

DQ0–DQ14 Data Outpu t

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFHQV

BYTE#

Switching

from byte

to word

mode

21519A-19

Figure 15. BYTE# Timings for Read Operations

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

21519A-20

Figure 16. BYTE# Timi ngs for Write Operations

CE#

WE#

BYTE#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

Am29DL800B 31

PRELIMINARY

AC CHARACTERISTICS

Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter

70 90 120JEDEC Std. Description Unit

tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns

tAVWL tAS Address Setup Time Min 0 ns

tASO Address Setup Time to OE# low during toggle bit polling Min 45 45 50 ns

tWLAX tAH Address Hold Time Min 45 45 50 ns

tAHT Address Hold Time From CE# or OE# high

during toggle bit polling Min 0 ns

tDVWH tDS Data Setup Time Min 35 45 50 ns

tWHDX tDH Data Hold Time Min 0 ns

tOEPH Output Enable High during toggle bit polling Min 20 20 25 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 35 35 50 ns

tWHDL tWPH Write Pulse Width High Min 30 ns

tSR/W Zero Latency Between Read and Write Operations Min 0 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs

Word Typ 11

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

tRB Write Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

32 Am29DL800B

PRELIMINARY

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tGHWL

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

tRB

tBUSY

tCH

Notes:

1. PA = program address, PD = program data, DOUT is the true data at the program address.

2. Illustration shows device in word mode

21519A-21

Figure 17. Program Operation Timings

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tGHWL

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

RY/BY#

tRB

tBUSY

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

. Illustrat ion shows device in word mode.

21519A-22

Figure 18. Chip/Sector Erase Operation Timings

Am29DL800B 33

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

Data

Valid

In Valid

Valid PA Valid RA

WPH

Valid

Out

ACC

OEH

GHWL

Valid

CE# Controlled Write CyclesWE# Controlled Write Cycle

Valid PA Valid PA

CPH

Read Cycle

SR/W

21519A-23

Figure 19. Back-to-Back Read/Write Cycle Timings

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

21519A-24

Figure 20. Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

34 Am29DL800B

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

tOEH

tDH

tAHT

tASO

tOEPH

tOE

Valid Data

(first read) (second read) (stops toggling)

tCEPH

tAHT

tAS

DQ6/DQ2 Valid Data

Valid

Status Valid

Status

RY/BY#

Note: V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle

21519A-25

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

Note: DQ2 toggles only when read at an address within an erase-suspended sector . The system may use OE# or CE# to toggle

DQ2 and DQ6.

21519A-26

Figure 22. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Pro gra m

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

Am29DL800B 35

PRELIMINARY

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std. Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

tRRB RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect Min 4 µs

RESET#

tVIDR

12 V

0 V or 3 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 V or 3 V

tRRB

21519A-27

Figure 23. Temporary Sector Unprotect Timing Diagram

36 Am29DL800B

PRELIMINARY

Sector Protect: 100 µs

Sector Unprotect: 10 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Protect/Unprotect Verify

VID

VIH

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

21519A-28

Figure 24. Sector Protect/Unprotect Timing Diagram

Am29DL800B 37

PRELIMINARY

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter

70 90 120JEDEC Std. Description Unit

tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns

tAVWL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 45 45 50 ns

tDVEH tDS Data Setup Time Min 35 45 50 ns

tEHDX tDH Data Hold Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 35 35 50 ns

tEHEL tCPH CE# Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation

(Note 2) Byte Typ 9 µs

Word Typ 11

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

38 Am29DL800B

PRELIMINARY

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data, DQ7# = complement of the data written to the device,

DOUT = data written to the device.

3. Waveforms are for the word mode.

21519A-29

Figure 25. Alternate CE# Controlled Erase/Program Operation Timings

Am29DL800B 39

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 5 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 sec Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 14 sec

Byte Program Time 9 300 µs

Excludes system level

overhead (Note 5)

Word Program Time 11 360 µs

Chip Program Time

(Note 3) Byte Mode 9 27 sec

Word Mode 5.8 17

Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE #, and RESE T#) –1.0 V 12.5 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Description Test Conditions Min Unit

Minimum Pa ttern Data Retent ion Time 150°C 10 Years

125°C 20 Years

40 Am29DL800B

PRELIMINARY

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP (measured in millimeters)

* For reference only. BSC is an ANSI standard for Basic Space Centering

TSR048—48-Pin Reverse TSOP (measured in millimeters)

* For reference only. BSC is an ANSI standard for Basic Space Centering.

18.30

18.50

19.80

20.20

11.90

12.10

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48-2

TS 048

DT95

8-8-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

18.30

18.50

19.80

20.20

11.90

12.10

SEATING PLANE

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48

TSR048

DT95

8-8-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

Am29DL800B 41

PRELIMINARY

PH YSICAL DIMENSI ONS (continued)

FGB048 —48-ball Fine-Pitch Ball Grid Array (FBGA), 6 x 9 mm (measured in mm)

5.80

6.20

8.80

9.20

DATUM B

DATUM A

INDEX

0.025

CHAMFER

0.15 MZBM

5.60

BSC

0.40

4.00

BSC

0.08 MZAB

0.10 Z

0.25

0.45

0.80

DETAIL A

0.20 Z

DETAIL A

1.20 MAX

0.40 ± 0.08 (48x) 0.40

16-038-FGB-2

EG137

12-2-97 lv

42 Am29DL800B

PRELIMINARY

PH YSICAL DIMENSI ONS (continued)

SO 044—44-Pin Small Outline (measured in millimeters)

44 23

122

13.10

13.50 15.70

16.30

1.27 NOM.

28.00

28.40

2.17

2.45

0.35

0.50 0.10

0.35

2.80

MAX. SEATING

PLANE

16-038-SO44-2

SO 044

DF83

8-8-96 lv

0.10

0.21

0.60

1.00

0°

8°

END VIEW

SIDE VIEW

TOP VIEW

Am29DL800B 43

PRELIMINARY

REVISION SUMMARY FOR AM29DL800B

Revision A+1

Reset Command

Deleted last parag raph in section, which applied to RE-

SET#, not the reset command.

Revision A+2

Hard ware Reset (RESET#)

Added note to table, fixed ref erences to note.

Revision A+3

Global

Removed references to the 80 ns speed option.

Changed the 70R ns (VCC ± 5%) speed option to the

70 ns (VCC ± 10%) speed option.

Figure 2, In-System Sector Protect/U nprotect

Algorithms

In the sector protect algorithm, added a “Reset

PLSCNT=1” box in the pa th from “Pr otect ano ther sec-

tor?” back to setting up the next sector address.

DQ6: Toggle Bit I

In the first and second paragraphs, clarified that the

toggle bit may be read “at any address within the pro-

gra mming or erasing bank,” no t “at an y address.” In the

fourth paragraph, clarified “device” to “bank.”

DC Charact eristics

Added reference to Note 4 on ICC6 and ICC7 specifica-

tions.

AC Characteristics

Erase/Program Operations; Alternate CE# Controlled

Erase/Program Operations:

Corrected the notes refe r-

ence for tWHWH1 and tWHWH2. These parameters are

100% tested. Corrected the note reference for tVCS.

This parameter is not 100% tested.

Temporary Sector Unprotect Table

Added note reference for tVIDR. This parameter is not

100% tested.

Figure 24, Sector Protect/Unprotect Timing

Diagram

A valid address is not required for the first write cycle;

only the data 60h.

Erase and Programming Performance

In Note 2, the worst case endurance is now 1 million cy-

cles.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.