KAI-08052 3296 (H) x 2472 (V) Interline CCD Image Sensor Description The KAI-08052 Image Sensor is an 8-megapixel, 4/3" optical format CCD that provides increased Quantum Efficiency (particularly for NIR wavelengths) compared to members of the standard 5.5 mm family. The sensor shares the same broad dynamic range, excellent imaging performance, and flexible readout architecture as other members of the 5.5 mm pixel family. But QE at 820 nm has been approximately doubled compared to existing devices, enabling enhanced sensitivity without a corresponding decrease in the Modulation Transfer Function (MTF) of the device. The KAI-08052 is available with the Sparse Color Filter Pattern, which provides a 2x improvement in light sensitivity compared to a standard color Bayer part. The KAI-08052 is drop-in compatible with the KAI-08051 Image Sensor, simplifying adoption by camera manufacturers currently working with the KAI-08051. Table 1. GENERAL SPECIFICATIONS Parameter www.onsemi.com Figure 1. KAI-08052 CCD Image Sensor Features Typical Value * Increased QE, with 2x Improvement Architecture Interline CCD; Progressive Scan Total Number of Pixels 3364 (H) x 2520 (V) Number of Effective Pixels 3320 (H) x 2496 (V) Number of Active Pixels 3296 (H) x 2472 (V) Pixel Size 5.5 mm (H) x 5.5 mm (V) Active Image Size 18.13 mm (H) x 13.60 mm (V) 22.66 mm (diag), 4/3" optical format Aspect Ratio 4:3 Number of Outputs 1, 2, or 4 Charge Capacity 20,000 electrons Output Sensitivity 35 mV/e- Quantum Efficiency Pan (-ABA, -QBA) R, G, B (-FBA, -QBA) 48%, 12%, 5% (535, 850, 920 nm) 42%, 41%, 38% (615, 535, 460 nm) Read Noise (f = 40 MHz) 10 e- Dark Current Photodiode / VCCD 1 / 70 electrons/s * * * * * at 820 nm Bayer Color, Sparse Color, and Monochrome Configurations Progressive Scan Readout Flexible Readout Architecture High Sensitivity, Low Noise Architecture Excellent Smear Performance Applications * Scientific and Medical Imaging * Intelligent Transportation Systems * Machine Vision ORDERING INFORMATION Dark Current Doubling Temp. Photodiode / VCCD 7C / 9C Dynamic Range 66 dB Charge Transfer Efficiency 0.999999 Blooming Suppression > 300 X Smear -100 dB Image Lag < 10 electrons Maximum Pixel Clock Speed 40 MHz Maximum Frame Rates Quad / Dual / Single Output 16 / 8 / 4 fps Package 68 pin PGA Cover Glass AR coated, 2 Sides or Clear Glass See detailed ordering and shipping information on page 2 of this data sheet. NOTE: All parameters are specified at T = 40C unless otherwise noted. (c) Semiconductor Components Industries, LLC, 2016 July, 2016 - Rev. 0 1 Publication Order Number: KAI-08052/D KAI-08052 ORDERING INFORMATION Table 2. ORDERING INFORMATION Part Number Description KAI-08052-ABA-JD-BA Monochrome, Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Standard Grade KAI-08052-ABA-JD-AE Monochrome, Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade KAI-08052-ABA-JP-BA Monochrome, Telecentric Microlens, PGA Package, Taped Clear Cover Glass, no coatings, Standard Grade KAI-08052-ABA-JP-AE Monochrome, Telecentric Microlens, PGA Package, Taped Clear Cover Glass, no coatings, Engineering Grade KAI-08052-FBA-JD-BA Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Standard Grade KAI-08052-FBA-JD-AE Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade KAI-08052-QBA-JD-BA Gen2 Color (Sparse CFA), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Standard Grade KAI-08052-QBA-JD-AE Gen2 Color (Sparse CFA), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR coating (both sides), Engineering Grade Marking Code KAI-08052-ABA Serial Number KAI-08052-FBA Serial Number KAI-08052-QBA Serial Number See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAI-08052 DEVICE DESCRIPTION Architecture H2Bd H2Sd H1Bd H1Sd SUB H2Bc H2Sc H1Bc H1Sc RDc Rc VDDc VOUTc RDd Rd VDDd VOUTd IIIIIIIIIIIIIIIIIIIIIIII EEEEEEEEEEEEEEEEEEEEEE HLOD 1 10 22 12 8 1648 1648 12 8 22 10 1 1 Dummy 12 12 GND OGc H2SLc V1T V2T V3T V4T GND OGd H2SLd V1T V2T V3T V4T DevID ESD 3296H x 2472V 5.5 mm x 5.5 mm Pixels 22 12 12 22 V1B V2B V3B V4B RDa Ra VDDa VOUTa V1B V2B V3B V4B EEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEE IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII 12 Buffer 12 Dark 1 Dummy (Last VCCD Phase = V1 H1S) 1 10 22 12 8 1648 1648 HLOD H2Bb H2Sb H1Bb H1Sb SUB H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa ESD 12 8 22 10 1 RDb Rb VDDb VOUTb GND OGb H2SLb Figure 2. Block Diagram (Monochrome - No Filter Pattern) Dark Reference Pixels Active Buffer Pixels There are 12 dark reference rows at the top and 12 dark rows at the bottom of the image sensor. The dark rows are not entirely dark and so should not be used for a dark reference level. Use the 22 dark columns on the left or right side of the image sensor as a dark reference. Under normal circumstances use only the center 20 columns of the 22 column dark reference due to potential light leakage. 12 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. These pixels are light sensitive but are not tested for defects and non-uniformities. Image Acquisition An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. Dummy Pixels Within each horizontal shift register there are 11 leading additional shift phases. These pixels are designated as dummy pixels and should not be used to determine a dark reference level. In addition, there is one dummy row of pixels at the top and bottom of the image. www.onsemi.com 3 KAI-08052 ESD Protection power-down sequences may cause damage to the sensor. See Power-Up and Power-Down Sequence section. Adherence to the power-up and power-down sequence is critical. Failure to follow the proper power-up and Bayer Color Filter Pattern H2Bd H2Sd H1Bd H1Sd SUB H2Bc H2Sc H1Bc H1Sc IIIIIIIIIIIIII EEEEEEEEEEEEEE RDc Rc VDDc VOUTc RDd Rd VDDd VOUTd HLOD 1 10 22 12 8 1648 1648 12 8 22 10 1 1 Dummy 12 12 GND OGc H2SLc BG G R V1T V2T V3T V4T BG G R GND OGd H2SLd V1T V2T V3T V4T DevID ESD 3296H x 2472V 5.5 mm x 5.5 mm Pixels 22 12 V1B V2B V3B V4B 12 22 ESD V1B V2B V3B V4B BG G R 12 Buffer 12 Dark 1 Dummy (Last VCCD Phase = V1 H1S) BG G R EEEEEEEEEEEEEE IIIIIIIIIIIIII RDa Ra VDDa VOUTa 1 10 22 12 8 1648 1648 RDb Rb VDDb VOUTb 12 8 22 10 1 HLOD GND OGb H2SLb H2Bb H2Sb H1Bb H1Sb SUB H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa Figure 3. Bayer Color Filter Pattern Sparse Color Filter Pattern H2Bd H2Sd H1Bd H1Sd SUB H2Bc H2Sc H1Bc H1Sc IIIIIIIIIIIIII IIIIIIIIIIIIII EEEEEEEEEEEEEE RDc Rc VDDc VOUTc RDd Rd VDDd VOUTd HLOD 1648 1 10 22 12 8 1648 12 8 22 10 1 1 Dummy 12 12 GND OGc H2SLc G P B P V1T V2T V3T V4T P G P B R P G P P R P G G P B P P G P B R P G P P R P G GND OGd H2SLd V1T V2T V3T V4T DevID ESD 22 12 V1B V2B V3B V4B RDa Ra VDDa VOUTa G P B P P G P B R P G P P R P G 12 22 G P B P P G P B R P G P ESD V1B V2B V3B V4B P R P G EEEEEEEEEEEEEE IIIIIIIIIIIIII 12 Buffer 12 Dark 1 Dummy (Last VCCD Phase = V1 H1S) 1 10 22 12 8 1648 1648 HLOD H2Bb H2Sb H1Bb H1Sb SUB H2Ba H2Sa H1Ba H1Sa GND OGa H2SLa 3296H x 2472V 5.5 mm x 5.5 mm Pixels Figure 4. Sparse Color Filter Pattern www.onsemi.com 4 12 8 22 10 1 RDb Rb VDDb VOUTb GND OGb H2SLb KAI-08052 PHYSICAL DESCRIPTION Pin Description and Device Orientation 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 V3T V1T VDDc GND Rc H2SLc H1Bc H2Sc N/C H2Sd H1Bd H2SLd Rd GND VDDd V1T V3T 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 ESD V4T V2T VOUTc RDc OGc H2Bc H1Sc SUB H1Sd H2Bd OGd RDd VOUTd V2T V4T DevID Pixel (1,1) 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 V4B V2B VOUTa RDa OGa H2Ba H1Sa SUB H1Sb H2Bb OGb RDb VOUTb V2B V4B ESD 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 V3B V1B VDDa GND Ra H2SLa H1Ba H2Sa N/C H2Sb H1Bb H2SLb Rb GND VDDb V1B V3B Figure 5. Package Pin Designations - Top View www.onsemi.com 5 KAI-08052 Table 3. PIN DESCRIPTION Description Pin Name Description 68 ESD ESD Protection Disable Pin Name 1 V3B Vertical CCD Clock, Phase 3, Bottom 67 V3T Vertical CCD Clock, Phase 3, Top 3 V1B Vertical CCD Clock, Phase 1, Bottom 66 V4T Vertical CCD Clock, Phase 4, Top 4 V4B Vertical CCD Clock, Phase 4, Bottom 65 V1T Vertical CCD Clock, Phase 1, Top 5 VDDa Output Amplifier Supply, Quadrant a 64 V2T Vertical CCD Clock, Phase 2, Top VDDc Output Amplifier Supply, Quadrant c Video Output, Quadrant c 6 V2B Vertical CCD Clock, Phase 2, Bottom 63 7 GND Ground 62 VOUTc 8 VOUTa Video Output, Quadrant a 61 GND Ground 9 Ra Reset Gate, Quadrant a 60 RDc Reset Drain, Quadrant c 10 RDa Reset Drain, Quadrant a 59 Rc Reset Gate, Quadrant c 11 H2SLa Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a 58 OGc Output Gate, Quadrant c 57 H2SLc Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c 12 OGa Output Gate, Quadrant a 13 H1Ba Horizontal CCD Clock, Phase 1, Barrier, Quadrant a 56 H2Bc Horizontal CCD Clock, Phase 2, Barrier, Quadrant c 14 H2Ba Horizontal CCD Clock, Phase 2, Barrier, Quadrant a 55 H1Bc Horizontal CCD Clock, Phase 1, Barrier, Quadrant c 15 H2Sa Horizontal CCD Clock, Phase 2, Storage, Quadrant a 54 H1Sc Horizontal CCD Clock, Phase 1, Storage, Quadrant c 16 H1Sa Horizontal CCD Clock, Phase 1, Storage, Quadrant a 53 H2Sc Horizontal CCD Clock, Phase 2, Storage, Quadrant c 17 N/C No Connect 52 SUB Substrate N/C No Connect 18 SUB Substrate 51 19 H2Sb Horizontal CCD Clock, Phase 2, Storage, Quadrant b 50 H1Sd Horizontal CCD Clock, Phase 1, Storage, Quadrant d 20 H1Sb Horizontal CCD Clock, Phase 1, Storage, Quadrant b 49 H2Sd Horizontal CCD Clock, Phase 2, Storage, Quadrant d 21 H1Bb Horizontal CCD Clock, Phase 1, Barrier, Quadrant b 48 H2Bd Horizontal CCD Clock, Phase 2, Barrier, Quadrant d 22 H2Bb Horizontal CCD Clock, Phase 2, Barrier, Quadrant b 47 H1Bd Horizontal CCD Clock, Phase 1, Barrier, Quadrant d 23 H2SLb Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant b 46 OGd Output Gate, Quadrant d 45 H2SLd 24 OGb Output Gate, Quadrant b 25 Rb Reset Gate, Quadrant b 44 RDd Reset Drain, Quadrant d 26 RDb Reset Drain, Quadrant b 43 Rd Reset Gate, Quadrant d 27 GND Ground 42 VOUTd 28 VOUTb Video Output, Quadrant b 41 GND Ground 29 VDDb Output Amplifier Supply, Quadrant b 40 V2T Vertical CCD Clock, Phase 2, Top 30 V2B Vertical CCD Clock, Phase 2, Bottom 39 VDDd V4T Vertical CCD Clock, Phase 4, Top Vertical CCD Clock, Phase 1, Top 31 V1B Vertical CCD Clock, Phase 1, Bottom 38 32 V4B Vertical CCD Clock, Phase 4, Bottom 37 V1T 33 V3B Vertical CCD Clock, Phase 3, Bottom 36 DevID 34 ESD ESD Protection Disable 35 V3T Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d Video Output, Quadrant d Output Amplifier Supply, Quadrant d Device Identification Vertical CCD Clock, Phase 3, Top 1. Liked named pins are internally connected and should have a common drive signal. 2. N/C pins (17, 51) should be left floating. www.onsemi.com 6 KAI-08052 IMAGING PERFORMANCE Table 4. TYPICAL OPERATION CONDITIONS Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions. Condition Description Notes Light Source Continuous red, green and blue LED illumination Operation Nominal operating voltages and timing For monochrome sensor, only green LED used. Table 5. SPECIFICATIONS All Configurations Description Dark Field Global Non-Uniformity Symbol Min. Nom. Max. Units DSNU - - 2.0 mVpp Die 27, 40 - 2.0 5.0 %rms Die 27, 40 1 - 5.0 15.0 %pp Die 27, 40 1 - 1.0 2.0 %rms Die 27, 40 1 Bright Field Global Non-Uniformity Bright Field Global Peak to Peak Non-Uniformity Temperature Tested At (5C) Sampling Plan PRNU Bright Field Center Non-Uniformity Notes Maximum Photoresponse Nonlinearity NL - 2 - % Design 2 Maximum Gain Difference Between Outputs DG - 10 - % Design 2 Maximum Signal Error due to Nonlinearity Differences DNL - 1 - % Design 2 Horizontal CCD Charge Capacity HNe - 55 - ke- Design - ke- Design ke- Die Vertical CCD Charge Capacity Photodiode Charge Capacity VNe - 40 PNe - 20 - Horizontal CCD Charge Transfer Efficiency HCTE 0.999995 0.999999 - Die 27, 40 Vertical CCD Charge Transfer Efficiency VCTE 0.999995 0.999999 - Die Photodiode Dark Current Ipd - 1 70 e/p/s Die 40 Vertical CCD Dark Current Ivd - 70 300 e/p/s Die 40 e- Design 3 Image Lag Lag - - 10 Antiblooming Factor Xab 300 - - Vertical Smear Smr - -100 - dB Design Design 4 4, 5 Design Read Noise ne-T - 10 - e-rms Dynamic Range DR - 66 - dB Design Output Amplifier DC Offset Vodc - 9.1 - V Die Output Amplifier Bandwidth f-3db - 250 - MHz Die Output Amplifier Impedance ROUT - 127 - W Die Output Amplifier Sensitivity DV/DN - 35 - mV/e- Design 27, 40 6 27, 40 1. Per color 2. Value is over the range of 10% to 90% of photodiode saturation. 3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is 800 mV. 4. At 40 MHz 5. Uses 20LOG (PNe/ ne-T) 6. Assumes 5 pF load. www.onsemi.com 7 KAI-08052 Table 6. KAI-08052-ABA AND KAI-08052-QBA CONFIGURATIONS WITH MAR GLASS Symbol Min. Nom. Max. Units Sampling Plan Peak Quantum Efficiency QEmax - 48 - % Design Peak Quantum Efficiency Wavelength lQE - 535 - nm Design Quantum Efficiency (850 nm) QEmax - 12 - % Design Quantum Efficiency (920 nm) QEmax - 5 - % Design Description Temperature Tested At (5C) Notes Temperature Tested At (5C) Notes Temperature Tested At (5C) Notes Table 7. KAI-08052-ABA CONFIGURATIONS WITH TAPED CLEAR GLASS Symbol Min. Nom. Max. Units Sampling Plan Peak Quantum Efficiency (No Glass) QEmax - 48 - % Design Peak Quantum Efficiency Wavelength (No Glass) lQE - 535 - nm Design Description Table 8. KAI-08052-FBA AND KAI-08052-QBA CONFIGURATIONS WITH MAR GLASS Description Symbol Min. Nom. Max. Units Sampling Plan Peak Quantum Efficiency Blue Green Red QEmax - 38 41 42 - % Design Peak Quantum Efficiency Wavelength Blue Green Red lQE - 460 535 615 - nm Design www.onsemi.com 8 KAI-08052 TYPICAL PERFORMANCE CURVES Quantum Efficiency KAI-08052 Monochrome with Microlens (MAR Glass) Figure 6. Monochrome with Microlens (MAR Glass) Quantum Efficiency KAI-08052 Monochrome with Microlens (No Glass) Figure 7. Monochrome with Microlens (No Cover Glass) Quantum Efficiency www.onsemi.com 9 KAI-08052 KAI-08052 Color (Bayer RGB) with Microlens (MAR Glass) Figure 8. KAI-08052 Bayer Color with Microlens (MAR Glass) Quantum Efficiency KAI-08052 Color (Sparse CFA) with Microlens (MAR Glass) Figure 9. KAI-08052 Sparse CFA Color with Microlens (MAR Glass) Quantum Efficiency www.onsemi.com 10 KAI-08052 Angular Quantum Efficiency For the curves marked "Horizontal", the incident light angle is varied in a plane parallel to the HCCD. For the curves marked "Vertical", the incident light angle is varied in a plane parallel to the VCCD. Monochrome with Microlens Figure 10. Monochrome with Microlens Angular Quantum Efficiency Dark Current versus Temperature Figure 11. Dark Current versus Temperature www.onsemi.com 11 KAI-08052 Power - Estimated 1.2 Power (W) 1.0 0.8 0.6 0.4 0.2 0.0 10 15 20 25 30 35 40 HCCD Frequency (MHz) Single Dual Quad Figure 12. Power Frame Rate (fps) Frame Rates 20 20 18 18 16 16 14 14 12 12 10 10 8 8 6 6 4 4 2 2 0 0 10 15 20 25 30 35 HCCD Frequency (MHz) Single Dual (Left/Right) Figure 13. Frame Rates www.onsemi.com 12 Quad 40 KAI-08052 DEFECT DEFINITIONS Table 9. OPERATION CONDITIONS FOR DEFECT TESTING AT 405C Description Condition Notes Operational Mode Two outputs, using VOUTa and VOUTc, continuous readout HCCD Clock Frequency 10 MHz Pixels Per Line 3520 1 Lines Per Frame 1360 2 Line Time 354.9 ms Frame Time 482.7 ms Photodiode Integration Time Mode A: PD_Tint = Frame Time = 482.7 ms, no electronic shutter used Mode B: PD_Tint = 33 ms, electronic shutter used 1. 2. 3. 4. VCCD Integration Time 447.2 ms Temperature 40C 3 Light Source Continuous red, green and blue LED illumination Operation Nominal operating voltages and timing 4 Horizontal overclocking used. Vertical overclocking used. VCCD Integration Time = 1260 lines x Line Time, which is the total time a pixel will spend in the VCCD registers. For monochrome sensor, only the green LED is used. Table 10. DEFECT DEFINITIONS FOR TESTING AT 405C Description Definition Standard Grade Notes 80 1 Major dark field defective bright pixel PD_Tint = Mode A Defect 191 mV or PD_Tint = Mode B Defect 13.8 mV Major bright field defective dark pixel Defect 12% Minor dark field defective bright pixel PD_Tint = Mode A Defect 99 mV or PD_Tint = Mode B Defect 7 mV 800 Cluster defect A group of 2 to 10 contiguous major defective pixels, but no more than 3 adjacent defects horizontally. 15 2 Column defect A group of more than 10 contiguous major defective pixels along a single column 0 2 1. For the Bayer color device (KAI-08052-FBA), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects). www.onsemi.com 13 KAI-08052 Table 11. OPERATION CONDITIONS FOR DEFECT TESTING AT 275C Description 1. 2. 3. 4. Condition Notes Operational Mode Two outputs, using VOUTa and VOUTc, continuous readout HCCD Clock Frequency 20 MHz Pixels Per Line 3520 1 Lines Per Frame 1360 2 Line Time 177.8 ms Frame Time 241.8 ms Photodiode Integration Time (PD_Tint) Mode A: PD_Tint = Frame Time = 241.8 ms, no electronic shutter used VCCD Integration Time 224.0 ms Temperature 27C Light Source Continuous red, green and blue LED illumination Operation Nominal operating voltages and timing Mode B: PD_Tint = 33 ms, electronic shutter used 3 4 Horizontal overclocking used. Vertical overclocking used. VCCD Integration Time = 1260 lines x Line Time, which is the total time a pixel will spend in the VCCD registers. For monochrome sensor, only the green LED is used. Table 12. DEFECT DEFINITIONS FOR TESTING AT 275C Description Definition Standard Grade Notes 80 1 A group of 2 to 10 contiguous major defective pixels, but no more than 3 adjacent defects horizontally. 15 2 A group of more than 10 contiguous major defective pixels along a single column 0 2 Major dark field defective bright pixel PD_Tint = Mode A Defect 30 mV or PD_Tint = Mode B Defect 4.6 mV Major bright field defective dark pixel Defect 12% Cluster defect Column defect 1. For the Bayer color device (KAI-08052-FBA), a bright field defective pixel deviates by 12% with respect to pixels of the same color. 2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects). Defect Map defects are not included in the defect map. All defective pixels are reference to pixel 1, 1 in the defect maps. See Figure 14: Regions of interest for the location of pixel 1,1. The defect map supplied with each sensor is based upon testing at an ambient (27C) temperature. Minor point www.onsemi.com 14 KAI-08052 TEST DEFINITIONS Test Regions of Interest Image Area ROI: Pixel (1, 1) to Pixel (3320, 2496) Active Area ROI: Pixel (13, 13) to Pixel (3308, 2484) Center ROI: Pixel (1611, 1199) to Pixel (1710, 1298) Only the Active Area ROI pixels are used for performance and defect tests. Overclocking The test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. See Figure 14 for a pictorial representation of the regions of interest. VOUTc 12 dark rows 12 buffer rows Horizontal Overclock 22 dark columns 12 buffer columns 12 buffer columns 22 dark columns Pixel 13, 13 3296 x 2472 Active Pixels Pixel 1, 1 12 buffer rows 12 dark rows VOUTa Figure 14. Regions of Interest Tests Dark Field Global Non-Uniformity This test is performed under dark field conditions. The sensor is partitioned into 768 sub regions of interest, each of which is 103 by 103 pixels in size. The average signal level of each of the 768 sub regions of interest is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Where i = 1 to 768. During this calculation on the 768 sub regions of interest, the maximum and minimum signal levels are found. The dark field global uniformity is then calculated as the maximum signal found minus the minimum signal level found. Units: mVpp (millivolts peak to peak) Signal of ROI[i] = (ROI Average in counts - Horizontal overclock average in counts) * mV per count www.onsemi.com 15 KAI-08052 Dark Field Defect Test This test is performed under dark field conditions. The sensor is partitioned into 768 sub regions of interest, each of which is 103 by 103 pixels in size. In each region of interest, the median value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the "Defect Definitions" section. Global Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 560 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 800 mV. Global non-uniformity is defined as GlobalNon-Uniformity + 100 ActiveAreaStandardDeviation ActiveAreaSignal Units: %rms. Active Area Signal = Active Area Average - Dark Column Average Bright Field Defect Test This test is performed with the imager illuminated to a level such that the output is at approximately 476 mV. Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mV. The average signal level of all active pixels is found. The bright and dark thresholds are set as: Global Peak to Peak Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 560 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 800 mV. The sensor is partitioned into 768 sub regions of interest, each of which is 103 by 103 pixels in size. The average signal level of each of the 768 sub regions of interest (ROI) is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Dark defect threshold = Active Area Signal * threshold Bright defect threshold = Active Area Signal * threshold The sensor is then partitioned into 768 sub regions of interest, each of which is 103 by 103 pixels in size. In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. Example for major bright field defective pixels: * Average value of all active pixels is found to be 560 mV * Dark defect threshold: 560 mV * 12 % = 67 mV * Bright defect threshold: 560 mV * 12 % = 67 mV * Region of interest #1 selected. This region of interest is pixels 13, 13 to pixels 115, 115. Median of this region of interest is found to be 560 mV. Any pixel in this region of interest that is (560 + 67 mV) 627 mV in intensity will be marked defective. Any pixel in this region of interest that is (560 - 67 mV) 493 mV in intensity will be marked defective. * All remaining 768 sub regions of interest are analyzed for defective pixels in the same manner. Signal of ROI[i] = (ROI Average in counts - Horizontal overclock average in counts) * mV per count Where i = 1 to 768. During this calculation on the 768 sub regions of interest, the maximum and minimum signal levels are found. The global peak to peak uniformity is then calculated as: GlobalUniformity + 100 MaximumSignal * MinimumSignal ActiveAreaSignal Units: %pp Center Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 560 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 800 mV. Defects are excluded for the calculation of this test. This test is performed on the center 100 by 100 pixels of the sensor. Center uniformity is defined as: Center ROI Uniformity + 100 Center ROI Standard Deviation Center ROI Signal Units: %rms. Center ROI Signal = Center ROI Average - Dark Column Average www.onsemi.com 16 KAI-08052 OPERATION Table 13. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Units Notes Operating Temperature TOP -50 70 C 1 Humidity RH 5 90 % 2 Output Bias Current Iout 60 mA 3 Off-chip Load CL 10 pF Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Noise performance will degrade at higher temperatures. 2. T = 25C. Excessive humidity will degrade MTTF. 3. Total for all outputs. Maximum current is -15 mA for each output. Avoid shorting output pins to ground or any low impedance source during operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity). Table 14. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND Description Minimum Maximum Units Notes VDDa, VOUTa -0.4 15.5 V 1 RDa -0.4 15.5 V 1 V1B, V1T ESD - 0.4 ESD + 24.0 V V2B, V2T, V3B, V3T, V4B, V4T ESD - 0.4 ESD + 14.0 V H1Sa, H1Ba, H2Sa, H2Ba, H2SLa, Ra, OGa ESD - 0.4 ESD + 14.0 V ESD -10.0 0.0 V SUB -0.4 40.0 V 1 2 1. a denotes a, b, c or d 2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. (AND9183/D) Power-Up and Power-Down Sequence Adherence to the power-up and power-down sequence is critical. Failure to follow the proper power-up and power-down sequences may cause damage to the sensor. Do not pulse the electronic shutter until ESD is stable V+ VDD SUB time ESD V- VCCD Low HCCD Low Activate all other biases when ESD is stable and SUB is above 3 V Figure 15. Power-Up and Power-Down Sequence limiting the SUB current to less than 10 mA. SUB and VDD must always be greater than GND. ESD must always be less than GND. Placing diodes between SUB, VDD, ESD and ground will protect the sensor from accidental overshoots of SUB, VDD and ESD during power on and power off. See the figure below. Notes: 1. Activate all other biases when ESD is stable and SUB is above 3 V 2. Do not pulse the electronic shutter until ESD is stable 3. VDD cannot be +15 V when SUB is 0 V 4. The image sensor can be protected from an accidental improper ESD voltage by current www.onsemi.com 17 KAI-08052 The VCCD clock waveform must not have a negative overshoot more than 0.4 V below the ESD voltage. Example of external diode protection for SUB, VDD and ESD. a denotes a, b, c or d 0.0 V VDDa SUB GND ESD ESD - 0.4 V All VCCD Clocks absolute maximum overshoot of 0.4 V ESD Figure 17. Figure 16. Table 15. DC BIAS OPERATING CONDITIONS Pins Symbol Minimum Nominal Maximum Units Maximum DC Current Notes Reset Drain RDa RD 11.8 12.0 12.2 V 10 mA 1 Output Gate OGa OG -2.2 -2.0 -1.8 V 10 mA 1 Output Amplifier Supply VDDa VDD 14.5 15.0 15.5 V 11.0 mA 1, 2 Ground GND GND 0.0 0.0 0.0 V -1.0 mA Substrate SUB VSUB 5.0 VAB VDD V 50 mA 3, 8 ESD ESD -9.2 -9.0 Vx_L V 50 mA 6, 7, 9 VOUTa Iout -3.0 -7.0 -10.0 mA Description ESD Protection Disable Output Bias Current 1, 4, 5 1. a denotes a, b, c or d 2. The maximum DC current is for one output. Idd = Iout + Iss. See Figure 18. 3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such that the photodiode charge capacity is the nominal PNe (see Specifications). 4. An output load sink must be applied to each VOUT pin to activate each output amplifier. 5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise. 6. Adherence to the power-up and power-down sequence is critical. See Power-Up and Power-Down Sequence section. 7. ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V 8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions (AND9183/D) 9. Where Vx_L is the level set for V1_L, V2_L, V3_L, or V4_L in the application. www.onsemi.com 18 VDDa RDa Ra KAI-08052 Idd HCCD Floating Diffusion Iout OGa VOUTa Iss Source Follower #1 Source Follower #2 Figure 18. Output Amplifier www.onsemi.com 19 Source Follower #3 KAI-08052 AC Operating Conditions Table 16. CLOCK LEVELS Description Vertical CCD Clock, Phase 1 Symbol Level Minimum Nominal Maximum Units Capacitance (2) V1B, V1T V1_L Low -8.2 -8.0 -7.8 V 43 nF (6) V1_M Mid -0.2 0.0 0.2 V1_H High 11.5 12.0 12.5 V2_L Low -8.2 -8.0 -7.8 V 43 nF (6) V2_H High -0.2 0.0 0.2 V3_L Low -8.2 -8.0 -7.8 V 43 nF (6) V3_H High -0.2 0.0 0.2 V4_L Low -8.2 -8.0 -7.8 V 43 nF (6) V4_H High -0.2 0.0 0.2 H1S_L Low -5.2 (7) -4.0 -3.8 V 280 pF (6) H1S_A Amplitude 3.8 4.0 5.2 (7) H1B_L Low -5.2 (7) -4.0 -3.8 V 190 pF (6) H1B_A Amplitude 3.8 4.0 5.2 (7) H2S_L Low -5.2 (7) -4.0 -3.8 V 280 pF (6) H2S_A Amplitude 3.8 4.0 5.2 (7) H2B_L Low -5.2 (7) -4.0 -3.8 V 190 pF (6) V 20 pF (6) V 16 pF (6) V 3 nF (6) Vertical CCD Clock, Phase 2 V2B, V2T Vertical CCD Clock, Phase 3 V3B, V3T Vertical CCD Clock, Phase 4 V4B, V4T Horizontal CCD Clock, Phase 1 Storage H1Sa Horizontal CCD Clock, Phase 1 Barrier H1Ba Horizontal CCD Clock, Phase 2 Storage H2Sa Horizontal CCD Clock, Phase 2 Barrier H2Ba Horizontal CCD Clock, Last Phase (3) H2SLa Reset Gate Ra Electronic Shutter (5) 1. 2. 3. 4. 5. 6. 7. Pins (1) SUB H2B_A Amplitude 3.8 4.0 H2SL_L Low -5.2 -5.0 -4.8 H2SL_A Amplitude 4.8 5.0 5.2 Low -3.5 -2.0 -1.5 R_H High 2.5 3.0 4.0 VES High 29.0 30.0 40.0 R_L (4) 5.2 (7) a denotes a, b, c or d Capacitance is total for all like named pins Use separate clock driver for improved speed performance. Reset low should be set to -3 V for signal levels greater than 40,000 electrons. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions (AND9183/D) Capacitance values are estimated If the minimum horizontal clock low level is used (-5.2 V), then the maximum horizontal clock amplitude should be used (5.2 V amplitude) to create a -5.2 V to 0.0 V clock. If a 5 V clock driver is used, the horizontal low level should be set to -5.0 V and the high level should be a set to 0.0 V. The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. VES VSUB GND GND Figure 19. www.onsemi.com 20 KAI-08052 Device Identification The device identification pin (DevID) may be used to determine which 5.5 micron pixel interline CCD sensor is being used. Note that the KAI-08052 shares the same Device ID value as the KAI-08050 and KAI-08051. Table 17. DEVICE IDENTIFICATION Description Device Identification Pins Symbol Minimum Nominal Maximum Units Maximum DC Current Notes DevID DevID 8,000 10,000 12,000 W 50 mA 1, 2 1. If the Device Identification is not used, it may be left disconnected. 2. Values specified are for 40C. Recommended Circuit Note that V1 must be a different value than V2. V1 V2 R_external DevID ADC R_DeviceID GND KAI-08052 Figure 20. Device Identification Recommended Circuit www.onsemi.com 21 KAI-08052 TIMING Table 18. REQUIREMENTS AND CHARACTERISTICS Description Symbol Minimum Nominal Maximum Units Photodiode Transfer tpd 1.0 - - ms VCCD Leading Pedestal t3p 4.0 - - ms VCCD Trailing Pedestal t3d 4.0 - - ms VCCD Transfer Delay td 1.0 - - ms VCCD Transfer tv 2.0 - - ms VVCR 75 100 % tVR, tVF 5 - 10 % ths 0.2 - - ms HCCD Transfer te 25.0 - - ns Shutter Transfer tsub 1.0 - - ms Shutter Delay thd 1.0 - - ms Reset Pulse tr 2.5 - - ns Reset - Video Delay trv - 2.2 - ns H2SL - Video Delay thv - 3.1 - ns Line Time tline 45.5 - - ms 87.6 - - 57.4 - - 114.8 - - Dual HCCD Readout 220.7 - - Single HCCD Readout VCCD Clock Cross-over VCCD Rise, Fall Times HCCD Delay Frame Time tframe 1. Refer to timing diagrams as shown in Figures 21, 22, 23, 24 and 25. 2. Refer to Figure 25: VCCD Clock Edge Alignment 3. Relative to the pulse width www.onsemi.com 22 Notes 2, 3 Dual HCCD Readout Single HCCD Readout ms Quad HCCD Readout KAI-08052 Timing Diagrams The timing sequence for the clocked device pins may be represented as one of seven patterns (P1-P7) as shown in the table below. The patterns are defined in Figure 21 and Figure 22. Contact ON Semiconductor Application Engineering for other readout modes. Table 19. Quad Readout Dual Readout VOUTa, VOUTb Dual Readout VOUTa, VOUTc Single Readout VOUTa V1T P1T P1B P1T P1B V2T P2T P4B P2T P4B V3T P3T P3B P3T P3B V4T P4T P2B P4T P2B Device Pin V1B P1B V2B P2B V3B P3B V4B P4B P5 H1Sa H1Ba P6 H2Sa2 H2Ba Ra P7 P5 H1Sb P5 H1Bb H2Sb P6 (2) P6 P6 H2Bb P5 Rb P7 P7 (1) or Off (3) P7 (1) or Off (3) P5 P5 (1) or Off (3) P5 P5 (1) or Off (3) P6 P6 (1) or Off (3) P6 P6 (1) or Off (3) Rc P7 P7 (1) or Off (3) P7 P7 (1) or Off (3) H1Sd P5 P5 (1) or Off (3) P5 P5 (1) or Off (3) P6 P6 (1) or Off (3) H1Sc H1Bc H2Sc (2) H2Bc H1Bd H2Sd (2) P6 H2Bd Rd # Lines/Frame (Minimum) # Pixels/Line (Minimum) P6 (1) or Off (3) P6 P5 P7 P7 (1) or Off (3) P7 (1) or Off (3) P7 (1) or Off (3) 1260 2520 1260 2520 1693 3386 1. For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should be a multiple of the frequency used on the a and b register. 2. H2SLx follows the same pattern as H2Sx For optimal speed performance, use a separate clock driver. 3. Off = +5 V. Note that there may be operating conditions (high temperature and/or very bright light sources) that will cause blooming from the unused c/d register into the image area. www.onsemi.com 23 KAI-08052 Photodiode Transfer Timing A row of charge is transferred to the HCCD on the falling edge of V1 as indicated in the P1 pattern below. Using this timing sequence, the leading dummy row or line is combined with the first dark row in the HCCD. The "Last Line" is dependent on readout mode - either 632 or 1264 minimum counts required. It is important to note that, in Pattern td 1 2 t3p 3 tpd 4 t3d P1T 5 6 general, the rising edge of a vertical clock (patterns P1-P4) should be coincident or slightly leading a falling edge at the same time interval. This is particularly true at the point where P1 returns from the high (3rd level) state to the mid-state when P4 transitions from the low state to the high state. td tv tv tv/2 tv/2 P2T tv/2 tv/2 P3T P4T tv P1B tv/2 tv tv/2 P2B P3B P4B ths P5 Last Line ths L1 + Dummy Line L2 P6 P7 Figure 21. Photodiode Transfer Timing Line and Pixel Timing Each row of charge is transferred to the output, as illustrated below, on the falling edge of H2SL (indicated as P6 pattern). The number of pixels in a row is dependent on Pattern P1T tline tv tv P1B ths P5 P6 readout mode - either 853 or 1706 minimum counts required. te/2 te tr P7 VOUT Pixel 1 Pixel 34 Pixel n Figure 22. Line and Pixel Timing www.onsemi.com 24 KAI-08052 Pixel Timing Detail P5 P6 P7 VOUT trv thv Figure 23. Pixel Timing Detail Frame/Electronic Shutter Timing The resulting photodiode integration time is defined from the falling edge of SUB to the falling edge of V1 (P1 pattern). The SUB pin may be optionally clocked to provide electronic shuttering capability as shown below. tframe Pattern P1T/B SUB P6 thd tint tsub thd Figure 24. Frame/Electronic Shutter Timing VCCD Clock Edge Alignment VVCR 90% tV 10% tVR tVF 90% tV 10% tVF tVR Figure 25. VCCD Clock Edge Alignment www.onsemi.com 25 KAI-08052 Line and Pixel Timing - Vertical Binning by 2 tv tv tv ths P1T P2T P3T P4T P1B P2B P3B P4B ths P5 P6 P7 VOUT Pixel 1 Pixel n Pixel 34 Figure 26. Line and Pixel Timing - Vertical Binning by 2 www.onsemi.com 26 KAI-08052 MECHANICAL INFORMATION Completed Assembly Notes: 1. See Ordering Information for marking code. 2. No materials to interfere with clearance through guide holes. 3. The center of the active image is nominally at the center of the package. 4. Die rotation < 0.5 degrees 5. Internal traces may be exposed on sides of package. Do not allow metal to contact sides of ceramic package. 6. Recommended mounting screws: 1.6 X 0.35 mm (ISO Standard); 0 - 80 (Unified Fine Thread Standard) 7. Units: millimeters Figure 27. Completed Assembly, Top and Side View www.onsemi.com 27 KAI-08052 Notes: 1. 2. 3. 4. See Ordering Information for marking code. No materials to interfere with clearance through guide holes. Recommended mounting screws: 1.6 X 0.35 mm (ISO Standard); 0 - 80 (Unified Fine Thread Standard) Units: millimeters Figure 28. Completed Assembly, Bottom View www.onsemi.com 28 KAI-08052 Notes: 1. 2. 3. 4. No materials to interfere with clearance through guide holes. Internal traces may be exposed on sides of package. Do not allow metal to contact sides of ceramic package. Recommended mounting screws: 1.6 X 0.35 mm (ISO Standard); 0 - 80 (Unified Fine Thread Standard) Units: millimeters Figure 29. Completed Assembly, Side View with Glass and Die Detail www.onsemi.com 29 KAI-08052 Notes: 1. No materials to interfere with clearance through guide holes. 2. Recommended mounting screws: 1.6 X 0.35 mm (ISO Standard); 0 - 80 (Unified Fine Thread Standard) 3. Units: millimeters Figure 30. Mechanical Details, Oblong Guide Hole www.onsemi.com 30 KAI-08052 MAR Cover Glass Notes: 1. Dust/Scratch count - 12 micron maximum 2. Units: mm Figure 31. MAR Cover Glass Clear Cover Glass Notes: 1. Dust/Scratch count - 10 micron maximum 2. Units: mm Figure 32. Clear Cover Glass www.onsemi.com 31 KAI-08052 Cover Glass Transmission 100 90 Transmission (%) 80 70 60 50 40 30 20 10 0 200 300 400 500 600 700 Wavelength (nm) MAR Clear Figure 33. Cover Glass Transmission www.onsemi.com 32 800 900 KAI-08052 STORAGE AND HANDLING Table 20. STORAGE CONDITIONS Description Symbol Minimum Maximum Units Notes Storage Temperature TST -55 80 C 1 Humidity RH 5 90 % 2 1. Long term storage toward the maximum temperature will accelerate color filter degradation. 2. T = 25C. Excessive humidity will degrade MTTF. REFERENCES For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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