1 ANALOG DEVICES AN317 APPLICATION NOTE ONE TECHNOLOGY WAY e P.O. BOX 9106 e NORWOOD, MASSACHUSETTS 02062-9106 e 617/329-4700 Circuit Applications of the AD7226 Quad CMOS DAC by Mike Byrne The AD7226 is a monolithic quad 8-bit CMOS DAC pack- aged in a 20-pin DIP. Each DAC output is buffered by a CMOS amplifier which is capable of developing +10V across a 2k0 resistor. Data is loaded from a common 8-bit data bus into one of the on-chip latches provided for each individual DAC (see Figure 1). The AD7226 has certain features which make the part a unique and extremely useful device. Firstly, housing four DACs plus interface logic and output buffer amplifiers in a 20-pin package allows for substantial savings in circuit board space requirements and complexity. Additionally, the converters are operated in the voltage-mode which al- lows single supply operation for the part, with a unique DAC switch pair arrangement allowing an extended refer- ence range not previously available with voltage-mode converters. Since all four DACs are fabricated on the same ' chip, precise matching and tracking between them is inherent. This application note discusses some uses of the AD7226 in de or voltage setting type applications. Operation of some of these circuits relies on the inherent DAC-to-DAC matching provided by the AD7226. Other circuits benefit trom the circuit board space saving offered by the AD7226 and from its ability to operate with a single power supply. Veer Vao S __N ta cr] LATCHA DACA 2) VourA rv UN pb [tatcue pace y 1) VourB MsB ary DATA @- , f i BIT) Ly Ls U ~ |LatcHe pacc 29) Vour s ry LATCHD DACD Pd 49) VourD WR (5 I V CONTROL tr | Ar 8 toons AD7226 Vss AGND DGND Figure 1, AD7226 Functional Diagram This application note does not discuss the basic operation of the AD7226; consult the data sheet for this information. AD7226 APPLICATIONS DISCUSSED IN THIS NOTE 1. Programmable Offset Adjust of Operational Amplifiers using one-channel of the quad DAC per op amp. 2. Set-Point Controller Circuit which allows fine adjust over a wide voltage range. 3. Self-Programmable Reference Voltage using one DAC of the AD7226. 4. Staircase Window Comparator Circuit for Measure- ment of Threshold Values for a TTL device. 5. Vss Generation Circuits to allow dual supply operation of the AD7226 from a single power supply. 6. 5V Single Supply results showing excellent Differential Nonlinearity performance. PROGRAMMABLE OFFSET ADJUST The AD7226 can be used to provide programmable input offset voitage adjustment for operational amplifiers. The circuit configuration used to achieve this is shown in Fig- ure 2. Each output of the AD7226 can be used to trim the input offset voltage of one operational amplifier. This means that programmable offset adjustment can be achieved on four operational amplifiers by the addition of just one 20-pin device and some extra resistors. The circuit configuration uses the input offset voltage nul- ling pins provided on most operational amplifiers. Resis- tor R2, tied to + 10V, provides a fixed bias current to one offset node. The output of the D/A converter is connected via R1 to provide a variable bias current to the other offset node. Therefore, changing the code on the D/A converter provides offset adjust for the operational amplifier. For symmetrical adjustment, the bias current through R2 should equal the current in the other offset node with the half-full scale code {i.e. 10000000) on the D/A converter. Resistors R1 and R2 are chosen such that enough current variation over the DAC code range is given to provide the required range of offset adjustment for the op amp in question. Reducing the vatues of R1 and R2 increases the range of offset which can be trimmed, with a correspond- ing reduction in resolution. The method of programmable offset adjustment can be used with most operational amplifiers which have offsetnulling pins provided. Table | shows some results achieved with four popular op amps. The table shows the typical range of offset values which can be trimmed using the given values of resistors R1 and R2. It also gives typi- cal figures for final values of offset achieved after using the method outlined above. The circuit configuration of Figure 2 ensures that, for in- creasing code on the D/A converter, the op amp offset goes more positive when using the first three op amps of Table |. For the TLO91 and other op amps of the family (TLO61, TLO71, etc.) the trim terminals must be swopped (as indicated in Figure 3) to ensure that for increasing code the output offset will go in the positive direction. +10V +15V Figure 2. Offset Adjust Using AD7226 +10V +15V Voo ae VRE 4 18 TLo91 Re + 4 5 1 2 DACA + RI AD7226 Figure 3. Offset Adjust for TLO91 The trimming of op amp offsets in this manner increases the offset drift temperature coefficient of the op amp. For example, using the AD544 this increase will be 3u.V/C per millivolt of offset adjustment assuming Oppm/*C temper- ature coefficient for the external resistors R1 and R2. How- ever, the same drift would have been introduced had an external trimpot been used to trim the offset. The method outlined above has the advantage of being programma- ble and, therefore, any drift over temperature can be ad- justed out during a periodic calibration cycle. The programmable input offset voltage adjust can be used to deliberately introduce input offset voltage into the op amp. This could be useful in a system context where programmably introducing offset at a node in the system could give the desired value at the output of the system. The first three op amps shown in Table | operate from dual supplies. The TLO91 op amp is specified to operate at 5V single supply. The AD7226 can operate at 5V single supply and will remain monotonic to 8-bits under these condi- Final : R2 R1 Range Offset ' OpAmp (kQ)) (kQ) (mv) (pV) | AD741 1200 1000 +6.75 14.5 | AD544 620 500 +2.75 3.3 ' AD542 470 360 +24 4.6 TLO91* 1000 500 +9.0 2.5 *Operating in Single Supply Vsg = OV Vpp = + 15V. Allother op amps dual supply + 15V. Table l. Typical Op Amp Offset Results tions. This is basically all that is required for the configura- tions of Figure 2 and Figure 3 to function. The 5V single supply operation of the AD7226 is discussed later in this application note. Some operational amplifiers, especially duals and quads, do not have trim terminals available to the user. The AD7226 can still be used to provide offset adjustment by programmably varying the voltage at the required op amp input terminal. One such configuration is outlined in Figure 4. The noninverting input of the op amp is offset in a negative direction via R4 to 15V. Ina similar fashion to the previous method, for symmetrical adjustment the current through R4 should equal the current through R3 with the half-full scale code on the D/A converter. Once again increasing the digital code will vary the offset in a positive direction. The resistor configuration will be seen as a low impedance by the noninverting input of the op amp to prevent noise injection. The circuit configuration does not affect the gain or transfer function of the op amp. . Using the TLO44 quad op amp, with the components values given in Figure 4, the typical range of offset which could be trimmed using the method outlined for Figure 3 was +5.5mV. A typical figure for the final offset value achieved was 10,V. Similar techniques can be used for other op amp configurations. +15V 1/4 T1044 Figure 4. Alternative Offset Adjust SET-POINT CONTROLLER The set-point controller circuit of Figure 5 allows pro- grammable fine and coarse adjust of the output voltage, Vout, Over a 200V range. The circuit has a fine adjust reso- lution of 8mV which means that an output voltage can be setin the range 100V to + 100V to within +4mV. The circuit uses DAC A as a programmable coarse adjust and DAC B as a programmable fine adjust of the output voltage. DAC A has an effective output voltage range ofVarer | 10kN R3 10k WA = R2,10kQ JAD741 > VV anians @) +110V 110V Figure 5. Set-Point Controller Circuit 100V to + 100V over the digital input code range giving an LSB size of 800mvV for this coarse adjust DAC. DAC B has an effective output voltage range, at Vout, of 2V giv- ing an LSB size of 8mV for this fine adjust DAC. Amplifier A1 sums the output of both DACs and provides a bipolar output voltage, Vx, at point X. Amplifier A2, with the additional level shifting circuitry, provides a gain of 10 between Vx and Vour. In general, the output voitage Vout can be expressed as: R; ( R, Vour=R. 2Voura * R, +R, + 2-Voure*( ) ~ ( Veet For the component values given in the circuit of Figure 5 this can be simplified to give the expression for Voyy as: 2000 Vour= 10 | Vouta ( 2000 ) vom :25) = (va) The resolution of the fine adjust circuitry can be changed by varying R2. This is done without any significant effect on the overall output voltage range. Adjusting R7 will change the output voltage range, varying the resolution of both the fine adjust and coarse adjust DACs. This circuit of Figure 5 is capable of developing + 100V across a 2.7kQ load. It is useful in set-point controller ap- plications or in a programmable power supply. The other two channels of the AD7226 can be used to perform nor- mal D/A converter functions or configured as above to provide a second set-point controller. SELF-PROGRAMMABLE REFERENCE The circuit of Figure 6 shows how one D/A converter of the AD7226, in this case DAC A, may be used in a feedback configuration to provide a programmable reference volt- age for itself and the other three converters. The relation- ship of Vper to Vin is dependant upon digital code and upon the ratio of resistors R1 and R2. it can be expressed by the formula (1+G) Vrer- 7+ GD, Vin where G = R2/e, and D, is a fractional representation of the digital word in latch A (0<D,=255/256). Figure 6. Self-Programmable Reference st 1 Vop= + 15V 3.5 Vin \ Ves=5V 3M \ R2=3R1 Vance 25 Vm NX Lf R= 2R1 NY WY) R2=R1 2 Vi N, NX M MQ mM 1.5 Vin {> Re a Vin pe 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255 DIGITAL CODE DECIMAL EQUIVALENT Figure 7, Variation of Vaer with Feedback Configuration Figure 7 shows typical plots of Vaer versus digital code for three different values of R2. With Viy=2.5V and R2=3R1the voltage at the output of A1 (i.e. reference voltage for the AD7226) will vary between +2.5V and + 10V over the digital input code range. This gives an effective 10-bit dy- namic range to the other three D/A converter outputs with the minimum LSB size being 10mV over a potential full scale output range of Oto 10V. The circuit of Figure 6 should only be used when the , AD7226 is operated from dual supplies (i.e. Vss = 5V). One reason for this is that the AD7226 is specified at + 10V reference voltage only for single supply operation. More importantly, however, is the fact that the AD7226 has re- duced current sink capability at output voitages near OV when used in single supply (see AD7226 data sheet). This means that the circuit would not operate correctly at lower values of digital input code. For correct operation with dua! supplies R1 must be greater than 6.8kQ. Different configurations of A1 and resistors can be de- vised to give other ranges of reference voltage. It must be noted that varying the voltage at the Vrer pin varies the reference voltage for all the converters. Whatever config- uration devised must ensure that the voltage at the Vper pin of the AD7226 must never go negative with respect to either AGND or DGND. THRESHOLD TESTING in test systems and other applications it is necessary to determine whether some unknown voltage lies within certain limits. In these cases the AD7226 can be used with external comparators or op amps to provide a program- mable staircase window comparator. The voltage levels on the comparator and the window sizes are determined by the digital code in the latches of the D/A converters. Figure 8 shows one such application where the AD7226 | can be used to measure the threshold levels of a TTL de- vice under test. wn a ~ Vouta and Vours of the AD7226 in addition to the six exter- nal comparators, form a staircase window comparator. - Each adjacent pair of comparators forms a window of programmable size. When a voltage lies within a window, the output from that window goes high . Window 1 is set with an upper limit of Voc=5V and a lower limit of Vouta=2.4V. Window 2 has an upper limit of 2.4V and a lower limit of 0.4V, while Window 3 has an upper limit of 0.4V and a lower limit of AGND = OV. These levels can be programmably set and varied as required. The staircase window comparator circuit is used in testing the output threshold levels of the device under test (DUT1), When D8 goes high, SW1 is set so that 400A is sourced from the output of DUT1. The Voy of DUT1 is ap- plied to the staircase window comparator. For the part to pass its Vox test, the output from Window 1 must go high. Any other window going high indicates that the device fails. When D8 goes low, SW1 is switched so that the out- put of DUT1 will sink 16mA and the Vor of DUT1 is meas- ured. Window 3 of the staircase window comparator must go high for the device to pass its Vo, test. Window 2 is not really necessary in the application shown. However, it has been included to demonstrate the non-overlapping staircase comparator configuration. Voute and Voutp of the AD7226, along with additional comparators, can be used to extend the staircase window comparator to give five programmable non-overlapping windows. The window structure for these five non-over- lapping windows is shown in Figure 9 with the upper limit of the staircase now at Vper. If overlapping windows are required, the configuration can easily be adapted as shown in Figure 10a. In this case all four outputs are used with the external comparators to provide three overlap- ping windows. The window structure for this overlapping window configuration is shown in Figure 10b. Veo = +5V swt 16mA Vrest Vo DUT 1 Virw Q 400 nA 1/4 CA339 we > 10k Vaer Voo +5V P WINDOW 1 O09) ps Vour a @ b? IN a > 10k CONTROL LOGIC nV, +5V AA@ WINDOW 2 AD7226 rT > Vout 6 bt 4 10k +5V--VWA-@ WINDOW 3 oo Vourc Ge) Vour o (19 AGND Figure 8. Threshold TestingVeer WINDOW 1 Voura $_______}__ _ WINDOW 2 qos Vourta WINDOW 3 Vourte Wwindow4 Voutp WINDOW 5 AGND Figure 9. Window Structure Vrest FROM D.U.T. 10k +5V~W-9_ WINDOW 1 ey _ +, AD7226 WINDOW 2 Voure +5VVA--9-- WINDOW 3 Figure 10a. Overlapping Windows Veer WINDOW 1 Vours Vouta WINDOW 2 Vourp Vv, oure WINDOW 3 AGND Figure 10b. Window Structure Vss GENERATION Operating the AD7226 from dual supplies results in en- hanced performance over single supply operation on a number of parameters. The negative Vss gives additionai headroom to the output amplifier which results in im- proved negative-going settling-time, improved zero code error performance and an extended input reference range. Some applications may require this enhanced per- formance but may only have a single power supply rail available. The following circuits show some methods of generating a negative Vss froma single power supply rail for the AD7226. Figure 11 shows one such method of generating a nega- tive supply using one CD4049, operated from a Vpp of + 15V. Two inverters of the hex inverter chip are used as an oscillator. The other four inverters are paralleled and used as buffers for higher output current. The square- wave output is level translated to a negative-going signal, then rectified and filtered. The circuit configuration shown will provide an output voltage of 5.1V for current --. loadings in the range of 0.5mA to 8mA. This will satisfy -- the AD7226 Iss requirement over the commercial operat- ing temperature range. Noise spikes which are generated ... ON this Vgg line from the clock can be considerably re- - duced by decoupling the Vpp supply line to the CD4049. 1/6 CD4049AE 5100 Your 1N4001 svt Figure 11. Ves Generation Circuit An alternative method of generating a negative supply from a positive rail is to use Analog Devices AD7560, a DC- DC voltage converter. This can provide a 5V supply from a +5V rail. The circuit configuration used to achieve this is outlined in Figure 12. +Vpp [+5V) C1,C2: 10nF/10V Coix: 1nF e NA 16 aC1y Cox fs} 3 14 AD7560 S 4 [13 } 0 - Vo (- 5) cH Fi G] [19] CG] [2] Figure 12. AD7&60 Giving 5V Some applications may require a + 5V reference but may only have a single supply rail available. The AD7226 is specified at + 5V reference when used with dual supplies only. The circuit of Figure 13 could prove useful in such applications. It provides a Vss of 5V, the + 5V reference and Vpp of +11.4V to +16.5V from a single + 16.4V to +21.5V power supply rail (in battery applications two 9V batteries in series). The AD584 is a pin-programmable Precision voltage reference. The AD380 op-amp buffer es- tablishes the ground for the AD7226 midway between 0 and + 10V. Hence, pin 1 of the AD584 can be used as the +5V reference for the AD7226. The V of the input signal is used to provide a Veg of 5V. If the input voltage can exceed the limits above (i.e., + 16.4V to + 21.5V) a zener diode may be required to provide a regulated supply volt- age to the Vpp pin of the AD7226. The voltage at the Vpp pin must never exceed +17V with respect to the AD7226 ground.V+ + +5V OUT GROUND ' ~S5VOUT 0 Figure 13. Voltage Splitting Using AD584 5V SINGLE SUPPLY OPERATION The AD7226 can be operated from a single +5V power supply rail, but because the output amplifier now loses a considerable amount of headroom, the performance of the part is degraded. However, one important parameter which retains its specified performance is differential nonlinearity. At a single +5V supply this remains within +1LSB which ensures that the AD7226 will remain monotonic over the output voltage range. This monotonic operation makes the AD7226, at single +5V supply, suitable for applications where the absolute value (or accuracy) of the output voltage is not important but where it is essential that the output increases as the digital code increases. An example of this type of applica- tion has already been outlined in this application note: trimming the offset of operational amplifiers. The required overhead voltage of 4V between the refer- ence voltage and the Vpp input must still be maintained under these conditions. This means that the reference voltages must remain below 1V to ensure monotonic op- :eration. At these low reference voltages, the output offset :voltage is obviously very large with respect to the input reference and the relative accuracy is also degraded. However, the output voltage does increase as the input digital code varies from 0 to 255. This can be seen from the plot of Figure 14 which shows differential nonlinearity for single +5V supply at a reference of 600mV. Figure 15 shows a plot of relative accuracy for the same part under the same conditions. Additionally, the digital input threshold levels and digital input currents are not affected by operating the AD7226 from the single + 5V supply rail. ' 0.50 Vpp = +5V Veer = 600mV o iy a 2 2 3 DIFFERENTIAL NONLINEARITY LSB ~0.25 0 32 64 96 128 160 192 224 INPUT CODE Figure 14. Differential Nonlinearity at5V Vop 2.0 15 Vop= +5V 1.0 Vaer=600mV 2 05 a J 0.0 oO @ -05 3 Q -1.0f < w -15 2 - 20 -25 -3.0} 3.5- ~4.0 0 32 64 36 128 160 192224 INPUT CODE Figure 15. Relative Accuracy at 5V Vpp