January 2010 Doc ID 13365 Rev 2 1/49
49
STA333W
2-channel high-efficiency digital audio system
Sound Terminal™
Features
Wide supply-voltage range (4.5 V - 20 V)
2 power output configurations
– 2 channels of binary PWM (stereo mode)
– 2 channels of ternary PWM (stereo mode)
PowerSSO-36 with exposed pad down
2 channels of 24-bit DDX®
100-dB SNR and dynamic range
Selectable 32- to 192-kHz input sample rates
I2C control with selectable device address
Digital gain -80 dB to +48 dB in 0.5-dB steps
Software volume update
Individual channel and master gain/attenuation
Individual channel and master software and
hardware mute
Independent channel volume bypass
Automatic zero-detect mute
Automatic invalid input detect mute
2-channel I2S input data Interface
Selectable clock input ratio
Input channel mapping
Automatic volume control for limiting maximum
power
96-kHz internal processing sample rate, 24-bit
precision
Advanced AM interference frequency
switching and noise suppression modes
Thermal-overload and short-circuit protection
embedded
Video application: 576 * fS input mode support
Applications
LCD
DVD
Cradle
Digital speaker
Wireless-speaker cradle
Description
The STA333W is an integrated circuit comprising
digital audio processing, digital amplifier control
and DDX® power output stage to create a high-
power, single-chip DDX® solution for all-digital
amplification with high quality and high efficiency.
The STA333W power section consists of four
independent half-bridges stages. These can be
configured via digital control to operate in different
modes. 2 channels can be provided by two full
bridges, providing up to 20 W + 20 W of power.
Also provided in the STA333W are new advanced
AM radio interference reduction modes. The serial
audio data input interface accepts all possible
formats, including the popular I2S format. Three
channels of DDX® processing are provided.
The STA333W is part of the Sound Terminal™
family that provides full digital audio streaming to
the speaker offering cost effectiveness, low power
dissipation and sound enrichment.
PowerSSO-36 package
with exposed
pad down (EPD)
Table 1. Device summary
Order code Package Packaging
STA333W PowerSSO-36 EPD Tube
STA333W13TR PowerSSO-36 EPD Tape and reel
www.st.com
Contents STA333W
2/49 Doc ID 13365 Rev 2
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Power-on/off sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Functional pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1 Power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.2 Reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Serial audio interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.1 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5I
2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STA333W Contents
Doc ID 13365 Rev 2 3/49
5.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Volume control registers (addr 0x06 to 0x09) . . . . . . . . . . . . . . . . . . . . . . 32
6.2.1 Mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . . 32
6.2.2 Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2.3 Channel volume (addr 0x08, 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3 Automodes™ register (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4 Channel configuration registers (addr 0x0E, 0x0F) . . . . . . . . . . . . . . . . . 35
6.5 Variable max power correction registers (addr 0x27, 0x28) . . . . . . . . . . . 35
6.6 Variable distortion compensation registers (addr 0x29, 0x2A) . . . . . . . . . 36
6.7 Fault detect recovery constant registers (addr 0x2B, 0x2C) . . . . . . . . . . 36
6.8 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.9 Reserved registers (addr 0x2E, 0x2F, 0x30, 0x31) . . . . . . . . . . . . . . . . . 37
6.10 Postscale registers (addr 0x32, 0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.11 Output limit register (addr 0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.11.1 Thermal and overcurrent warning output limit register . . . . . . . . . . . . . 38
7 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1 Applications scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2 PLL filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 Characterization data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Contents STA333W
4/49 Doc ID 13365 Rev 2
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 47
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STA333W List of tables
Doc ID 13365 Rev 2 5/49
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Electrical characteristics for digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Electrical specifications for power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. MCS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Thermal warning recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Thermal warning adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Fault detect recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. Support serial audio input formats for MSB first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. Supported serial audio input formats for LSB-First (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 26
Table 20. Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 21. DDX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 22. DDX compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 23. Overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 24. Zero detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 25. Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 26. Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 27. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 28. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 29. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 30. Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 31. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 32. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 33. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 34. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 35. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 36. Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 37. Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 38. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 39. Master mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 40. Channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 41. Master volume offset as a function of MV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 42. Channel volume as a function of CxV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 43. AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 44. Automodes™ AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 45. Status bits description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 46. Output limit values for thermal and overcurrent warnings. . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 47. PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 48. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
List of figures STA333W
6/49 Doc ID 13365 Rev 2
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Pin connection (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Current dead-time test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Left justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Write-mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Read-mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Applications diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 13. Output configuration for stereo BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. Output power vs. supply voltage (THD = 1%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 15. FFT 0 dBfs (VCC = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 16. FFT -60 dBfs (VCC = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 17. THD vs. frequency (VCC = 12 V, Po = 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 18. FFT 0 dBfs (VCC = 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 19. FFT -60 dBfs (VCC = 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 20. THD vs. frequency (VCC = 18 V, Po = 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 21. Double-layer PCB with two copper ground areas and 16 vias . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22. Power derating curve for PCB used as heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 23. PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STA333W Block diagram
Doc ID 13365 Rev 2 7/49
1 Block diagram
Figure 1. Block diagram
Protection
current/thermal
Logic
Regulators
Bias
Power
control
DDX
PLL
Volume
control
Channel
1A
Channel
1B
Channel
2A
Channel
2B
I2S
interface
PowerDigital DSP
I2C
Pin description STA333W
8/49 Doc ID 13365 Rev 2
2 Pin description
2.1 Pin out
Figure 2. Pin connection (package top view)
2.2 Pin list
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VDD_DIG
GND_DIG
SCL
SDA
INT_LINE
RESET
SDI
LRCKI
BICKI
XTI
GND_PLL
FILTER_PLL
VDD_PLL
PWRDN
GND_DIG
VDD_DIG
N.C.
N.C.
GND_SUB
SA
TEST_MODE
VSS
VCC_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
VCC1
GND1
OUT1A
GND_REG
VDD_REG
CONFIG
N.C.
N.C.
D05AU1638
EP
exposed pad (down)
Connect to ground
Table 2. Pin description
Number Type Name Description
1 PWR GND_SUB Substrate ground
2I SA I
2C select address
3 I TEST_MODE This pin must be connected to ground
4 I/O VSS Internal reference at VCC - 3.3 V
5 I/O VCC_REG Internal VCC reference
6 O OUT2B Output half bridge 2B
7 PWR GND2 Power negative supply
8 PWR VCC2 Power positive supply
9 O OUT2A Output half bridge 2A
STA333W Pin description
Doc ID 13365 Rev 2 9/49
10 O OUT1B Output half bridge 1B
11 PWR VCC1 Power positive supply
12 PWR GND1 Power negative supply
13 O OUT1A Output half bridge 1A
14 PWR GND_REG Internal ground reference
15 PWR VDD_REG Internal 3.3-V reference voltage
16 I CONFIG Paralleled mode command
17 - N.C. No internal connection
18 - N.C. No internal connection
19 - N.C. No internal connection
20 - N.C. No internal connection
21 PWR VDD_DIG Positive supply digital
22 PWR GND_DIG Digital ground
23 I PWRDN
Power down:
0: power stage is switched off then the PLL is also
switched off (this operation take 13 million clock cycles)
1: normal operation
24 PWR VDD_PLL Positive supply for PLL
25 I FILTER_PLL Connection to PLL filter
26 PWR GND_PLL Negative supply for PLL
27 I XTI PLL input clock, 256 * fS, or 384 * fS
28 I BICKI I
2
S serial clock
29 I LRCKI I
2
S left/right clock
30 I SDI I
2
S serial data channel
31 I RESET
Reset:
0: reset state, power stage is switched off, all registers are
set to default value
1: normal operation
32 O INT_LINE Fault interrupt
33 I/O SDA I2C serial data, used as SDA_OUT
34 I SCL I2C serial clock
35 PWR GND_DIG Digital ground
36 PWR VDD_DIG Digital supply
--EP Exposed pad for ground-plane heatsink, to be connected
to GND
Table 2. Pin description (continued)
Number Type Name Description
Pin description STA333W
10/49 Doc ID 13365 Rev 2
2.3 Thermal data
Table 3. Thermal data
Symbol Parameter Min Typ Max Unit
RTh(j-case) Thermal resistance junction to case (thermal pad) - 1.5 2.0 °C/W
Tsd Thermal-shutdown junction temperature 140 150 160 °C
TwThermal-warning temperature - 130 - °C
Thsd Thermal-shutdown hysteresis 18 20 22 °C
STA333W Electrical specification
Doc ID 13365 Rev 2 11/49
3 Electrical specification
3.1 Absolute maximum ratings
Warning: Stresses beyond those listed in Table 4: Absolute maximum
ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated in
Table 5: Recommended operating conditions are not implied.
Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. In the real
application, a power supply with nominal value rated within
the limits of the recommended operating conditions, may
experience some rising beyond the maximum operating
conditions for a short time when no or very low current is
being sinked (amplifier in mute state). In this case the
reliability of the device is guaranteed, provided that the
absolute maximum ratings are not exceeded.
3.2 Recommended operating conditions
Table 4. Absolute maximum ratings
Symbol Parameter Min Typ Max Unit
VCC Analog supply voltage (pins VCCx) - - 23 V
VDD Digital supply voltage (pins VDD_DIG) - - 4.0 V
ILLogic input interface -0.3 - 4.0 V
Top Operating junction temperature 0 - 150 °C
Tstg Storage temperature -40 - 150 °C
Table 5. Recommended operating conditions
Symbol Parameter Min Typ Max Unit
VCC Analog supply voltage (VCCx) 4.5 - 20.0 V
VDD Digital supply voltage (VDD_DIG) 2.7 3.3 3.6 V
ILLogic input interface 2.7 3.3 3.6 V
Tamb Ambient temperature 0 - 70 °C
Electrical specification STA333W
12/49 Doc ID 13365 Rev 2
3.3 Electrical specifications - digital section
3.4 Electrical specifications - power section
The specifications in Ta bl e 7 below are given for the conditions VCC = 18 V, VDD = 3.3 V,
fSW = 384 kHz, Tamb = 25 °C and RL = 8 Ω, unless otherwise specified.
Table 6. Electrical characteristics for digital section
Symbol Parameter Conditions Min Typ Max Unit
Iil Input current, no pull-up or
pull-down resistor
Vi = 0 V - - ±10 µA
Iih Vi = VDD = 3.6 V - - ±10 µA
Vil Low-level input voltage - - - 0.2 *
VDD
V
Vih High-level input voltage - 0.8 *
VDD
--V
Vol Low-level output voltage Iol = 2 mA - - 0.4 *
VDD
V
Voh High-level output voltage Ioh = 2 mA 0.8 *
VDD
--V
Ipu Pull-up current - 25 66 125 µA
Rpu
Equivalent pull-up
resistance --50-kΩ
Table 7. Electrical specifications for power section
Symbol Parameter Conditions Min Typ Max Unit
Po Output power BTL THD = 1% - 16 - W
THD = 10% - 20 -
RdsON
Power P-channel/N-channel
MOSFET (total bridge) ld = 1 A - 180 250 mΩ
ldss
Power P-channel/N-channel
leakage VCC = 18 V --10µA
gP Power P-channel RdsON
matching ld = 1 A 95--%
gN Power N-channel RdsON
matching ld = 1 A 95--%
ILDT
Low-current dead time
(static)
Resistive load,
refer to Figure 5 - 5 10 ns
IHDT
High-current dead time
(dynamic) Refer to Figure 6 - 1020ns
trRise time Resistive load,
refer to Figure 5 - 8 10 ns
tfFall time Resistive load,
refer to Figure 5 - 8 10 ns
STA333W Electrical specification
Doc ID 13365 Rev 2 13/49
VCC Supply voltage - 4.5 - 20 V
IVCC
Supply current from VCC in
power down PWRDN = 0 30 60 200 µA
Supply current from VCC in
operation
PCM input signal = -60 dBfs
Switching frequency =
384 kHz
No LC filters
- 3050mA
IVDD_DIG
Supply current for DDX
processing (reference only) Internal clock = 49.152 MHz 10 30 50 mA
Supply current in standby - 8 11 25 mA
ILIM Overcurrent limit Non-linear output (1) 2.23.54.3A
ISCP Short-circuit protection High-impedance output (2) 2.73.85.0A
VUVP
Undervoltage protection
threshold - - 3.5 4.3 V
tmin
Output minimum pulse
width No load 20 30 60 ns
THD+N Total harmonic distortion
and noise
DXX stereo mode, Po = 1 W,
f = 1 kHz - 0.05 0.2 %
DR Dynamic range - - 100 - dB
SNR
Signal to noise ratio in
ternary mode A-weighted - 100 -
dB
Signal to noise ratio in
binary mode A-weighted - 90 -
PSRR Power supply rejection ratio
DXX stereo mode, < 5 kHz,
VRIPPLE = 1 V RMS
audio input = dither only
-80-dB
XTA L K Crosstalk
DXX stereo mode, < 5 kHz,
One channel driven at 1 W
the other channel measured
-80-dB
ηPeak efficiency
in DXX mode Po = 2 x 20 W into 8 Ω-90-%
1. The ILIM data is for 1 channel of BTL configuration, thus, 2 * ILIM drives the 2-channel BTL configuration.
The current limit is active when OCRB = 0 (see Table 23: Overcurrent warning detect adjustment bypass
on page 28. When OCRB = 1 then ISC applies.
2. The ISCP current limit data is for 1 channel of BTL configuration, thus, 2 * ISCP drives the 2-channel BTL
configuration. The short-circuit current is applicable when OCRB = 1 (see Table 23: Overcurrent warning
detect adjustment bypass on page 28.
Table 7. Electrical specifications for power section (continued)
Symbol Parameter Conditions Min Typ Max Unit
Electrical specification STA333W
14/49 Doc ID 13365 Rev 2
3.5 Power-on/off sequences
The power-on/off sequences shown in Figure 3 and Figure 4 below ensure a pop-free turn
on and turn off.
Figure 3. Power-on sequence
Figure 4. Power-off sequence
Don’t care
VCC
VDD_Dig
XTI
Reset TR
Don’t care
Don’t care
PWRDN
Soft EAPD
Reg. 0x05
Bit 7 = 1
TC
Don’t care
VCC
VDD_Dig
XTI
Reset TR
Don’t care
Don’t care
PWRDN
Soft EAPD
Reg. 0x05
Bit 7 = 1
TC
TR = mimimum time between XTI master clock stable and reset removal: 1 ms
TC = minimum time between reset removal and I2C program sequence start: 1 ms
No specific VCC and VDD_DIG turn-on sequence is required
Clock stable means: fmax - fmin < 1 MHz
VCC
VDD_DIG
XTI
RESET
PWRDN
Bit EAPD
Register 0x05
Don’t care
VCC
VDD_Dig
XTI Don’t care
Soft Mute
Reg. 0x07
Data 0xFE
Soft EAPD
Reg. 0x05
Bit 7 = 0
Don’t care
FE
Don’t care Don’t care
Don’t care
VCC
VDD_Dig
XTI Don’t care
Soft Mute
Reg. 0x07
Data 0xFE
Soft EAPD
Reg. 0x05
Bit 7 = 0
Don’t care
FE
Don’t care Don’t care
No specific VCC and VDD_DIG turn-off sequence is required
VCC
VDD_DIG
XTI
Mute
Bit EAPD
Register 0x05
Register 0x07
STA333W Electrical specification
Doc ID 13365 Rev 2 15/49
3.6 Testing
Figure 5. Test circuit
Figure 6. Current dead-time test circuit
Low current dead time = MAX(DTr,DTf)
OUTxY
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
t
DTfDTr
Duty cycle = 50%
INxY OUTxY
gnd
+Vcc
M58
M57
R 8Ω
+
-
V67 =
vdc = Vcc/2
D03AU1458
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Rload=8Ω
Q2
OUTB
DTout(B) DTin(B)
DTout(A)
C71 470nF C70
470nF
C69
470nF
Iout=4A
Iout=4A
Q4
Q1
Q3
M64
INB
M63
D03AU1517
M58
INA
M57
DTin(A)
Duty cycle=A Duty cycle=B
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
L68 22µL67 22µ
OUTA
Lout = 1.5 A Lout = 1.5 A
Functional description STA333W
16/49 Doc ID 13365 Rev 2
4 Functional description
4.1 Functional pins
4.1.1 Power-down function
Pin PWRDN (23) is used to power down the STA333W.
PWRDN = 0 (0 V): power-down state.
PWRND = 1 (VDD): normal operation.
During the power-down sequence the output begins to mute. After the mute condition is
reached the power stage is switched off and the output becomes high impedance. Then the
master clock to all internal hardware blocks is gated off. The PLL is also switched off. The
complete power-down sequence takes 13 million cycles.
4.1.2 Reset function
Pin RESET (31) is used to reset the STA333W.
RESET = 0 (0 V): reset state.
RESET = 1 (VDD): normal operation.
When pin RESET is forced to 0 the power stage is switched off (with high-impedance
output) and the master clock to all internal hardware blocks is gated off.
Note: Reset has a higher priority than power down.
STA333W Functional description
Doc ID 13365 Rev 2 17/49
4.2 Serial audio interface description
4.2.1 Serial audio interface protocols
The STA333W serial audio input was designed to interface with standard digital audio
components and to accept serial data formats. The STA333W always acts as a slave when
receiving audio input from standard digital audio components. Serial data for two channels
is provided using 3 input pins: left/right clock LRCKI (pin 29), serial clock BICKI (pin 28), and
serial data SDI (pin 30).
The available formats are showed in Tab l e 7 and Ta bl e 8 , and set through register CONFB
on page 24.
Figure 7. I2S
Figure 8. Left justified
1n
n-1
23
BICKI
SDI
LRCLKI
n
n-1
n
n-1
3
21 3
21
1n
n-1
n
n-1
23
SDI
BICKI
LRCLKI
123
I2C bus specification STA333W
18/49 Doc ID 13365 Rev 2
5 I2C bus specification
The STA333W supports the I2C protocol via the input ports SCL and SDA. This protocol
defines any device that sends data on to the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the data transfer is known as the master and
the other as the slave. The master always starts the transfer and provides the serial clock for
synchronization. The STA333W is always a slave device in all of its communications. It
supports up to 400 kb/s (fast-mode bit rate).
5.1 Communication protocol
5.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a START or STOP condition.
5.1.2 Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
5.1.3 Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between
STA333W and the bus master.
5.1.4 Data input
During the data input the STA333W samples the SDA signal on the rising edge of clock
SCL. For correct device operation the SDA signal must be stable during the rising edge of
the clock and the data can change only when the SCL line is low.
5.2 Device addressing
To start communication between the master and the STA333W, the master must initiate a
start condition. Following this, the master sends onto the SDA line 8 bits (MSB first)
corresponding to the device-select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus
definition. In the STA333W the I2C interface has two device addresses depending on the SA
port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode and
0 for write mode. After a START condition the STA333W identifies the device address on the
SDA bus and if a match is found, acknowledges the identification during the 9th bit time. The
byte following the device identification byte is the internal space address.
STA333W I2C bus specification
Doc ID 13365 Rev 2 19/49
5.3 Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA333W acknowledges this and then waits for the byte of internal address. After
receiving the internal byte address the STA333W again responds with an
acknowledgement.
5.3.1 Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the
STA333W. The master then terminates the transfer by generating a STOP condition.
5.3.2 Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Figure 9. Write-mode sequence
5.4 Read operation
5.4.1 Current address byte read
Following the START condition the master sends a device select code with the RW bit set
to 1. The STA333W acknowledges this and then responds by sending one byte of data. The
master then terminates the transfer by generating a STOP condition.
5.4.2 Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA333W. The master acknowledges each data
byte read and then generates a STOP condition terminating the transfer.
5.4.3 Random address byte read
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA333W acknowledges this and then the master writes the internal address byte.
After receiving, the internal byte address the STA333W again responds with an
acknowledgement. The master then initiates another START condition and sends the device
select code with the RW bit set to 1. The STA333W acknowledges this and then responds
by sending one byte of data. The master then terminates the transfer by generating a STOP
condition.
DEV-ADDR
ACK
START RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
BYTE
WRITE
DEV-ADDR
ACK
START RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
MULTIBYTE
WRITE
DATA IN
ACK
I2C bus specification STA333W
20/49 Doc ID 13365 Rev 2
5.4.4 Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are
read from sequential addresses within the STA333W. The master acknowledges each data
byte read and then generates a STOP condition to terminate the transfer.
Figure 10. Read-mode sequence
DEV-ADDR
ACK
START RW
DATA
NO ACK
STOP
CURRENT
ADDRESS
READ
DEV-ADDR
ACK
START RW
SUB-ADDR
ACK
DEV-ADDR
ACK
STOP
RANDOM
ADDRESS
READ
DATA
NO ACK
START RW
DEV-ADDR
ACK
START
DATA
ACK
DATA
ACK
STOP
SEQUENTIAL
CURRENT
READ
DATA
NO ACK
DEV-ADDR
ACK
START RW
SUB-ADDR
ACK
DEV-ADDR
ACK
SEQUENTIAL
RANDOM
READ
DATA
ACK
START RW
DATA
ACK NO ACK
STOP
DATA
RW=
HIGH
STA333W Register description
Doc ID 13365 Rev 2 21/49
6 Register description
Table 8. Register summary
Addr Name D7 D6 D5 D4 D3 D2 D1 D0
0x00 CONFA FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0
0x01 CONFB C2IM C1IM Reserved SAIFB SAI3 SAI2 SAI1 SAI0
0x02 CONFC OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0
0x03 CONFD Reserved ZDE Reserved
0x04 CONFE SVE ZCE DCCV PWMS AME NSBW MPC MPCV
0x05 CONFF EAPD PWDN ECLE LDTE BCLE IDE Reserved
0x06 MUTE Reserved C2M C1M MMUTE
0x07 MVOL MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0
0x08 C1VOL C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0
0x09 C2VOL C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0
0x0C AUTO Reserved AMAM2 AMAM1 AMAM0 AMAME
0x0E C1CFG Reserved C1VBP Reserved
0x0F C2CFG Reserved C2VBP Reserved
0x27 MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8
0x28 MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0
0x29 DCC1 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8
0x2A DCC2 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0
0x2B FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8
0x2C FDRC2 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0
0x2D STATUS PLLUL FAULT UVFAULT Reserved OCFAULT OCWARN TFAULT TWARN
0x2E BIST1 Reserved RO1BACT R5BACT R4BACT R3BACT R2BACT R1BACT
0x2F BIST2 Reserved R01BEND R5BEND R4BEND R3BEND R2BEND R1BEND
0x30 BIST3 Reserved R5BBAD R4BBAD R3BBAD R1BBAD R1BBAD
0x31 TSTCTL Reserved
0x32 C1PS C1PS7 C1PS6 C1PS5 C1PS4 C1PS3 C1PS2 C1PS1 C1PS0
0x33 C2PS C2PS7 C2PS6 C2PS5 C2PS4 C2PS3 C2PS2 C2PS1 C2PS0
0x34 OLIM OLIM7 OLIM6 OLIM5 OLIM4 OLIM3 OLIM2 OLIM1 OLIM0
Register description STA333W
22/49 Doc ID 13365 Rev 2
6.1 Configuration registers (addr 0x00 to 0x05)
6.1.1 Configuration register A (addr 0x00)
Master clock select
The STA333W supports sample rates of 32 kHz, 44.1 kHz, 48 KHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
z32.768 MHz for 32 kHz
z45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
z49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fS).
The relationship between the input clock and the input sample rate is determined by both
the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor
generating the internal clock and the IR bit determines the oversampling ratio used
internally.
D7 D6 D5 D4 D3 D2 D1 D0
FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0
01100011
Table 9. Master clock select
Bit R/W RST Name Description
0R/W1MCS0
Master clock select: Selects the ratio between the
input I2S sample frequency and the input clock.
1R/W1MCS1
2R/W0MCS2
Table 10. MCS bits
Input sample rate
fS (kHz) IR
MCS[2:0]
101 100 011 010 001 000
32, 44.1, 48 00 576 * fS128 * fS256 * fS384 * fS512 * fS768 * fS
88.2, 96 01 NA 64 * fS128 * fS192 * fS256 * fS384 * fS
176.4, 192 1X NA 32 * fS64 * fS96 * fS128 * fS192 * fS
STA333W Register description
Doc ID 13365 Rev 2 23/49
Interpolation ratio select
The STA333W has variable interpolation (oversampling) settings such that internal
processing and DDX output rates remain consistent. The first processing block interpolates
by either 2 times or 1 time (pass-through) or provides a 2-times downsample. The
oversampling ratio of this interpolation is determined by the IR bits.
Thermal warning recovery bypass
If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning
recovery determines if the -3 dB output limit is removed when thermal warning is negative.
If TWRB = 0 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit
is removed and the gain is added back to the system. If TWRB = 1 and TWAB = 0, then
when a thermal warning disappears the -3 dB output limit remains until TWRB is changed to
zero or the device is reset.
Table 11. Interpolation ratio select
Bit R/W RST Name Description
4:3 R/W 00 IR [1:0]
Interpolation ratio select: Selects internal
interpolation ratio based on input I2S sample
frequency.
Table 12. IR bit settings as a function of input sample rate
Input sample rate fS (kHz) IR 1st stage interpolation ratio
32 00 2-times oversampling
44.1 00 2-times oversampling
48 00 2-times oversampling
88.2 01 Pass-through
96 01 Pass-through
176.2 10 2-times downsampling
192 10 2-times downsampling
Table 13. Thermal warning recovery
Bit R/W RST Name Description
5R/W1TWRB
Thermal warning recovery bypass:
0: thermal warning recovery enabled
1: thermal warning recovery disabled
Register description STA333W
24/49 Doc ID 13365 Rev 2
Thermal warning adjustment bypass
The on-chip STA333W power output block provides feedback to the digital controller using
inputs to the power control block. The TWARN input is used to indicate a thermal warning
condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the
power control block will force a -3dB output limit (determined by TWOCL in coefficient RAM)
to the modulation limit in an attempt to eliminate the thermal warning condition. Once the
thermal warning output limit adjustment is applied, it remains in this state until reset, unless
FDRB = 0.
Fault detect recovery bypass
The on-chip STA333W power output block provides feedback to the digital controller using
inputs to the power control block. The FAULT input is used to indicate a fault condition (either
overcurrent or thermal). When FAULT is asserted (set to 0), the power control block attempts
a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the
power output block to begin recovery), holding it at 0 for period of time in the range of 0.1 ms
to 1 second as defined by the fault detect recovery constant register (FDRC registers 0x2B,
0x2C), then toggling it back to 1. This sequence is repeated as log as the fault indication
exists. This feature is enabled by default but can be bypassed by setting the FDRB control
bit to 1.
6.1.2 Configuration register B (addr 0x01)
Table 14. Thermal warning adjustment
Bit R/W RST Name Description
6R/W1TWAB
Thermal warning adjustment bypass:
0: thermal warning adjustment enabled
1: thermal warning adjustment disabled
Table 15. Fault detect recovery
Bit R/W RST Name Description
7R/W0FDRB
Fault detect recovery bypass:
0: fault detect recovery enabled
1: fault detect recovery disabled
D7 D6 D5 D4 D3 D2 D1 D0
C2IM C1IM Reserved SAIFB SAI3 SAI2 SAI1 SAI0
10000000
STA333W Register description
Doc ID 13365 Rev 2 25/49
Serial audio input interface format
Serial data interface
The STA333W audio serial input interfaces with standard digital audio components and
accepts a number of serial data formats. STA333W always acts a slave when receiving
audio input from standard digital audio components. Serial data for two channels is provided
using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data SDI.
Bits SAI and bit SAIFB are used to specify the serial data format. The default serial data
format is I2S, MSB first. Available formats are shown in the tables and figure that follow.
Serial data first bit
Table 16. Serial audio input interface format
Bit R/W RST Name Description
0R/W0SAI0
Determines the interface format of the input serial
digital audio interface.
1R/W0SAI1
2R/W0SAI2
3R/W0SAI3
Table 17. Serial data first bit
SAIFB Format
0 MSB-first
1 LSB-first
Table 18. Support serial audio input formats for MSB first (SAIFB = 0)
BICKI SAI [3:0] SAIFB Interface format
32 * fS
0000 0 I2S 15-bit data
0001 0 Left/right justified 16-bit data
48* fS
0000 0 I2S 16- to 23-bit data
0001 0 Left justified 16- to 24-bit data
0010 0 Right justified 24-bit data
0110 0 Right justified 20-bit data
1010 0 Right justified 18-bit data
1110 0 Right justified 16-bit data
Register description STA333W
26/49 Doc ID 13365 Rev 2
64* fS
0000 0 I2S 16- to 24-bit data
0001 0 Left justified 16- to 24-bit data
0010 0 Right justified 24-bit data
0110 0 Right justified 20-bit data
1010 0 Right justified 18-bit data
1110 0 Right justified 16-bit data
Table 19. Supported serial audio input formats for LSB-First (SAIFB = 1)
BICKI SAI[3:0] SAIFB Interface format
32* fS
1100 1 I2S 15-bit data
1110 1 Left/right justified 16-bit data
48* fS
0100 1 I2S 23-bit data
0100 1 I2S 20-bit data
1000 1 I2S 18-bit data
1100 1 LSB first I2S 16-bit data
0001 1 Left justified 24-bit data
0101 1 Left justified 20-bit data
1001 1 Left justified 18-bit data
1101 1 Left justified 16-bit data
0010 1 Right justified 24-bit data
48* fS
0110 1 Right justified 20-bit data
1010 1 Right justified 18-bit data
1110 1 Right justified 16-bit data
64* fS
0000 1 I2S 24-bit data
0100 1 I2S 20-bit data
1000 1 I2S 18-bit data
1100 1 LSB First I2S 16-bit data
0001 1 Left justified 24-bit data
0101 1 Left justified 20-bit data
1001 1 Left justified 18-bit data
1101 1 Left justified 16-bit data
0010 1 Right justified 24-bit data
0110 1 Right justified 20-bit data
1010 1 Right justified 18-bit data
1110 1 Right justified 16-bit data
Table 18. Support serial audio input formats for MSB first (SAIFB = 0) (continued)
STA333W Register description
Doc ID 13365 Rev 2 27/49
Channel input mapping
Each channel received via I2S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I2S input channel to its corresponding processing channel.
6.1.3 Configuration register C (addr 0x02)
DDX power output mode
DDX compensation pulse size register
Table 20. Channel input mapping
Bit R/W RST Name Description
6R/W0C1IM 0: processing channel 1 receives left I2S input
1: processing channel 1 receives right I2S input
7R/W0C2IM 0: processing channel 2 receives left I2S input
1: processing channel 2 receives right I2S input
D7 D6 D5 D4 D3 D2 D1 D0
OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0
10010111
Table 21. DDX power output mode
Bit R/W RST Name Description
0 R/W 1 OM0 The DDX power output mode selects the configuration
of the DDX output:
00: drop compensation
01: discrete output stage: tapered compensation
10: full-power mode
11: variable drop compensation (CSZx bits)
1R/W1OM1
Table 22. DDX compensating pulse size
Bit R/W RST Name Description
2 R/W 1 CSZ0 When OM[1:0] = 11, this register determines the size of
the DDX compensating pulse from 0 to 15 clock periods:
0000: 0 ns (0 ticks) compensating pulse size
0001: 20 ns (1 tick) clock period compensating pulse
size
.....
1111: 300 ns (15 ticks) clock period compensating pulse
size
3R/W0CSZ1
4R/W1CSZ2
5R/W0CSZ3
Register description STA333W
28/49 Doc ID 13365 Rev 2
Overcurrent warning detect adjustment bypass
The status bit OCWARN is used to warn of an overcurrent condition. When OCWARN is
asserted (set to 0), the power control block forces an adjustment to the modulation limit
(default -3dB) in an attempt to eliminate the overcurrent warning condition. Once the
overcurrent warning volume adjustment is applied, it remains applied until the device is
reset. The overcurrent limit can be changed via register OLIM (Output limit register (addr
0x34) on page 38).
6.1.4 Configuration register D (addr 0x03)
Zero-detect mute enable
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at
the data for each processing channel at the output of the crossover (bass management)
filter. If any channel receives 2048 consecutive zero value samples (regardless of fS) then
that individual channel is muted if this function is enabled.
6.1.5 Configuration register E (addr 0x04)
Max power correction variable
Table 23. Overcurrent warning detect adjustment bypass
Bit R/W RST Name Description
7R/W1OCRB 0: overcurrent warning adjustment enabled
1: overcurrent warning adjustment disabled
D7 D6 D5 D4 D3 D2 D1 D0
Reserved ZDE Reserved
01000000
Table 24. Zero detect mute enable
Bit R/W RST Name Description
6 R/W 1 ZDE 1: enable the automatic zero-detect mute
D7 D6 D5 D4 D3 D2 D1 D0
SVE ZCE DCCV PWMS AME NSBW MPC MPCV
11000010
Table 25. Max power correction variable
Bit R/W RST Name Description
0R/W0MPCV 0: use standard MPC coefficient
1: use MPCC bits for MPC coefficient
STA333W Register description
Doc ID 13365 Rev 2 29/49
Max power correction
Setting the MPC bit turns on special processing that corrects the STA333W power device at
high power. This mode lowers the THD+N of a full DDX system at maximum power output
and slightly below. If enabled, MPC is operational in all output modes except tapered
(OM[1:0] = 01) and binary. When OCFG = 00, MPC does not affect channels 3 and 4, the
line-out channels.
Noise-shaper bandwidth selection
AM mode enable
The STA333W features a DDX processing mode that minimizes the amount of noise
generated in frequency range of AM radio. This mode is intended for use when DDX is
operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to
approximately 83 dB in this mode, which is still greater than the SNR of AM radio.
PWM speed mode
Distortion compensation variable enable
Table 26. Max power correction
Bit R/W RST Name Description
1R/W1MPC 1: enable power bridge correction for THD reduction
near maximum power output.
Table 27. Noise-shaper bandwidth selection
Bit R/W RST Name Description
2R/W0NSBW 1: 3rd order NS
0: 4th order NS
Table 28. AM mode enable
Bit R/W RST Name Description
3R/W0AME 0: normal DDX operation
1: AM reduction mode DDX operation
Table 29. PWM speed mode
Bit R/W RST Name Description
4R/W0PWMS 0: normal speed (384 kHz) all channels
1: odd speed (341.3 kHz) all channels
Table 30. Distortion compensation variable enable
Bit R/W RST Name Description
5 R/W 0 DCCV 0: uses preset DC coefficient.
1: uses DCC coefficient.
Register description STA333W
30/49 Doc ID 13365 Rev 2
Zero-crossing volume enable
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital
zero-crossings no clicks will be audible.
Soft volume update enable
6.1.6 Configuration register F (addr 0x05)
Invalid Input detect mute enable
Setting the IDE bit enables this function, which looks at the input I2S data and will
automatically mute if the signals are perceived as invalid.
Binary output mode clock loss detection
Detects loss of input MCLK in binary mode and outputs 50% of the duty cycle.
Table 31. Zero-crossing volume enable
Bit R/W RST Name Description
6R/W1ZCE
1: volume adjustments will only occur at digital
zero-crossings
0: volume adjustments will occur immediately
Table 32. Zero-crossing volume enable
Bit R/W RST Name Description
7R/W1SVE
1: volume adjustments ramp according to SVR
settings
0: volume adjustments will occur immediately
D7 D6 D5 D4 D3 D2 D1 D0
EAPD PWDN ECLE LDTE BCLE IDE Reserved
0101110 0
Table 33. Invalid input detect mute enable
Bit R/W RST Name Description
2 R/W 1 IDE 1: enables the automatic invalid input detect mute
Table 34. Binary output mode clock loss detection
Bit R/W RST Name Description
3 R/W 1 BCLE Binary output mode clock loss detection enable
STA333W Register description
Doc ID 13365 Rev 2 31/49
LRCK double trigger protection
Actively prevents double trigger of LRCLK.
Auto EAPD on clock loss
When active will issue a power device power-down signal (EAPD) on clock loss detection.
IC power down
The PWDN register is used to put the IC in a low-power state. When PWDN is 0, the output
begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down
the power stage, then the master clock to all internal hardware except the I2C block is gated.
This puts the IC in a very low power consumption state.
External amplifier power down
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled).
Table 35. LRCK double trigger protection
Bit R/W RST Name Description
4 R/W 1 LDTE LRCLK double trigger protection enable
Table 36. Auto EAPD on clock loss
Bit R/W RST Name Description
5 R/W 0 ECLE Auto EAPD on clock loss
Table 37. Power down
Bit R/W RST Name Description
6R/W1PWDN 0: power down, low-power condition
1: normal operation
Table 38. External amplifier power down
Bit R/W RST Name Description
7 R/W 1 EAPD 0: external power stage power down active
1: normal operation
Register description STA333W
32/49 Doc ID 13365 Rev 2
6.2 Volume control registers (addr 0x06 to 0x09)
6.2.1 Mute/line output configuration register (addr 0x06)
Master mute
Channel mute
D7 D6 D5 D4 D3 D2 D1 D0
Reserved C2M C1M MMUTE
00000000
Table 39. Master mute
Bit R/W RST Name Description
0R/W0MMUTE 0: normal operation
1: all channels are in mute condition
Table 40. Channel mute
Bit R/W RST Name Description
1R/W0C1M
Channel 1 mute:
0: not muted, it is possible to set the channel volume
1: hardware muted
2R/W0C2M
Channel 2 mute:
0: not muted, it is possible to set the channel volume
1: hardware muted
STA333W Register description
Doc ID 13365 Rev 2 33/49
6.2.2 Master volume register (addr 0x07)
6.2.3 Channel volume (addr 0x08, 0x09)
Volume setting
The volume structure of the STA333W consists of individual volume registers for each
channel and a master volume register that provides an offset to each channels volume
setting. The individual channel volumes are adjustable in 0.5-dB steps from +48 dB to
-80 dB. As an example if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain
for channel 3 = +36 dB.
The master mute when set to 1 will mute all channels at once, whereas the individual
channel mutes (CxM) mute only that channel. Both the master mute and the channel mutes
provide a “soft mute” with the volume ramping down to mute in 4096 samples from the
maximum volume setting at the internal processing rate (about 96 kHz). A hard mute can be
obtained by commanding a value of all 1’s (255) to any channel volume register or the
master volume register. When volume offsets are provided via the master volume register
any channel that whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1 (configuration register F)
on a per channel basis as this creates the smoothest possible volume transitions. When
ZCE = 0, volume updates will occur immediately.
D7 D6 D5 D4 D3 D2 D1 D0
MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0
11111111
D7 D6 D5 D4 D3 D2 D1 D0
C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0
01100000
D7 D6 D5 D4 D3 D2 D1 D0
C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0
01100000
Table 41. Master volume offset as a function of MV
MV[7:0] Volume offset from channel value
00000000 (0x00) 0 dB
00000001 (0x01) -0.5 dB
00000010 (0x02) -1 dB
……
01001100 (0x4C) -38 dB
……
11111110 (0xFE) -127.5 dB
11111111 (0xFF) Hard master mute
Register description STA333W
34/49 Doc ID 13365 Rev 2
6.3 Automodes™ register (0x0C)
AM interference frequency switching
AMAM bits
Table 42. Channel volume as a function of CxV
CxV[7:0] Volume
00000000 (0x00) +48 dB
00000001 (0x01) +47.5 dB
00000010 (0x02) +47 dB
……
01011111 (0x5F) +0.5 dB
01100000 (0x60) 0 dB
01100001 (0x61) -0.5 dB
……
11010111 (0xD7) -59.5 dB
11011000 (0xD8) -60 dB
11011001 (0xD9) -61 dB
11011010 (0xDA) -62 dB
……
11101100 (0xEC) -80 dB
11101101 (0xED) Hard channel mute
……
11111111 (0xFF) Hard channel mute
D7 D6 D5 D4 D3 D2 D1 D0
Reserved AMAM2 AMAM1 AMAM0 AMAME
00000000
Table 43. AM interference frequency switching
Bit R/W RST Name Description
0R/W0AMAME 0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM setting
Table 44. Automodes™ AM switching frequency selection
AMAM[2:0] 48 kHz / 96 kHz input fS44.1 kHz / 88.2 kHz input fS
000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz
001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz
STA333W Register description
Doc ID 13365 Rev 2 35/49
6.4 Channel configuration registers (addr 0x0E, 0x0F)
Volume bypass
Each channel contains an individual channel volume bypass. If a particular channel has
volume bypassed via the CxVBP = 1 register then only the channel volume setting for that
particular channel affects the volume setting, the master volume setting will not affect that
channel.
6.5 Variable max power correction registers (addr 0x27, 0x28)
MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is
used in place of the default coefficient when MPCV = 1.
010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz
011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz
100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz
101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz
110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz
Table 44. Automodes™ AM switching frequency selection
D7 D6 D5 D4 D3 D2 D1 D0
Reserved C1VBP Reserved
00000000
D7 D6 D5 D4 D3 D2 D1 D0
Reserved C2VBP Reserved
00000000
D7 D6 D5 D4 D3 D2 D1 D0
MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8
00011010
D7 D6 D5 D4 D3 D2 D1 D0
MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0
11000000
Register description STA333W
36/49 Doc ID 13365 Rev 2
6.6 Variable distortion compensation registers (addr 0x29, 0x2A)
DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient
is used in place of the default coefficient when DCCV = 1.
6.7 Fault detect recovery constant registers (addr 0x2B, 0x2C)
FDRC bits specify the 16-bit fault detect recovery time delay. When status register bit FAULT
is asserted, the tristate output is immediately asserted low and held low for the time period
specified by this constant. A value of 0x0001 in this register is approximately 0.083 ms. The
default value of 0x000C gives approximately 0.1 ms.
Note: 0x0000 is a reserved value for this register pair. This value must not be used.
6.8 Device status register (addr 0x2D)
This read-only register provides the fault, warning and PLL status from the power control
block.
D7 D6 D5 D4 D3 D2 D1 D0
DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8
11110011
D7 D6 D5 D4 D3 D2 D1 D0
DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0
00110011
D7 D6 D5 D4 D3 D2 D1 D0
FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8
00000000
D7 D6 D5 D4 D3 D2 D1 D0
FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0
00001100
D7 D6 D5 D4 D3 D2 D1 D0
PLLUL FAULT UVFAULT Reserved OCFAULT OCWARN TFAULT TWARN
Table 45. Status bits description
Bit R/W RST Name Description
0RO- TWARN
Thermal warning:
0: junction temperature is close to the fault condition
1: normal operation
1RO- TFAULT
Thermal fault:
0: junction temperature limit detection
1: normal operation
STA333W Register description
Doc ID 13365 Rev 2 37/49
6.9 Reserved registers (addr 0x2E, 0x2F, 0x30, 0x31)
These registers are not to be used.
6.10 Postscale registers (addr 0x32, 0x33)
Postscale
The STA333W provides one additional multiplication after the last interpolation stage and
the distortion compensation on each channel, which can be used to limit the maximum
modulation index and therefore the peak current through the power device. The register
values represent an 8-bit signed fractional number. This number is extended to a 24-bit
number, by adding zeros to the right, and then directly multiplied by the data on that
channel. An independent postscale is provided for each channel but all channels can use
channel 1 postscale factor by setting the postscale link bit. By default, all postscale factors
are set to 0x7F (pass-through).
2RO- OCWARN
Overcurrent warning:
0: warning
1: normal operation
3RO- OCFAULT
Overcurrent fault:
0: fault detected
1: normal operation
4--- Reserved
5 RO - UVFAULT
Undervoltage warning:
0: VCCx below lower voltage threshold
1: normal operation
6RO- FAULT
Power bridge fault:
0: fault detected
1: normal operation
7 RO - PLLUL
PLL lock:
0: locked
1: not locked
Table 45. Status bits description (continued)
Bit R/W RST Name Description
D7 D6 D5 D4 D3 D2 D1 D0
C1PS7 C1PS6 C1PS5 C1PS4 C1PS3 C1PS2 C1PS1 C1PS0
01111111
D7 D6 D5 D4 D3 D2 D1 D0
C2PS7 C2PS6 C2PS5 C2PS4 C2PS3 C2PS2 C2PS1 C2PS0
01111111
Register description STA333W
38/49 Doc ID 13365 Rev 2
6.11 Output limit register (addr 0x34)
6.11.1 Thermal and overcurrent warning output limit register
The STA333W provides a simple mechanism for reacting to a thermal or overcurrent
warning in the power device. When the TWARN or OCWARN status bit is asserted, the
output is limited to the OLIM setting. The limit can be adjusted by modifying the thermal
warning/overcurrent output limit value. As for the normal postscale, the register value
represents an 8-bit signed fractional number. This number is extended to a 24-bit number,
by adding zeros to the right, and then directly multiplied by the data on both channels. The
scaling value range is from 0x80 = -1 to 0x7F = 0.992. To avoid phase changes in the output
signal only the positive range is used (0x00 to 0x7F). The default setting of 0x5A provides a
-3-dB limit.
If the cause of the limiting is a thermal warning, the output limiting is removed when the
thermal warning situation disappears. If the cause of the limiting is an overcurrent warning,
output limiting remains in effect until the device is reset.
D7 D6 D5 D4 D3 D2 D1 D0
OLIM7 OLIM6 OLIM5 OLIM4 OLIM3 OLIM2 OLIM1 OLIM0
01011010
Table 46. Output limit values for thermal and overcurrent warnings
OLIM[7:0] Attenuation (dB)
0x7F 0.06
0x7E 0.13
.... ....
0x5A 3.0
.... ....
0x40 6.0
.... ....
0x28 10
.... ....
0x01 42
0x00 Inf
STA333W Applications information
Doc ID 13365 Rev 2 39/49
7 Applications information
7.1 Applications scheme for power supplies
Figure 11 below shows a typical applications scheme for STA333W.
Special care has to be taken with regard to the power supplies when laying out the PCB. In
particular the 3.3-Ω resistors on the digital supplies (VDD_DIG) have to be placed as close
as possible to the device. This prevents unwanted oscillation on the digital parts of the
device due to the inductive effects of the PCB tracks. The same rule also applies to all the
decoulpling capacitors; they should be placed as close as possible to the device in order to
limit the effect of spikes on the supplies.
Figure 11. Applications diagram
7.2 PLL filter
It is recommended to use the circuit in Figure 12 below for the PLL loop filter to achieve the
best performance from the device in general applications. Note that the ground of this filter
has to be connected to the ground of the PLL without any resistive path.
For the component values, it should be remembered that the greater the filter bandwidth, the
shorter the lock time but the higher the PLL output jitter.
9
8
100nF
+
1000uF 35V
1nF
SCL
SDA
RESET
VCC
RESET
100nF
3V3
1uF 35V
100nF
100nF
1uF 35V
INTL
100nF
100nF
3V3
3V3
3R3
3R3
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
OUT2A
GND_SUB
1
SA
2
TEST_MODE
3
VSS
4
VCC_REG
5
OUT2B
6
GND2
7
VCC2
OUT2A
OUT1B
10
VCC1
11
GND1
12
OUT1A
13
GND_REG
14
VDD
15
CONFIG
16
NC
17
NC
18 NC 19
NC 20
VDD_DIG 21
GND_DIG 22
PWRDN 23
VDD_PLL 24
FILTER_PLL 25
PLL_GND 26
XTI 27
BICKI 28
LRCKI 29
SDI 30
RESET 31
INT_LINE 32
SDA 33
SCL 34
GND_DIG 35
VDD_DIG 36
OUT1B
DATA
PLL_FILT
OUT1A
10K
100nF
1nF
SCL
SDA
RESET
RESET
100nF
100nF
OUT2A
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
DATA
PLL_FILT
BEAD
BEADBEAD
PLL_GND GND_DIG
GND_DIG
GND_DIG
GND_DIG
9
8
100nF
+
1000uF 35V
1nF
SCL
SDA
RESET
VCC
RESET
100nF
3V3
1uF 35V
100nF
100nF
1uF 35V
INTL
100nF
100nF
3V3
3V3
3R3
3R3
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
OUT2A
GND_SUB
1
SA
2
TEST_MODE
3
VSS
4
VCC_REG
5
OUT2B
6
GND2
7
VCC2
OUT2A
OUT1B
10
VCC1
11
GND1
12
OUT1A
13
GND_REG
14
VDD
15
CONFIG
16
NC
17
NC
18 NC 19
NC 20
VDD_DIG 21
GND_DIG 22
PWRDN 23
VDD_PLL 24
FILTER_PLL 25
PLL_GND 26
XTI 27
BICKI 28
LRCKI 29
SDI 30
RESET 31
INT_LINE 32
SDA 33
SCL 34
GND_DIG 35
VDD_DIG 36
OUT1B
DATA
PLL_FILT
OUT1A
10K
100nF
1nF
SCL
SDA
RESET
RESET
100nF
100nF
OUT2A
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
DATA
PLL_FILT
BEAD
BEADBEAD
PLL_GND GND_DIG
GND_DIG
GND_DIG
GND_DIG
9
8
100nF
+
1000uF 35V
1nF
SCL
SDA
RESET
VCC
RESET
100nF
3V3
1uF 35V
100nF
100nF
1uF 35V
INTL
100nF
100nF
3V3
3V3
3R3
3R3
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
OUT2A
GND_SUB
1
SA
2
TEST_MODE
3
VSS
4
VCC_REG
5
OUT2B
6
GND2
7
VCC2
OUT2A
OUT1B
10
VCC1
11
GND1
12
OUT1A
13
GND_REG
14
VDD
15
CONFIG
16
NC
17
NC
18 NC 19
NC 20
VDD_DIG 21
GND_DIG 22
PWRDN 23
VDD_PLL 24
FILTER_PLL 25
PLL_GND 26
XTI 27
BICKI 28
LRCKI 29
SDI 30
RESET 31
INT_LINE 32
SDA 33
SCL 34
GND_DIG 35
VDD_DIG 36
OUT1B
DATA
PLL_FILT
OUT1A
10K
100nF
1nF
SCL
SDA
RESET
RESET
100nF
100nF
OUT2A
LRCKI
PWDN
3V3
OUT2B
XTI
BICKI
DATA
PLL_FILT
BEAD
BEADBEAD
PLL_GND GND_DIG
GND_DIG
GND_DIG
GND_DIG
Applications information STA333W
40/49 Doc ID 13365 Rev 2
Figure 12. PLL filter circuit
7.3 Typical output configuration
Figure 13 below shows a typical output configuration used for BTL stereo mode.
Figure 13. Output configuration for stereo BTL mode
100pF
FILTER_PLL
680pF
4.7nF
2K2
100pF
FILTER_PLL
680pF
4.7nF
2K2
BEAD
PLL_GNDGND_DIG
100pF
FILTER_PLL
680pF
4.7nF
2K2
100pF
FILTER_PLL
680pF
4.7nF
2K2
BEADBEAD
PLL_GNDGND_DIG
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
LEFT
100nF
6.2
OUT1A
OUT1B
6.2
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
RIGHT
100nF
6.2
OUT2A
OUT2B
6.2
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
LEFT
100nF
6.2
OUT1A
OUT1B
6.2
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
LEFT
100nF
6.2
OUT1A
OUT1B
6.2
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
RIGHT
100nF
6.2
OUT2A
OUT2B
6.2
22uH
22uH
100nF
100nF
470nF
330pF
100nF
22
RIGHT
100nF
6.2
OUT2A
OUT2B
6.2
STA333W Characterization data
Doc ID 13365 Rev 2 41/49
8 Characterization data
The following characterizations were made with RL = 8 Ω and f = 1 kHz unless otherwise
stated.
Figure 14. Output power vs. supply voltage (THD = 1%)
Figure 15. FFT 0 dBfs (VCC = 12 V)
0
5
10
15
20
25
30
57911 1315 17 19
Supply voltage, V
RKP
RKP
RKP
RKP
0
5
10
15
20
25
30
57911 1315 17 19
Output power, W
4Ω
6Ω
8Ω
16 Ω
-150
+10
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-150
+10
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Characterization data STA333W
42/49 Doc ID 13365 Rev 2
Figure 16. FFT -60 dBfs (VCC = 12 V)
Figure 17. THD vs. frequency (VCC = 12 V, Po = 1 W)
-150
+10
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-150
+10
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
0.01
1
0.02
0.05
0.1
0.2
0.5
%
20 20k50 100 200 500 1k 2k 5k 10k
Hz
4ohm
6ohm
8ohm
8 Ω
4 Ω
6 Ω
STA333W Characterization data
Doc ID 13365 Rev 2 43/49
Figure 18. FFT 0 dBfs (VCC = 18 V)
Figure 19. FFT -60 dBfs (VCC = 18 V)
Figure 20. THD vs. frequency (VCC = 18 V, Po = 1 W)
-150
+10
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-150
+10
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-150
+10
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-150
+10
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
0.01
1
0.02
0.05
0.1
0.2
0.5
%
20 20k50 100 200 500 1k 2k 5k 10k
Hz
4ohm6ohm
8ohm
0.01
1
0.02
0.05
0.1
0.2
0.5
%
20 20k50 100 200 500 1k 2k 5k 10k
Hz
4ohm6ohm
8ohm
4 Ω
6 Ω
8 Ω
Package thermal characteristics STA333W
44/49 Doc ID 13365 Rev 2
9 Package thermal characteristics
A thermal resistance of 25 °C/W can be achieved by mounting the device on a PCB which
has two copper ground areas of 3 x 3 cm and 16 vias (see Figure 21).
Given that the amount of power dissipated within the device depends primarily on the supply
voltage, load impedance and output modulation level the maximum estimated dissipated
power for the STA333W is 3 W.
With the above suggested board as heatsink, a maximum junction temperature rise, ∆Tj, of
75 °C is possible. In consumer environments where 50 °C is the maximum ambient
temperature this provides some safety margin before the intervention of the thermal
protection (T
j
= 150 °C).
Figure 21. Double-layer PCB with two copper ground areas and 16 vias
Figure 22 shows the power derating curve for the PowerSSO-36 package on PCBs with
copper areas of 2 x 2 cm2 and 3 x 3 cm2.
Figure 22. Power derating curve for PCB used as heatsink
0
1
2
3
4
5
6
7
8
0 20 40 60 80 100 120 140 160
Pd (W)
Tamb ( °C)
Copper Area 2x2 cm
and via holes
STA333W
PSSO36
Copper Area 3x3 cm
and via holes
0
1
2
3
4
5
6
7
8
0 20 40 60 80 100 120 140 160
0
1
2
3
4
5
6
7
8
0 20 40 60 80 100 120 140 160
Pd (W)
Tamb ( °C)
Copper Area 2x2 cm
and via holes
Copper Area 2x2 cm
and via holes
STA333W
PSSO36
STA333W
PSSO36
Copper Area 3x3 cm
and via holes
Copper Area 3x3 cm
and via holes
STA333W
PowerSSO-36
Package mechanical data STA333W
46/49 Doc ID 13365 Rev 2
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 47. PowerSSO-36 EPD dimensions
Symbol
Dimensions in mm Dimensions in inches
Min Typ Max Min Typ Max
A 2.15 - 2.47 0.085 - 0.097
A2 2.15 - 2.40 0.085 - 0.094
a1 0.00 - 0.10 0.000 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.40 - 7.60 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G- - 0.10 - - 0.004
H 10.10 - 10.50 0.398 - 0.413
h- - 0.40 - - 0.016
k 0 - 8 degrees 0 - 8 degrees
L 0.60 - 1.00 0.024 - 0.039
M - 4.30 - - 0.169 -
N - - 10 degrees - - 10 degrees
O - 1.20 - - 0.047 -
Q - 0.80 - - 0.031 -
S - 2.90 - - 0.114 -
T - 3.65 - - 0.144 -
U - 1.00 - - 0.039 -
X 4.10 - 4.70 0.161 - 0.185
Y 4.90 - 7.10 0.193 - 0.280
STA333W Trademarks and other acknowledgements
Doc ID 13365 Rev 2 47/49
11 Trademarks and other acknowledgements
DDX is a registered trademark of Apogee Technology Inc.
Automodes is a trademark of Apogee Technology Inc.
ECOPACK is a registered trademark of STMicroelectronics.
Sound Terminal is a trademark of STMicroelectronics.
Revision history STA333W
48/49 Doc ID 13365 Rev 2
12 Revision history
Table 48. Document revision history
Date Revision Changes
25-May-2007 1 Initial release.
21-Jan-2010 2
Updated features for operating voltage range, digital gain increments
and maximum power control on page 1
Updated description on page 1
Updated electrical specifications Ta b l e 4 , Tabl e 3 and Tabl e 5 o n
page 11
Added Section 3.3: Electrical specifications - digital section on
page 12
Added chapter Functional description on page 16
Updated usage of pin name SDA in first paragraph of Chapter 5: I2C
bus specification on page 18
Added Section 5.4: Read operation on page 19
Removed PSL (register add 0x03) in Table 8: Register summary on
page 21
Updated text concerning overcurrent warning for register CONFC on
page 27
Removed bit PSL in Configuration register D (addr 0x03) on page 28
Corrected reset value for register bit MPCV in Table 25 on page 28
Updated bit names and added register description table in Device
status register (addr 0x2D) on page 36
Updated text and added OLIM attenuation table in Output limit
register (addr 0x34) on page 38
Deleted mention of appsnote in Section 7.3 on page 40
Updated package Y (Min) dimension in Table 47 on page 46
Removed references to STA50x/51x throughout the document
STA333W
Doc ID 13365 Rev 2 49/49
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