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GENERAL DESCRIPTION
The DS21Q55DK is an easy-to-use evaluation board
for the DS21Q55 quad T1/E1/J1 transceiver. The
DS21Q55DK is intended to be used as a daughter
card with the DK101 motherboard or the DK2000
motherboard. The DS21Q55DK comes complete with
a DS21Q55 quad SCT, transformers, termination
resistors, configuration switches, line-protection
circuitry, network connectors, and motherboard
connectors. The DK101/DK2000 motherboard and
Dallas’ ChipView software give point-and-click
access to configuration and status registers from a
Windows®-based PC. On-board LEDs indicate
receive loss-of-signal and interrupt status. An on-
board FPGA contains mux logic to connect framer
ports to one another or to the DK2000 in a variety of
configurations.
Each DS21Q55DK is shipped with a free DK101
motherboard. For complex applications, the DK2000
high-performance demo kit motherboard can be
purchased separately.
Windows is a registered trademark of Microsoft Corp.
ORDERING INFORMATION
PART DESCRIPTION
DS21Q55DK DS21Q55 Demo Kit Daughter Card
(with included DK101 Motherboard)
FEATURES
Demonstrates Key Functions of DS21Q55
Quad T1/E1/J1 Transceiver
Includes DS21Q55 Quad LIU, Transformers,
BNC, and RJ45 Net work Connectors and
Termination Passives
Compatible with DK101 and DK2000 Demo Kit
Motherboards
DK101/DK2000 and ChipView Software
Provide Point-and-Click Access to the
DS21Q55 Register Set
All Equipment-Side Framer Pins are Easily
Accessible for External Data Source/Sink
Memory-Mapped FPGA Provides Flexible
Clock/Data/Sync Connections Among Framer
Ports and DK2000 Motherboard
LEDs for Loss-of-Signal and Interrupt Status
Easy-to-Read Silk-Screen Labels Identify the
Signals Associated with All Connectors,
Jumpers and LEDs
Network Interface Protection for Overvoltage
and Overcurrent Events
DESIGN KIT CONTENTS
DS21Q55DK Design Kit Daughter Card
DK101 Low-Cost Motherboard
CD-ROM
ChipView Software
DS21Q55DK Data Sheet
DK101 Data Sheet
DS21Q55 Data Sheet
DS21Q55 Errata Sheet
www.maxim-ic.com
DS21Q55D
K
Quad T1/E1/J1 Transceiver Design Kit
Daughter Card
DS21Q55DK Quad T1/E1/J1 Transceiver De sign Kit
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TABLE OF CONTENTS
COMPONENT LIST.....................................................................................................................3
BOARD FLOORPLAN.................................................................................................................4
ERRATA......................................................................................................................................4
BASIC OPERATION....................................................................................................................4
HARDWARE CONFIGURATION.....................................................................................................................4
Using the DK101 Processor Board: ..................................................................................................................... 4
Using the DK2000 Processor Board: ................................................................................................................... 4
General................................................................................................................................................................. 5
Miscellaneous....................................................................................................................................................... 5
QUICK SETUP (DEMO MODE).....................................................................................................................5
QUICK SETUP (REGISTER VIEW)........................................................................................................5
ADDRESS MAP ..........................................................................................................................6
FPGA REGISTER MAP ........................................................................................................................7
ID REGISTERS............................................................................................................................7
CONTROL REGISTERS..............................................................................................................8
FPGA CONTROL EXAMPLES..................................................................................................15
DS21Q55 INFORMATION.........................................................................................................17
DS21Q55DK INFORMATION....................................................................................................17
TECHNICAL SUPPORT............................................................................................................17
SCHEMATICS ...........................................................................................................................17
DOCUMENT REVISION HISTORY ...........................................................................................17
LIST OF TABLES
Table 1. Daughter Card Address Map........................................................................................................6
Table 2. FPGA Register Map .....................................................................................................................7
Table 3. TCLKx Source Definition..............................................................................................................8
Table 4. TSYSCLKx Source Definition.......................................................................................................9
Table 5. RSYSCLKx Source Definition.......................................................................................................9
Table 6. RSYNCx Function Definition ......................................................................................................11
Table 7. TSERx Source Definition............................................................................................................12
Table 8. FPGA Configuration for Scenario #1 (Port 1, T1 Mode).............................................................15
Table 9. FPGA Configuration for Scenario #2 (Port 1, T1 Mode).............................................................16
Table 10. DS21Q55 Partial Configuration for Scenario #2 (Port 1, T1 Mode)..........................................16
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COMPONEN T LIST
DESIGNATION QTY DESCRIPTION SUPPLIER PART
C1–C8 8
0.22μF, 50V capacitors Phycomp PCF1150CT-ND
C9, C10, C12, C18,
C22–C33, C35,
C38–C43 23 0.1μF 10%, 16V ceramic capacitors (0603) Phycomp 06032R104K7B20D
C11, C13–C15 4 0.1μF 10%, 25V ceramic capacitors (1206) Panasonic ECJ-3VB1E104K
C16, C17, C19–C21,
C34, C36, C45 8 1μF 10%, 16V ceramic capacitors (1206) Panasonic ECJ-3YB1C105K
C37, C44 2 10μF 20%, 10V ceramic capacitors (1206) Panasonic ECJ-3YB1A106M
CH1 1 Quad port choke Pulse T8132
DS1 1 LED, red, SMD Panasonic LN1251C
DS2–DS6 5 LED, green, SMD Panasonic LN1351C
F1–F16 16 1.25A, 250V fuse, SMT Teccor F1250T
J1 1 10-pin, dual row, vertical jumper Digi-Key S2012-05-ND
J2–J9 8 5-pin connectors, BNC right-angle vertical Cambridge CP-BNCPC-004
J10 1 8-pin 4-port jack, right-angle RJ 45 Molex 43223-8140
J11, J12 2 50-pin socket, SMD, dual row, vertical Samtec TFM-125-02-S-D-LC
J13 1 12-pin connector, dual ro w, vertical Digi-Key S2012-06-ND
R1, R2, R4 3 10kΩ 1%, 1/10W resistors (0805) Panasonic ERJ-6ENF1002V
R3, R26, R39, R41,
R45 5 10kΩ 5%, 1/10W resistors (0805) Panasonic ERJ-6GEYJ103V
R5–R12, R14–R21,
R48 17 0Ω 5%, 1/8W resistors (1206) Panasonic ERJ-8GEYJ0R00V
R13 1
470Ω 5%, 1/10W resistor (0805) Panasonic ERJ-6GEYJ471V
R22–R25 4
51.1Ω 1%, 1/10W resistors (0805) Panasonic ERJ-6ENF51R1V
R27, R28, R38 3 1.0kΩ 1%, 1/10W resistors (0805) Panasonic ERJ-6ENF1001V
R29–R36 8
61.9Ω 1%, 1/8W resistors (1206) Panasonic ERJ-8ENF61R9V
R37, R47 2 Not populated Panasonic Not populated
R40, R42–R44,
R46, R49 6 330Ω 0.1%, 1/10W MF resistors (0805) Panasonic ERA-6YEB331V
SW1–SW4 4 6-PIN TH Switch DPDT Tyco SSA22
T1 1 XFMR, XMIT/RCV, 1 to 2, SMT 32-pin Pulse TX1473
U1 1
XILINX spartan 2.5V FPGA
144-pin, 20 x 20 TQFP Xilinx XC2S50-5TQ144C
U2 1
Quad T1/E1/J1 transceiver
256-pin BGA, 0°C to +70°C
multichip module
Dallas
Semiconductor DS21Q55
U3 1 1M PROM for FPGA 44-pin TQFP Xilinx XC18V01VQ44C_U
U4 1
8-pin μMAX, SO
2.5V or ADJ Maxim MAX1792EUA25
U20 1
Serial configuration EEPROM for XILINX
65kb, 8-DIP Atmel AT17LV65EUA-NOPOP
Z1–Z8 8 50A, 6V Sidactor, DO214 SMD Teccor P0080SAMC
Z9–Z16 8 500A, 25V Sidactor, DO214 SMD Teccor P0300SCMC
Z17–Z32 16 500A, 170V Sidactor, DO214 SMD Teccor P1800SCMC
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BOARD FLOORPLAN
ERRATA
• Connector J1 has silk-screen misla beled such that the text TMS and TCK should be swapped. Worded
differently, TCK belongs to pin 7 and TMS belongs to pin 9.
• Switches SW1 to SW4 are missing silk screen to indicate which side is grounded. Sliding the switch toward the
BNC grounds the BNC shell (E1 mode). For T1 mode the switch should be slid away from the BNC.
BASIC OPERATION
This design kit relies up on several supporting files, which are available for down loading on our website at
www.maxim-ic.com/telecom. See the DS21Q55DK QuickView data sheet for these files.
Hardware Configuration
Using the DK101 Processor Board:
• Connect the daughter card to the DK101 processor b oard.
• Supply 3.3V to the banana-plug recepta cle s marked GND and VCC_3.3V. (The external 5V connector is
unused. Additionally, the ‘TIM 5V supply’ heade rs are unused.)
• All processor board DIP-switch settings should b e in the ON po sition with exception of the flash-programming
switch, which shoul d be OFF.
• From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs →
ChipView → ChipView.
Using the DK2000 Processor Board:
• Connect the daughter card to the DK2000 proces sor board.
• Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply may be connected
to connector J2.
• From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs →
ChipView → ChipView.
RJ45 x 4
BNC
PORT
4
BNC
PORT
3
BNC
PORT
2
BNC
PORT
1
LINE
PROTECTION
PORT 4
LINE
PROTECTION
PORT 3
LINE
PROTECTION
PORT 2
LINE
PROTECTION
PORT 1
DS21Q55
FPGA
CONFIG
PROM
CPU INTERFACE
CPU INTERFACE
FPGA
JTAG
PCM BUS
TEST POINTS
RLOS 1-4 LEDs
INT LED
FPGA
STATUS
LED
QUAD PORT
TRANSFORMER
QUAD PORT
CHOKE
2.5V FPGA
SUPPLY
IMPEDANCE
MATCHING/
LINE
PROTECTION
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General
• Upon power-up, the RLOS LEDs (green) will not be lit, the INT LED (red) will not be lit, but the FPGA status
LED (green) will be lit.
• When operating in E1 mode, slide SW1 –SW4 such that the BNC shell is grounded (to the left, as shown in the
board floorplan). When operating in T1 mode, en sure that SW1–S W4 are slid to the right as shown in the
board floorplan.
Miscellaneous
• Clock frequencies and certain pin bias levels are provided by a register-mapped FPGA, which is on the
DS21Q55 daughter card.
• The definition file for this FPGA is named DS21Q55DC_FPGA.def. The definitions are located on page 7. A
drop-down menu on the top of the screen allows for switching between definition files.
• All files referenced above are available for download as described in the section marked “BASIC OPERATION”
Quick Setup (Demo Mode)
• The PC will load ChipView offering a cho ice between DEMO MODE, REGISTER VIEW, and TERMINAL
MODE. Select Demo Mode.
• The program will request a configuration file, select am ong the displayed files
(DS2155_E1_DSNCO M_DRVR.cfg or DS2155_T1_ DSNCOM_DRVR.cfg).
• The Demo Mode screen will appear. Upon external loopback, the LOS and OOF indicators will extinguish.
• Note: Demo Mode interacts with the device driver, which is resident in the DK101/DK2000 firmware. The
current implementation of this driver is for one device. As such, the demo mode will only interact with Port 1.
With minor changes, the device drive r is extendible to N devices.
Quick Setup (Register View)
• The PC will load ChipView offering a cho ice between DEMO MODE, REGISTER VIEW, and TERMINAL
MODE. Select Register View.
• The program will request a definition file. Select DS21Q55DC_FPGA.def; through the ‘links’ section this will
also load DS21Q55DC.def .
• The Register View Screen will appear, showing the register name s, acronyms, and values for the DS21Q55
• Predefined register settings for several functions are available a s initialization files.
• INI files are loaded by selecting the menu File→Reg Ini File→Load Ini File
• Load the INI file DS21Q55_T1_BERT_ESF.ini
• After loading the INI file, the following may be observed:
− The RLOS LEDs (green) light upon exte rnal loopback.
− All four ports of the DS2Q155 begin tran smitting a Dal y pattern. When external loopback is applied, the
BERT bit count registers BBC1–3 and B E C1–3 may be updated by clearing and setting BC1.L C and
clicking the ‘Read All’ button.
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ADDRESS MAP
DK101 Daughter Card address space begin s at 0x81 000000.
DK2000 Daughter Card address space begins at:
0x30000000 for slot 0
0x40000000 for slot 1
0x50000000 for slot 2
0x60000000 for slot 3
All offsets given below are relative to the beginning of the daughter card addre ss space (shown above).
Table 1. Daughter Card Address Map
OFFSET DEVICE DESCRIPTION
0X0000
to
0X0015 FPGA Board identification and clock/signal routing
0X1000
to
0X10ff
T1/E1/J1
Transceiver #1 DS21Q55 T1/E1/J1 transce iver, port 1
0X2000
to
0X20ff
T1/E1/J1
Transceiver #2 DS21Q55 T1/E1/J1 transce iver, port 2
0X3000
to
0X30ff
T1/E1/J1
Transceiver #3 DS21Q55 T1/E1/J1 transce iver, port 3
0X4000
to
0X40ff
T1/E1/J1
Transceiver #4 DS21Q55 T1/E1/J1 transce iver, port 4
Registers in the FPGA may be easily modified using the ChipView host-b ased user-interface software along with
the definition file named “DS21Q55DC_FPGA.def.”
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FPGA Register Map
Table 2. FPGA Register Map
OFFSET REGISTER
NAME TYPE DESCRIPTION
0X0000 BID Read-Only
Board ID
0X0002 XBIDH Read-Only High-Nibble Extended Board ID
0X0003 XBIDM Read-Only Middle-Nibble Extended Board ID
0X0004 XBIDL Read-Only Low-Nibble Extended Board ID
0X0005 BREV Read-Only Board FAB Revision
0X0006 AREV Read-Only Board Assembly Revision
0X0007 PREV Read-Only PLD Revision
0X0011 MCSR Control
DS21Q55 MCLK Pin Source
0X0012 TCSR Control
DS21Q55 TCLK Pin Source
0X0013 SYSCLKT Control DS21Q55 TSYSCLK Pin Setting
0X0014 SYSCLKR Control DS21Q55 RSYSCLK Pin Setting
0X0015 SYNC1 Control
DS21Q55 TSYNC Source
0X0016 SYNC2 Control
DS21Q55 TSSYNC Source
0X0017 SYNC3 Control
DS21Q55 RSYNC Source
0X0018 TSERS Control
TSER Source
0X0019 PRSER Control
PCM RSER Source
0X001A PSYNC Control
PCM RSYNC/TSYNC Source
0X001B PCLK Control
PCM RCLK/TCLK Source
ID REGISTERS
BID: BOARD ID (Offset=0X 0000)
BID is read only with a value of 0xD
XBIDH: HIGH NIBBLE EXTENDED BOARD ID (Offset= 0X0002)
XBIDH is read only with a value of 0x0
XBIDM: MIDDLE NIBBLE EXTENDED BOARD ID (Offset=0X0003)
XBIDM is read only with a value of 0x1
XBIDL: LOW NIBBLE EXTENDED B OARD ID (Offset=0X00 04)
XBIDL is read only with a value of 0x6
BREV: BOARD FAB REVISION (Offset=0X000 5)
BREV is read only and displays the current fab revision
AREV: BOARD ASSEMBLY REVISION (Offset=0X0006)
AREV is read only and displays the current assembly revision
PREV: PLD REVISION (Offset=0X0007)
PREV is read only and displays the current PLD firmware revision
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CONTROL REGISTERS
Register Name: MCSR
Register Description: DS21Q55 MCLK Pin Source
Register Offset: 0x0011
Bit # 7 6 5 4 3 2 1 0
Name — — — — — — MSRCB MSRCA
Default — — — — — — 1 1
Bit 0: DS21Q55 Port 1 and 3 MCLK Source (MSRCA)
0 = Connect MCLK 1 (controls p ort 1 and 3) to the 1.544MHz clock
1 = Connect MCLK 1 (controls p ort 1 and 3) to the 2.048MHz clock
Bit 1: DS21Q55 Port 2 and 4 MCLK Source (MSRCA)
0 = Connect MCLK 2 (controls p ort 2 and 4) to the 1.544MHz clock
1 = Connect MCLK 2 (controls p ort 2 and 4) to the 2.048MHz clock
Register Name: TCSR
Register Description: DS21Q55 TCLK Pin Source
Register Offset: 0x0012
Bit # 7 6 5 4 3 2 1 0
Name T4S1 T4S0 T3S1 T3S0 T2S1 T2S0 T1S1 T1S0
Default 0 0 0 0 0 0 0 0
Bit 0 to 1: DS21Q55 Port 1 TCLK Source (T1S 0, T1S1)
The source for TCLK 1 is Defined as sho wn in Table 3.
Bit 2 to 3: DS21Q55 Port 2 TCLK Source (T2S 0, T2S1)
The source for TCLK 2 is Defined as sho wn in Table 3.
Bit 4 to 5: DS21Q55 Port 3 TCLK Source (T3S 0, T3S1)
The source for TCLK 3 is Defined as sho wn in Table 3.
Bit 6 to 7: DS21Q55 Port 4 TCLK Source (T4S 0, T4S1)
The source for TCLK 3 is Defined as sho wn in Table 3.
Table 3. TCLKx Source Definition
TxS1, TxS0 TCLK CONNECTION
00 Drive TCLKX with the 1.544MHz clock
01 Drive TCLKX with the 2.048MHz clock
10 Drive TCLKX with RCLKX
11 N/A
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Register Name: SYSCLKT
Register Description: DS21Q55 TSYSCLK Pin Setting
Register Offset: 0x0013
Bit # 7 6 5 4 3 2 1 0
Name R4S1 R4S0 R3S1 R3S0 R2S1 R2S0 R1S1 R1S0
Default 0 0 0 0 0 0 0 0
Bit 0 to 1: DS21Q55 Port 1 TSYSCLK Source (R1S0, R1S1)
The source for TSYSCLK 1 is Defined as shown in Table 4.
Bit 2 to 3: DS21Q55 Port 2 TSYSCLK Source (R2S0, R2S1)
The source for TSYSCLK 2 is Defined as shown in Table 4.
Bit 4 to 5: DS21Q55 Port 3 TSYSCLK Source (R3S0, R3S1)
The source for TSYSCLK 3 is Defined as shown in Table 4.
Bit 6 to 7: DS21Q55 Port 4 TSYSCLK Source (R4S0, R4S1)
The source for TSYSCLK 4 is Defined as shown in Table 4.
Table 4. TSYSCLKx Source Definition
RxS1, RxS0 TSYSCLKX CONNECTION
00 Drive TSYSCLKX with the 1.544MHz clock
01 Drive TSYSCLKX with the 2.048MHz clock
10 Drive TSYSCLK
X with 8.192MHz clock
11 Drive TSYSCLKX with DS21Q55 PortX BPCLK
Register Name: SYSCLKR
Register Description: DS21Q55 RSYSCLK Pin Setting
Register Offset: 0x0014
Bit # 7 6 5 4 3 2 1 0
Name T4S1 T4S0 T3S1 T3S0 T2S1 T2S0 T1S1 T1S0
Default 0 0 0 0 0 0 0 0
Bit 0 to 1: DS21Q55 Port 1 RSYSCLK Source (T1S0, T1S1)
The source for RSYSCLK 1 is Defined as shown in Table 5.
Bit 2 to 3: DS21Q55 Port 2 RSYSCLK Source (T2S0, T2S1)
The source for RSYSCLK 2 is Defined as shown in Table 5.
Bit 4 to 5: DS21Q55 Port 3 RSYSCLK Source (T3S0, T3S1)
The source for RSYSCLK 3 is Defined as shown in Table 5.
Bit 6 to 7: DS21Q55 Port 4 RSYSCLK Source (T4S0, T4S1)
The source for RSYSCLK 4 is Defined as shown in Table 5.
Table 5. RSYSCLKx Source Definition
TxS1, TxS0 RSYSCLKX CONNECTION
00 Drive RSYSCLKX with the 1.544MHz clock
01 Drive RSYSCLKX with the 2.048MHz clock
10 Drive RSYSCLK
X with 8.192MHz clock
11 Drive RSYSCLKX with DS21Q55 PortX BPCLK
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Register Name: SYNC1
Register Description: DS21Q55 TSYNC Pin Source
Register Offset: 0x0015
Bit # 7 6 5 4 3 2 1 0
Name — — — — T4SRC T3SRC T2SRC T1SRC
Default — — — — 0 0 0 0
Bit 0: DS21Q55 Port 1 TS YNC Source (T1SRC)
0 = TSYNC 1 is an output, tri-state corresponding FPGA driver pin (weak p ulldown)
1 = Drive TSYNC 1 with RSYNC 1
Bit 1: DS21Q55 Port 2 TS YNC Source (T2SRC)
0 = TSYNC 2 is an output, tri-state corresponding FPGA driver pin (weak p ulldown)
1 = Drive TSYNC 2 with RSYNC 2
Bit 2: DS21Q55 Port 3 TS YNC Source (T3SRC)
0 = TSYNC 3 is an output, tri-state corresponding FPGA driver pin (weak p ulldown)
1 = Drive TSYNC 3 with RSYNC 3
Bit 3: DS21Q55 Port 4 TS YNC Source (T4SRC)
0 = TSYNC 4 is an output, tri-state corresponding FPGA driver pin (weak p ulldown)
1 = Drive TSYNC 4 with RSYNC 4
Note: When driving TSYNCx with RSYNCx the corresponding DS21Q55 port should be configured such that
TSYNCx is an input (IOCR1.1 = 0) and RSYNCx is an output (IOCR1.4 = 0).
Register Name: SYNC2
Register Description: DS21Q55 TSSYNC Pin Source
Register Offset: 0x0016
Bit # 7 6 5 4 3 2 1 0
Name — — — — T4SRC T3SRC T2SRC T1SRC
Default — — — — 0 0 0 0
Bit 0: DS21Q55 Port 1 TS SYNC Source (T1SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 1 with RSYNC 1
Bit 1: DS21Q55 Port 2 TS SYNC Source (T2SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 2 with RSYNC 2
Bit 2: DS21Q55 Port 3 TS SYNC Source (T3SRC)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 3 with RSYNC 3
Bit 3: DS21Q55 Port 4 TSSYNC Source (T4Source)
0 = Not using transmit-side elastic store, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSSYNC 4 with RSYNC 4
Note: When driving TSSYNCx with RSYNCx the corresponding DS21Q55 port should be configured such that
RSYNCx is an output (IOCR1.4 = 0).
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Register Name: SYNC3
Register Description: DS21Q55 RSYNC Pin Setting
Register Offset: 0x0017
Bit # 7 6 5 4 3 2 1 0
Name RSOR1 RSOR0 — — R4IO R3IO R2IO R1IO
Default 0 0 — — 0 0 0 0
Bit 0: DS21Q55 Port 1 RS YNC Setting (R1IO)
0 = RSYNC 1 is an output, tri-state corresponding FPGA driver pin (weak p ulldown)
1 = Drive RSYNC 1 with R SYNCX as shown in Table 6
Bit 1: DS21Q55 Port 2 RS YNC Setting (R2IO)
0 = RSYNC 2 is an output, tri-state corresponding FPGA driver pin (weak p ulldown)
1 = Drive RSYNC 2 with R SYNC X as shown in Table 6
Bit 2: DS21Q55 Port 3 RS YNC Setting (R3IO)
0 = RSYNC 3 is an output, tri-state corresponding FPGA driver pin (weak p ulldown)
1 = Drive RSYNC 4 with R SYNCX as shown in Table 6
Bit 3: DS21Q55 Port 4 RS YNC Setting (R4IO)
0 = RSYNC 4 is an output, tri-state corresponding FPGA driver pin (weak p ulldown)
1 = Drive RSYNC 4 with R SYNCX as shown in Table 6
Note: When driving RSYNCy with RSYNCx the corresponding DS21Q55 port should be configured su ch that
RSYNCx is an output (IOCR1.4 = 0) and RSYNCy is an input (IOCR1.4 = 1).
Table 6. RSYNCx Function Definition
RSOR1, RSOR0 MASTER RSYNC DESIGNATION
00 RSYNC 1 is used to drive other RSYNC pins (providing RXIO = 1)
01 RSYNC 2 is used to drive other RSYNC pins (providing RXIO = 1)
10 RSYNC 3 is used to drive other RSYNC pins (providing RXIO = 1)
11 RSYNC 4 is used to drive other RSYNC pins (providing RXIO = 1)
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Register Name: TSERS
Register Description: DS21Q55 TSER Pin Source
Register Offset: 0x0018
Bit # 7 6 5 4 3 2 1 0
Name T4S1 T4S0 T3S1 T3S0 T2S1 T2S0 T1S1 T1S0
Default 0 0 0 0 0 0 0 0
Bit 0 to 1: DS21Q55 Port 1 TSER Source (T1S0, T1S1)
The source for TSER 1 is Defined as shown in Table 7 .
Bit 2 to 3: DS21Q55 Port 2 TSER Source (T2S0, T2S1)
The source for TSER 2 is Defined as shown in Table 7 .
Bit 4 to 5: DS21Q55 Port 3 TSER Source (T3S0, T3S1)
The source for TSER 3 is Defined as shown in Table 7 .
Bit 6 to 7: DS21Q55 Port 4 TSER Source (T4S0, T4S1)
The source for TSER 4 is Defined as shown in Table 7 .
Table 7. TSERx Source Definition
TxS1, TxS0 TSERX CONNECTION
00 Tri-state TSERX (weak pulldown)
01 Drive TSERX with RSERX
10 Drive TSERX with PCM_TXD bus (DK 2000 only)
11 N/A
Register Name: PRSER
Register Description: PCM RSER Source
Register Offset: 0x0019
Bit # 7 6 5 4 3 2 1 0
Name — — — — R1EN R1EN R1EN R1EN
Default — — — — 0 0 0 0
Bit 0 to 1: PCM RSER Source (R1EN)
0 = Do not drive DS21Q55 Port 1 RSER onto PCM_RSER
1 = Logically OR DS21Q5 5 Port 1 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 2 to 3: DS21Q55 Port 2 TSER Source (T2S0, T2S1)
0 = Do not drive DS21Q55 Port 2 RSER onto PCM_RSER
1 = Logically OR DS21Q5 5 Port 2 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 4 to 5: DS21Q55 Port 3 TSER Source (T3S0, T3S1)
0 = Do not drive DS21Q55 Port 3 RSER onto PCM_RSER
1 = Logically OR DS21Q5 5 Port 3 RSER with selected other RSER pins and drive onto PCM_RSER
Bit 6 to 7: DS21Q55 Port 4 TSER Source (T4S0, T4S1)
0 = Do not drive DS21Q55 Port 4 RSER onto PCM_RSER
1 = Logically OR DS21Q5 5 Port 4 RSER with selected other RSER pins and drive onto PCM_RSER
Note: PRSER register is for use with th e DK2000 only.
DS21Q55DK Quad T1/E1/J1 Transceiver De sign Kit
13 of 32
Register Name: PSYNC
Register Description: PCM RSYNC/TSYNC Source
Register Offset: 0x001A
Bit # 7 6 5 4 3 2 1 0
Name — — T2SR T1SR — — R2SR R1SR
Default — — 0 0 — — 0 0
Bit 0 to 1: PCM_RSYNC Source
R2SR, R1SR PCM_RSYNC Source
00 PCM_RSYNC is driven by DS21Q55 po rt 1 RSYNC.
01 PCM_RSYNC is driven by DS21Q55 po rt 2 RSYNC.
10 PCM_RSYNC is driven by DS21Q55 po rt 3 RSYNC.
11 PCM_RSYNC is driven by DS21Q55 po rt 4 RSYNC.
Bit 4 to 5: PCM_TSYNC Source
T2SR, T1SR PCM_TSYNC Source
00 PCM_TSYNC is driven by DS21Q55 port 1 TSYNC.
01 PCM_TSYNC is driven by DS21Q55 port 2 TSYNC.
10 PCM_TSYNC is driven by DS21Q55 port 3 TSYNC.
11 PCM_TSYNC is driven by DS21Q55 port 4 TSYNC.
Note: PSYNC register is for use with the DK2000 only.
DS21Q55DK Quad T1/E1/J1 Transceiver De sign Kit
14 of 32
Register Name: PCLK
Register Description: PCM RCLK/TCLK Source
Register Offset: 0x001B
Bit # 7 6 5 4 3 2 1 0
Name — TCM T2SR T1SR — RCM R2SR R1SR
Default — 0 0 0 — 0 0 0
Bit 0 to 2: PCM_RCLK Source
RCM, R2SR, R1SR PCM_RCLK Source
000 PCM_RCLK is driven by DS21Q55 port 1 RCLK.
001 PCM_RCLK is driven by DS21Q55 port 2 RCLK.
010 PCM_RCLK is driven by DS21Q55 port 3 RCLK.
011 PCM_RCLK is driven by DS21Q55 port 4 RCLK.
100 PCM_RCLK is driven by DS21Q55 port 1 BPCLK.
101 PCM_RCLK is driven by DS21Q55 port 2 BPCLK.
110 PCM_RCLK is driven by DS21Q55 port 3 BPCLK.
111 PCM_RCLK is driven by DS21Q55 port 4 BPCLK.
Bit 4 to 5: PCM_TCLK Source
TCM, T2SR, T1SR PCM_TCLK Source
000 PCM_TCLK is driven by source used for DS21Q55 port 1 TCLK.
001 PCM_TCLK is driven by source used for DS21Q55 port 2 TCLK.
010 PCM_TCLK is driven by source used for DS21Q55 port 3 TCLK.
011 PCM_TCLK is driven by source used for DS21Q55 port 4 TCLK.
100 PCM_TCLK is driven by DS21Q55 port 1 BPCLK.
101 PCM_TCLK is driven by DS21Q55 port 2 BPCLK.
110 PCM_TCLK is driven by DS21Q55 port 3 BPCLK.
111 PCM_TCLK is driven by DS21Q55 port 4 BPCLK.
Note: PCLK register is for use with the DK2000 only.
DS21Q55DK Quad T1/E1/J1 Transceiver De sign Kit
15 of 32
FPGA CONTROL EXAMPLES
Table 8. FPGA Configuration for Scenario #1 (Port 1, T1 Mode)
REGISTER SETTING FUNCTION
MCSR 0X01 Drive DS21Q55 ports 1 and 3 MCLK with 2.048MHz
TCSR 0X00 Drive TCLK with 1.544MHz
SYSCLKT 0X00 Drive TSYSCLK with 1.544MHz
SYSCLKR 0X00 Drive RSYSCLK with 1.544MHz
SYNC1 0X00 Tri-state FPGA driver pin for DS21Q55 TSYNC1
SYNC2 0X01 Drive TSSYNC1 with RSYNC1
SYNC3 0X00 Tri-state FPGA driver pin for DS21Q55 RSYNC
TSERS 0X02 Drive DS21Q55 TSER1 with data from PCM bus
PRSER 0X01 Drive DS21Q55 RSER1 onto PCM bus
PSYNC 0X00
PCM RSYNC and PCM TSYNC are provided by DS21Q55 port 1 RSYNC an d
TSYNC (respectively)
PCLK 0X44 PCM RCLK and TCLK are driven by port 1 BPCLK
TSER
TCLK
BPCLK
TSYNC
RSER
RCLK
BPCLK
RSYNC
DS21Q55 PCM_TXD
PCM_TCLK
PCM_TSYNC
PCM_RXD
PCM_RCLK
PCM_RSYNC
DK2000
XO
SCENARIO #1: DS21Q55 TO/FROM DK2000
DS21Q55DK Quad T1/E1/J1 Transceiver De sign Kit
16 of 32
Table 9. FPGA Configuration for Scenario #2 (Port 1, T1 Mode)
REGISTER SETTING FUNCTION
MCSR 0X01 Drive DS21Q55 ports 1 and 3 MCLK with 2.048MHz
TCSR 0X02 Drive TCLK1 with RCLK1
SYSCLKT 0X00 Drive TSYSCLK with 1.544MHz
SYSCLKR 0X00 Drive RSYSCLK with 1.544MHz
SYNC1 0X01 Drive TSYNC1 with RSYNC1
SYNC2 0X01 Drive TSSYNC1 with RSYNC1
SYNC3 0X00 Tri-state FPGA driver pin for DS21Q55 RSYNC
TSERS 0X01 Drive DS21Q55 TSER1 with data from RSER1
PRSER N/A Unused
PSYNC N/A Unused
PCLK N/A Unused
Table 10. DS21Q55 Partial Configuration for Scenario #2 (Port 1, T1 Mode)
REGISTER SETTING FUNCTION
IOCR1 TSIO = 0;
RSIO = 0 TSYNc is an input, RSYNC is an output
ESCR TESE = 0;
RESE = 0 Bypass Rx and Tx elastic stores
CCR1 TCSS1 = 0;
TCSS2 = 0 TCLK is driven by TCLK pin
SCENARIO #2: EXTERNAL REMOTE LOOPB ACK
(
FULL BANDWIDTH
,
NOT JUST PAYLOAD
)
TSER
TCLK
BPCLK
TSYNC
RSER
RCLK
BPCLK
RSYNC
DS21Q55
DS21Q55DK Quad T1/E1/J1 Transceiver De sign Kit
17 of 32
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.
DS21Q55 INFORMATION
For more information about the DS21Q55, please consult the DS21Q55 data sheet available on our website at
www.maxm-ic.com/DS21Q55. Software downloads are also available for this demo kit.
DS21Q55DK INFORMATION
For more information about the DS21Q55DK, including software downloads, please consult the DS21Q55DK data
sheet available on our web site at www.maxim-ic.com/telecom.
TECHNICAL S UPPORT
For additional technical support, please e-mail your questions to telecom.support@dalsemi.com.
SCHEMATICS
The DS21Q55DK schemat i cs are featured in the following page s.
DOCUMENT REVISION HISTORY
REVISION
DATE DESCRIPTION
121903 Initial DS21Q55DK data sheet release.
012506 Changed part number for CH1 in Component List from “TX1473” to “T8132.”
110106 Updated schematics.
REVISIONS:
A1: 3/7/2003 - REPLACED THE SYMBOL XC2S50E_U WITH SYMBOL XC2S50_U.
DS21Q55 DESIGN KIT
/
CONTENTS
DS21Q55DK02A1
STEVE SCULLY
14. SIGNAL CROSS-REFERENCE
1. COVER PAGE
2. DS21Q55 CONTROL AND BACKPLANE
9. TIM ADDRESS DATA BUS CONNECTION
8. PORT 4 TX / RX ANALOG PATHS
3. PORT 1 AND 2 TX / RX SYSTEM SIDE
4. PORT 3 AND 4 TX / RX SYSTEM SIDE
7. PORT 3 TX / RX ANALOG PATHS
6. PORT 2 TX / RX ANALOG PATHS
5. PORT 1 TX / RX ANALOG PATHS
15. COMPONENT CROSS-REFERENCE
2/24/03
15
10. FPGA CROSS CONNECT FOR RX / TX SIGNALS
11. FPGA AND CONFIG PROM CONTROL
12. FPGA CLOCK AND DATABUS
13. SUPPLY DECOUPLING
1
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
/
DS21Q55DK02A1
STEVE SCULLY
2/24/03
15
2
1
TP3
2
1
R48
K3
U18
C5
G18
W4
U19
D11
G19
W2
U16
W19
V20
D5
D4
J18
H19
T2
R2
W18
E4
J17
P1
N2
V17
H18
U10
W20
T1
K2
V18
W13
V19
N1
Y15
U1
N17
L20
H20
B9
B7
A5
B11
A20
A17
W8
U6
H3
P18
M20
M17
G20
C4
B6
B3
A9
D18
C16
C12
B12
V5
U2
N4
J3
U4
V4
U5
U9
U7
W15
J19
U11
K17
B5
A14
P3
P2
P4
U8
H4
V8
T4
V2
L17
U3
U2
1
TP2
A1
D_AD0
D_AD1
A2
A3
A5
A7
A6
CS1
CS2
D_AD4
D_AD5
D_AD7
D_AD3
A4
D_AD2
LIUC
MUX
BTS
INT
TSTRST
MCLK2
MCLK1
A0
JTD_SCT2PROM
WR_RW
CS4
CS3
D_AD6
JTDI_CON2SCT
JTCLK
RD_DS
JTMS
JTRST
0
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
CONTROL
DS21Q55_U
DVDD3<1>
MUX
LIUC
BTS
INT*
TSTRST
MCLK2
MCLK1
NC2
NC1
D3
D7
D6
D5
D4
D2
DVDD2<1>
CS2*
CS1*
CS3*
A6
A7
A5
A4
A3
A2
A1
A0
JTDO
JTDI
JTCLK
JTMS
RD*
WR*
CS4*
DVSS2<1>
DVSS3<3>
DVDD2<2>
DVDD2<3>
DVDD3<4>
DVDD3<3>
DVDD3<2>
DVDD1<3>
DVDD1<2>
DVDD1<1>
DVDD1<4>
DVDD2<4>
DVSS1<1>
TVSS3
TVSS2
TVSS1
TVSS4
DVSS1<2>
DVSS1<3>
DVSS2<2>
DVSS2<3>
DVSS3<1>
DVSS3<2>
DVSS4<1>
DVSS4<2>
DVSS4<3>
RVSS1<1>
RVSS1<2>
RVSS2<1>
RVSS2<2>
RVSS3<2>
RVSS3<1>
RVSS4<2>
RVSS4<1>
DVDD4<1>
DVDD4<2>
DVDD4<3>
DVDD4<4>
RVDD2
RVDD1
RVDD3
RVDD4
TVDD1
TVDD3
TVDD2
TVDD4
D1
D0
JTRST*
/
3
DS21Q55DK02A1
STEVE SCULLY
2/24/03
15
Y1
W11
V1
W12
W10
W9
Y2
V7
W3
T3
R1
W5
V3
W7
V6
Y9
V10
W1
Y10
H1
G1
K1
L2
J2
Y11
L4
R4
L3
R3
L1
H2
G2
F1
K4
M3
M4
N3
J1
M2
J4
V9
W6
M1
U2
Y3
A19
D20
B18
C18
C17
Y4
C19
C20
B20
F19
E19
E20
E18
D19
B19
A18
F20
Y13
F17
D12
C15
B16
D15
Y14
A16
B14
B15
D13
D16
E17
A13
A12
D17
C14
A15
B13 D14
G17
C13
B17
F18
H17
U2
RCLK2
TSYSCLK2
TSSYNC1
TSYNC2
TSYNC1
RLOS1
RLOS2
TCLK2
BPCLK1
RSYSCLK1
RTIP1
TRING1
TTIP1
RTIP2
TRING2
TTIP2
RRING2
TSER2
RSER1
RSYNC1
TCLK1
TSER1
TSYSCLK1
TSSYNC2
BPCLK2
RSYNC2
RSYSCLK2
RSER2
RRING1
RCLK1
ESIBR0
ESIBRD
ESIBR1
ESIBR0
ESIBRD
ESIBR1
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
PORT
DS21Q55_U
RPOSI
RNEGI
RCLKI
RPOSO
RRING
RCLK
RNEGO
TTIP
TRING
TNEGO
ESIBRD
TPOSO
TPOSI
TCLKI
RCLKO
RLOS/LOTC
BPCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSER
RSYSCLK
RSYNC
RMSYNC
RSIG
RSIGF
RFSYNC
TSYNC
TSSYNC
TSYSCLK
TSER
TCHBLK
TCHCLK
TSIG
TLINK
TLCLK
ESIBR0
ESIBR1
TCLKO
TNEGI
RTIP
TCLK
PORT
DS21Q55_U
RPOSI
RNEGI
RCLKI
RPOSO
RRING
RCLK
RNEGO
TTIP
TRING
TNEGO
ESIBRD
TPOSO
TPOSI
TCLKI
RCLKO
RLOS/LOTC
BPCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSER
RSYSCLK
RSYNC
RMSYNC
RSIG
RSIGF
RFSYNC
TSYNC
TSSYNC
TSYSCLK
TSER
TCHBLK
TCHCLK
TSIG
TLINK
TLCLK
ESIBR0
ESIBR1
TCLKO
TNEGI
RTIP
TCLK
/
4
2/24/03
15
DS21Q55DK02A1
STEVE SCULLY
Y5
A11
C7
D10
A10
C10
Y6
C9
A8
D9
D8
C6
D6
A7
C8
B10
B8
C11
Y16
G3
D1
D2
C1
E2
Y17
B1
B2
C2
A1
F2
E1
A3
D3
A2
B4
A4
E3 F3
G4
C3
A6
D7
F4
U2
Y7
N18
R18
K19
L19
K20
Y8
N19
R19
N20
R20
T19
T18
P19
P20
M19
L18
U20
Y19
W14
V12
V16
Y18
W17
Y20
U15
V15
U17
P17
W16
V11
U12
K18
V14
T17
R17
M18 U14
Y12
U13
J20
T20
V13
U2
TSYNC4
TSSYNC4
TSYNC3
RTIP4
TTIP4
RRING3
RTIP3
TRING3
TTIP3
TCLK3
TSSYNC3
TSYSCLK3
TSER3
RSYNC3
RSYSCLK3
RSER3
RCLK3
RRING4
TCLK4
RCLK4
TSYSCLK4
TSER4
RSYNC4
RSYSCLK4
RSER4
RLOS3
BPCLK3 TRING4
RLOS4
BPCLK4
ESIBR0
ESIBRD
ESIBR1
ESIBR0
ESIBRD
ESIBR1
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
PORT
DS21Q55_U
RPOSI
RNEGI
RCLKI
RPOSO
RRING
RCLK
RNEGO
TTIP
TRING
TNEGO
ESIBRD
TPOSO
TPOSI
TCLKI
RCLKO
RLOS/LOTC
BPCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSER
RSYSCLK
RSYNC
RMSYNC
RSIG
RSIGF
RFSYNC
TSYNC
TSSYNC
TSYSCLK
TSER
TCHBLK
TCHCLK
TSIG
TLINK
TLCLK
ESIBR0
ESIBR1
TCLKO
TNEGI
RTIP
TCLK
PORT
DS21Q55_U
RPOSI
RNEGI
RCLKI
RPOSO
RRING
RCLK
RNEGO
TTIP
TRING
TNEGO
ESIBRD
TPOSO
TPOSI
TCLKI
RCLKO
RLOS/LOTC
BPCLK
RLINK
RLCLK
RCHBLK
RCHCLK
RSER
RSYSCLK
RSYNC
RMSYNC
RSIG
RSIGF
RFSYNC
TSYNC
TSSYNC
TSYSCLK
TSER
TCHBLK
TCHCLK
TSIG
TLINK
TLCLK
ESIBR0
ESIBR1
TCLKO
TNEGI
RTIP
TCLK
/
15
2/24/03
STEVE SCULLY
5
DS21Q55DK02A1
2
1
R18
2
1
R19
2
1
C14
2
1
R30
2
1
R31
1
2
Z7
15 18
16 17
T1
2
1
R20
2
1
R21
2
1
C16
1
2
Z8
20
14
1913
T1
2
1
C6
2
1
C7
17
18
16
15
CH1
1
2
Z20
1
2
Z27
2
1
Z24
2
1
Z16
2
1
F7
2
1
F8
2
1
Z29
A8
A7
A6
A5
A4
A3
A2
A1
J10
1
2
J5
2
1
R23
6
54
3
2
1
SW4
19
20
14
13
CH1
1
2
Z15
2
1
F16
2
1
F15
1
2
J9
1.25 AMP
1.25 AMP
RRING1
RTIP1
TRING1
TTIP1
0
0
0.1UF
61.9
0
0
1UF
0.22UF
0.22UF
51.1
50A
500A 500A
500A
RJ45_4PORT
500A
500A 500A
50A
61.9
1.25 AMP
1.25 AMP
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
CONN_BNC_5PIN
DPDT
Z
Z
RCV
Z
XMIT
Z
Z
Z
Z
Z
6
5
RJ45
7
4
3
2
1
8
CONN_BNC_5PIN
/
2/24/03
6
DS21Q55DK02A1
STEVE SCULLY
15
2
1
R29
2
1
R7
1
2
R8
2
1
R11
2
1
C13
2
1
R34
1
2
Z2
1
2
Z4
11
22
12
21
T1
2
1
C5
21
22
12
11
CH1
24
9
23
10
T1
2
1
C8
23
24
10
9
CH1
2
1
R12
2
1
C19
2
1
Z18
1
2
Z22
2
1
Z14
2
1
F5
2
1
F6
1
2
Z30
1
2
Z26
2
1
Z13
2
1
F14
B8
B7
B6
B5
B4
B3
B2
B1
J10
1
2
J4
2
1
R24
6
54
3
2
1
SW2
2
1
F13
1
2
J8
RRING2
RTIP2
TRING2
TTIP2
0
0
0
0.1UF
61.9
0.22UF
0.22UF
0
1UF
1.25 AMP
1.25 AMP
1.25 AMP
51.1
1.25 AMP
61.9
50A
500A
500A 500A
RJ45_4PORT
500A
500A
500A
50A
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
Z
6
5
RJ45
7
4
3
2
1
8
CONN_BNC_5PIN
DPDT
Z
Z
RCV
XMIT
Z Z
Z
Z Z
CONN_BNC_5PIN
/
7
DS21Q55DK02A1
STEVE SCULLY
2/24/03
15
2
1
C15
2
1
R16
2
1
R17
2
1
R33
2
1
R32
2
1
R14
2
1
R15
2
1
C17
1
2
Z5
7
26
8
25
T1
2
1
C4
25
26
8
7
CH1
1
2
Z19
1
2
Z25
2
1
Z23
2
1
F4
2
1
Z12
2
1
F3
2
1
Z31
C8
C7
C6
C5
C4
C3
C2
C1
J10
1
2
J3
1
2
Z6
28
5
27
6
T1
2
1
C3
27
28
6
5
CH1
2
1
Z11
2
1
F12
2
1
F11
1
2
J7
2
1
R22
6
54
3
2
1
SW3
50A
61.9
61.9
500A 500A
500A
RJ45_4PORT
500A500A
500A
50A
51.1
1.25 AMP
1.25 AMP
1.25 AMP
1.25 AMP
0.22UF
1UF
0
0
0
0
0.1UF
TTIP3
TRING3
RTIP3
RRING3
0.22UF
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
Z
CONN_BNC_5PIN
Z
RCV
Z
Z
Z
Z
Z
6
5
RJ45
7
4
3
2
1
8
CONN_BNC_5PIN
Z
XMIT
DPDT
/
15
8
2/24/03
STEVE SCULLY
DS21Q55DK02A1
2
1
R5
2
1
R6
1
2
R36
2
1
R9
2
1
R10
2
1
C20
2
1
C11
1
2
R35
1
2
Z1
3
30
4
29
T1
2
1
C1
29
30
4
3
CH1
1
2
Z3
32
1
31
2
T1
2
1
C2
31
32
2
1
CH1
2
1
Z21
1
2
Z17
2
1
Z9
2
1
F2
2
1
F1
D8
D7
D6
D5
D4
D3
D2
D1
J10
2
1
Z32
1
2
Z28
1
2
Z10
2
1
F10
2
1
F9
1
2
J2
2
1
R25
6
54
3
2
1
SW1
1
2
J6
51.1
1.25 AMP
1.25 AMP
1.25 AMP
1.25 AMP
0.22UF
61.9
0.1UF
1UF
0
0
0
0
TTIP4
TRING4
RTIP4
RRING4
0.22UF
50A
500A
500A500A
RJ45_4PORT
500A
500A
500A
50A
61.9
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
Z
Z
CONN_BNC_5PIN
Z
RCV
Z
XMIT
DPDT
Z Z
Z
6
5
RJ45
7
4
3
2
1
8
Z
CONN_BNC_5PIN
JX
(TIM LSB)
/
J1X
9
STEVE SCULLY
2/24/03
15
DS21Q55DK02A1
12
11
10
9
8
7
65
4
3
2
1
J13
22
21
20
19
1817
1615
1413
12
11
10
9
8
7
65
4
3
5049
48
47
4645
2
4443
42
41
40
39
38
37
3635
3433
32
31
30
29
28
27
2625
2423
1
J11
22
21
20
19
18
17
1615
1413
12
11
10
9
8
7
65
4
3
5049
4847
4645
2
4443
42
41
40
39
3837
3635
3433
32
31
30
29
2827
2625
2423
1
J12
D_AD4
A5
D_AD3
A4
A1
A0
A9
A3
A8
D_AD7
D_AD6
D_AD5
D_AD2
D_AD1
D_AD0
A7
A6
CS_T
A10
A11
TIM5V
A15
A14
PCM_TXCLK
PCM_TSYNC
PCM_TXD
PCM_RXD
PCM_RXCLK
RW_T
CPU_RESET
PCM_RSYNC
AUX_CLK
INT
CLK16384_T
CLK1544_T
WE_T
A2
A13
A12
TIM5V
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
CON12P
5049
48
47
4645
4443
42
41
40
39
38
37
3635
3433
32
31
30
29
28
27
2423
22
21
17
11
7
4
25 26
20
19
9
1
8
16
12
10
2
14
3
65
18
15
13
5049
4847
4645
4443
42
41
40
39
3837
3635
3433
32
31
30
29
2827
2423
22
21
17
11
7
4
25 26
20
19
9
1
8
16
12
10
2
14
3
65
18
15
13
V3_3
/
2/24/03
1510
DS21Q55DK02A1
STEVE SCULLY
132
137
121
77
83
120
94
75
84
114
96
116
87
103
93
79
80
117
100
101
86
122
140
74
139
123
131
85
130
112
102
95
133
126
134
124 138
129
99
113
141
118
78
136
115
76
91
88
U1
TCLK2
BPCLK2
RSYNC2
TSYNC2
TSYSCLK2
RSYSCLK2
RSER2
TSER2
RCLK2
TSER1
AUX_CLK
RSER1
TSYSCLK1
RSYSCLK1
BPCLK1
TCLK1
RCLK1
PCM_RXD
PCM_TXD
TSSYNC1
TSYNC1
RSYNC1
TSYNC4
TSSYNC4
PCM_RSYNC
PCM_TSYNC
RSER4
TSER4
RCLK4
TCLK4
BPCLK4
RSYSCLK4
TSYSCLK4
RSYNC4
RSER3
TSER3
RCLK3
TCLK3
BPCLK3
RSYNC3
TSSYNC2
RSYSCLK3
TSYSCLK3
TSYNC3
TSSYNC3
PCM_RXCLK
PCM_TXCLK
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
BANK 6
I/O PORT
BANK 7
BANK 4
BANK 5
XC2S50_U
IO7_4
IO10_4
IO11_4
IO1_5
IO3_6/D3
IO2_6
IO1_6/TRDY_6
IO1_4
IO3_4/VREF2_4
IO2_4
IO5_4
IO6_4
IO11_7
IO12_7/IRDY_7
IO10_7
IO9_7/VREF2_7
IO8_7
IO7_7
IO6_7
IO5_7
IO8_4
IO9_4/VREF1_4
GCK0
IO12_4
IO2_5/VREF1_5
IO3_5
IO4_5
IO7_5
IO6_5
IO5_5
IO3_7/VREF1_7
IO4_7
IO1_7
IO2_7
IO13_6
IO11_6
IO12_6
IO10_6/VREF2_6
IO9_6
IO8_6
IO7_6
IO6_6
IO5_6
IO4_6/VREF1_6
IO9_5
IO8_5/VREF2_5
GCK1
IO4_4
SERIAL EEPROM OPTION - UNPOPULATED
/
J2.TDO
FPGA
TDI
CONFIG
TDO
PROM
JTAG CONFIGURATION
TESTPOINT
TDI
TDO
DS21Q55
J2.TDI
STEVE SCULLY
2/24/03DS21Q55DK02A1
15
11
2
1
R47
2
1
R37
54
8
7
3
2
6
1
U20
1
2
R13
107
90
71
70
53
36
35
16
144
127
108
1
125
97
92
82
55
24
14
9
142
34
32
2
69
105
104
106
111
109
81
73
61
52
45
33
25
17
143
135
128
119
110
98
89
8
72
37
U1
10
9
8
7
6 5
4
3
2
1
J1
1
2
R38
2
1
R27
2
1
R28
36
26
16
8
38
35
17
5
31
3
7
13
41
28
18
6
19
14
25
9
27
42
29
40
43
10
21
15
U3
NOPOP
1.0K
1.0K
1.0K
NOPOP
470
JTMS
JTD_PROM2SPART
JTCLK
JTDO_SPART2CON
CCLK
DONE
XRST
JTD_SCT2PROM
DONE
CCLK
XRST
JTDO_SPART2CON
JTD_PROM2SPART
CPU_RESET
CFG_DIN
CCLK
XRST
DONE
CFG_DIN
X_INIT
JTDI_CON2SCT
JTMS
JTCLK
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
XC2S50_U
CONTROL
VCCO12
VCCO11
VCCO10
VCCO9
VCCINT6
GND6
DONE
VCCO2
VCCO1
VCCO3
VCCO4
VCCO8
VCCINT3
GND4
GND14
GND15
TCK
TDI
VCCINT4
VCCINT5
TMS
GND13
GND12
GND9
GND10
GND11
GND8
GND7
GND5
GND3
GND2
GND1
GND16
TDO
M2
M0
NC1
NC2
M1
PROGRAM*
CCLK
VCCINT2
VCCINT1
VCCO7
VCCO6
VCCO5
VCCINT8
VCCINT7
V3_3
4
2
8
10
3
1
5
9
CONN_10P
6
7
V3_3
AT17LV65
CE
RESET
CLK
SER_EN
CEO
GND
VCCDATA
V3_3
V3_3
V2_5
VQ44C
XC18V02
VCCO3
VCCO2
VCCO1
VCC3
VCC2
VCC1
CLK
CF*
OE_RESET*
CEO*
CE*
TMS
TCK
TDO
TDI
D0
D1
D2
D3
D4
D5
D6
D7
VCCO4
GND1
GND2
GND3
GND4
/
/
ALL UNMARKED BIAS RESISTORS ARE 10K
12 15
2/24/03
STEVE SCULLY
DS21Q55DK02A1
2
1
DS6
2
1
R49
2
1
R42
1
2
R46
2
1
DS1
2
1
R44
2
1
R43
2
1
R40
2
1
DS2
2
1
DS3
2
1
DS4
2
1
DS5
1
2
R41
1
2
R39
1
2
R45
22
10
21
63
60
59
27
13
62
44
11
5
29
46
26
56
7
40
47
43
65
48
28
20
6
49
50
42
67
3
30
12
68
51
31
66
54
38
4
39
57
19
23
58
41
64
15
18
U1
1
2
R2
1
2
R3
2
1
R4
2
1
R1
JTRST
RED
LIUC
ESIBRD
INT
ESIBR1
ESIBR0
TSTRST
RLOS3_IND
330
330
RED
330
RLOS1_IND
RED
330
330
RED
RED
RLOS4_IND
RED
INT_IND
RLOS2_IND
330
CFG_DIN
A6
D_AD4
D_AD5
D_AD2
D_AD3
A4
A2
A3
D_AD6
CLK1544_T
A0
A1
CS1
CS2
CS4
A5
A15
RLOS1
CPU_RESET
CS3
BTS
WE_T
INT
A7
D_AD0
INT_IND
CLK16384_T
A12
A13
A14
RLOS3
RLOS2
RLOS1_IND
RLOS4
RLOS2_IND
RLOS4_IND
X_INIT
MCLK1
MCLK2
D_AD1
RLOS3_IND
RD_DS
WR_RW
MUX
RW_T
CS_T
D_AD7
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
I/O PORT
BANK 3
BANK 1
BANK 2
BANK 0
XC2S50_U
IO3_0
IO4_1/VREF1_1
IO3_1
IO12_2/DIN/D0
IO6_1
IO5_1
IO5_0
IO7_0/VREF2_0
IO6_0
IO1_1/CS*
IO2_1/WRITE*
GCK3
IO9_0
IO8_0
IO8_2
IO9_2
IO11_2
IO4_0
IO10_3/VREF2_3
IO9_3
IO13_2/DOUT/BUSY
IO10_2/VREF2_2
IO7_2/D1
IO5_2
IO6_2/D2
IO4_2/VREF1_2
IO3_2/D3
IO2_2
IO1_2/IRDY_2
IO1_0
IO2_0/VREF1_0
IO8_1
IO9_1/VREF2_1
GCK2
IO13_3/TRDY_3
IO12_3
IO11_3/D4
IO7_3/D6
IO8_3/D5
IO5_3
IO6_3
IO4_3/VREF1_3
IO2_3/D7
IO3_3
IO1_3/INIT*
IO10_1
IO11_1
IO7_1
V3_3
V3_3
V3_3
/
DS21Q55DK02A1
STEVE SCULLY
2/24/03
1513
2
1
C44
2
1
C45
2
1
R26
2
1
C36
2
1
C34
1
2
C37
1
2
C21
54
8
7
3
2
6
1
U4
1
1
1
1
2
1
C43
1
2
C31
1
2
C9
1
2
C18
1
2
C40
1
2
C25
1
2
C22
2
1
C10
1
2
C30
2
1
C27
2
1
C39
2
1
C12
1
2
C32
1
2
C29
2
1
C33
1
2
C24
2
1
C42
2
1
C26
2
1
C38
2
1
C23
2
1
C28
2
1
C41
2
1
C35
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
1UF
1UF
10K
1UF
X_INIT
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
VCC
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V3_3
V2_5
V2_5V3_3
MAX1792
IN
OUT
SET
GND
OUT
IN
SHDN
RST
TP TP TP TP
V3_3
CFG_DIN 11A4> 11B8<> 12B1<>
RLOS4_IND 12A3<> 12A5<>
RRING1 3C8< 5B8<
RRING2 3C4< 6B8<
RRING3 4C8< 7B8<
RRING4 4C4< 8B8<
RSYNC3 4B6<> 10B3<>
RSYNC2 3B1<> 10D4<>
RSYNC1 3B6<> 10B6<>
RSER4 4B1> 10A5<>
RSER3 4B6> 10C3<>
RSER2 3C1> 10D5<>
RSER1 3C6> 10C6<>
*** Signal Cross-Reference for the entire design ***
A0 9D6<> 12C5<> 2B7<
A1 9C6<> 12C5<> 2B7<
A2 9C6<> 12C5<> 2B7<
A3 9C6<> 12C5<> 2B7<
A4 9C6<> 12C5<> 2B7<
A5 9C6<> 12B5<> 2A7<
A6 9C6<> 12B5<> 2A7<
A7 9C6<> 12B5<> 2A7<
A8 9C6<>
A9 9C6<>
A10 9C3<>
RSYNC4 4B1<> 10A5<>
RSYSCLK1 10B6<> 3B6<
RSYSCLK2 10D5<> 3B1<
RSYSCLK3 10B3<> 4B6<
RSYSCLK4 10A5<> 4B1<
RTIP1 3C8< 5B8<
RTIP2 3C4< 6B8<
RTIP3 4C8< 7B8<
RTIP4 4C4< 8B8<
RW_T 9C6<> 12C1<>
TCLK1 10C6<> 3C8<
TCLK2 10D5<> 3C4<
TCLK3 10C3<> 4C8<
TCLK4 10A5<> 4C4<
TIM5V 9D3<> 9D8<>
TRING1 3C8> 5C8<
TRING2 3C4> 6C8<
TRING3 4C8> 7C8<
TRING4 4C4> 8C8<
TSER1 10C6<> 3B6<
TSER2 10D5<> 3B1<
TSER3 10C3<> 4B6<
TSER4 10A5<> 4B1<
TSSYNC1 10B6<> 3B6<
TSSYNC2 10C3<> 3B1<
TSSYNC3 10B3<> 4B6<
TSSYNC4 10A4<> 4B1<
TSTRST 2C3< 12D8<
TSYNC1 3B6<> 10B6<>
X_INIT 11A6<> 12A3<> 13D4<>
XRST 11A6> 11B8> 11C2<
WR_RW 12C1<> 2C7<
WE_T 9B6<> 12C1<>
TTIP4 4C4> 8C8<
TTIP3 4C8> 7C8<
TTIP2 3C4> 6C8<
TTIP1 3C8> 5C8<
TSYSCLK4 10A5<> 4B1<
TSYSCLK3 10B3<> 4B6<
TSYSCLK2 10D5<> 3B1<
TSYSCLK1 10B6<> 3B6<
TSYNC4 4B1<> 10A5<>
TSYNC3 4B6<> 10B3<>
TSYNC2 3B1<> 10D5<>
A12 9C3<> 12A4<>
A13 9C3<> 12A4<>
A14 9B3<> 12A4<>
A15 9B3<> 12A3<>
CCLK 11A6< 11B8< 11C1<
CPU_RESET 9B6<> 12B1<> 11C1<
ESIBRD 3B4<> 3B8<> 4A4<> 4A8<> 12D6<
ESIBR1 3A4<> 3A8<> 4A4<> 4A8<> 12C6<
ESIBR0 3A4<> 3A8<> 4A4<> 4A8<> 12C6<
D_AD7 2B3<> 9B6<> 12D4<>
D_AD6 2B3<> 9B6<> 12D4<>
D_AD5 2B3<> 9B6<> 12D3<>
D_AD4 2B3<> 9B6<> 12D3<>
D_AD3 2B3<> 9B6<> 12D3<>
D_AD2 2B3<> 9B6<> 12D3<>
D_AD1 2B3<> 9B6<> 12D3<>
D_AD0 2B3<> 9B6<> 12D3<>
DONE 11B8<> 11A6< 11C1<
CS_T 9B8<> 12C1<>
A11 9C3<>
AUX_CLK 9B8<> 10C7<
BPCLK1 3C6> 10C6<>
BPCLK2 3C1> 10D5<>
BPCLK3 4C6> 10C3<>
BPCLK4 4C1> 10A5<>
BTS 12C1<> 2C3<
CLK1544_T 9B2<> 12C5<
CLK16384_T 9C4<> 12D3<
CS4 12B1<> 2C7<
CS3 12B1<> 2C7<
CS2 12B1<> 2C7<
CS1 12B1<> 2C7<
INT 2C3> 9B8<> 12B5<> 12D6<
INT_IND 12B5<> 12D3<>
JTCLK 11A8<> 2B7< 11C1<
JTDO_SPART2CON 11A7<> 11C1>
JTD_PROM2SPART 11A6<> 11D1<
JTMS 11A8<> 2B7< 11D1<
PCM_RSYNC 9C8<> 10A4<>
PCM_RXCLK 9C8<> 10B3<>
PCM_RXD 9C8<> 10B7<>
PCM_TSYNC 9C8<> 10A4<>
PCM_TXCLK 9C8<> 10B3<>
PCM_TXD 9C8<> 10B7<>
RLOS1_IND 12A3<> 12A5<>
RLOS2_IND 12A3<> 12A5<>
RLOS3_IND 12A3<> 12A5<>
MUX 12C1<> 2B3<
MCLK2 12D3<> 2C3<
MCLK1 12D3<> 2C3<
LIUC 2C3< 12D6<
JTRST 2B7<> 12D8<
JTD_SCT2PROM 2B8<> 11A6<
JTDI_CON2SCT 11A8<> 2B8<
RLOS4 4C1> 12A3<>
RLOS3 4C6> 12A3<>
RLOS2 3C1> 12A3<>
RLOS1 3C6> 12A3<>
RD_DS 12C1<> 2C7<
RCLK4 4C4> 10A5<>
RCLK3 4C8> 10C3<>
RCLK2 3C4> 10D5<>
RCLK1 3C8> 10C6<>
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
Z5 SIDACTOR_2 7B6
Z6 SIDACTOR_2 7C6
Z7 SIDACTOR_2 5B6
Z8 SIDACTOR_2 5C6
Z9 SIDACTOR_2 8B4
Z10 SIDACTOR_2 8C4
Z11 SIDACTOR_2 7C4
Z12 SIDACTOR_2 7B4
Z13 SIDACTOR_2 6C4
Z14 SIDACTOR_2 6B4
Z15 SIDACTOR_2 5C4
Z16 SIDACTOR_2 5B4
Z17 SIDACTOR_2 8A4
Z18 SIDACTOR_2 6A4
Z19 SIDACTOR_2 7A4
Z20 SIDACTOR_2 5A4
Z21 SIDACTOR_2 8A4
Z22 SIDACTOR_2 6A4
Z23 SIDACTOR_2 7A4
Z24 SIDACTOR_2 5A4
Z25 SIDACTOR_2 7C4
Z26 SIDACTOR_2 6C4
Z27 SIDACTOR_2 5C4
Z28 SIDACTOR_2 8C4
Z29 SIDACTOR_2 5C4
Z30 SIDACTOR_2 6C4
Z31 SIDACTOR_2 7C4
Z32 SIDACTOR_2 8C4
J7 CONN_BNC_5PIN 7D2
J8 CONN_BNC_5PIN 6D2
J9 CONN_BNC_5PIN 5D2
J10 RJ45_8 5C3 6C3 7C3 8C3
J11 CONN_50P2 9D7
R5 RES 8B7
R4 RES1 12D6
R3 RES 12D7
R2 RES1 12D7
R1 RES1 12D6
J13 CON12P 9D8
J12 CONN_50P2 9D3
*** Part Cross-Reference for the entire design ***
C1 CAP 8B5
C2 CAP 8C5
C3 CAP 7C5
C4 CAP 7B5
C5 CAP 6B5
C6 CAP 5B5
C7 CAP 5C5
C8 CAP 6C5
C9 CAP 13B7
C10 CAP 13B5
C11 CAP 8A6 R6 RES 8B7
8C5
R7 RES 6B7
R8 RES 6B7
R9 RES 8C7
R10 RES 8D7
R11 RES 6C7
R12 RES 6D7
R13 RES 11C2
R14 RES 7C7
R15 RES 7D7
R16 RES 7B7
R17 RES 7B7
R18 RES 5B7
R19 RES 5B7
R20 RES 5C7
R21 RES 5D7
R22 RES 7B2
R23 RES 5B2
R24 RES 6B2
R25 RES 8B2
R26 RES 13D4
R27 RES1 11A7
R28 RES1 11A8
R29 RES1 6A6
R30 RES1 5A6
R31 RES1 5A6
R32 RES1 7A6
R33 RES1 7A6
R34 RES1 6A6
R35 RES1 8A6
R36 RES1 8A6
R37 RES1 11B7
R38 RES1 11A7
R39 RES 12C6
R40 RES1 12A6
R41 RES 12C6
R42 RES1 12A6
R43 RES1 12A6
R44 RES1 12A6
R45 RES 12D6
R46 RES1 12B6
R47 RES1 11A7
R48 RES 2B7
R49 RES1 12B2
SW1 SWITCH_DPDT_SLIDE_6P 8C1
SW2 SWITCH_DPDT_SLIDE_6P 6C1
SW3 SWITCH_DPDT_SLIDE_6P 7C1
SW4 SWITCH_DPDT_SLIDE_6P 5C1
T1 XFMR_QUADPORT_T1 5B5 5C5 6B5 6C5 7B5 7C5 8B5
Z4 SIDACTOR_2 6C6
Z3 SIDACTOR_2 8C6
Z2 SIDACTOR_2 6B6
Z1 SIDACTOR_2 8B6
U20 AT17LV65 11C7
U4 MAX1792 13D4
U3 XC18V02VQ44C_U 11A6
U2 DS21Q55_U 2D7 3C3 3C7 4C3 4C7
U1 XC2S50_U 10C5 11C3 12C3
TP26 TSTPNT_SNG 13B4
TP25 TSTPNT_SNG 13B4
TP24 TSTPNT_SNG 13B4
TP3 TESTPOINT 2B8
TP2 TESTPOINT 2B8
TP1 TSTPNT_SNG 13B3
C12 CAP 13B4
C13 CAP 6A6
C14 CAP 5A6
C15 CAP 7A6
C16 CAP 5D6
C17 CAP 7D6
C18 CAP 13B7
C19 CAP 6C6
C20 CAP 8C6
C21 CAP 13C4
C22 CAP 13B5
C23 CAP 13B2
C24 CAP 13B2
C25 CAP 13B6
C26 CAP 13B1
C27 CAP 13B4
C28 CAP 13B2
C29 CAP 13B3
C30 CAP 13B5
C31 CAP 13B7
C32 CAP 13B3
C33 CAP 13B2
C34 CAP 13D3
C35 CAP 13B1
C36 CAP 13D2
C37 CAP 13D3
C38 CAP 13B3
C39 CAP 13B4
C40 CAP 13B6
C41 CAP 13B2
C42 CAP 13B2
C43 CAP 13B8
C44 CAP 13B8
C45 CAP 13B8
CH1 CHOKE_QUADPORT_T1 5B4 5C4 6B4 6C4 7B4 7C4 8B4
8C4
DS1 LED 12B5
DS2 LED 12A5
DS3 LED 12A5
DS4 LED 12A5
DS5 LED 12B5
DS6 LED 12B2
F1 FUSE 8B4
F2 FUSE 8B4
F3 FUSE 7B4
F4 FUSE 7B4
F5 FUSE 6B3
F8 FUSE 5B4
F7 FUSE 5B4
F6 FUSE 6B3
F9 FUSE 8D4
J6 CONN_BNC_5PIN 8D2
J5 CONN_BNC_5PIN 5B2
J4 CONN_BNC_5PIN 6B2
J3 CONN_BNC_5PIN 7B2
J2 CONN_BNC_5PIN 8B2
J1 CONN_10P 11B8
F16 FUSE 5C4
F15 FUSE 5D4
F14 FUSE 6C3
F13 FUSE 6D3
F12 FUSE 7C4
F11 FUSE 7D4
F10 FUSE 8C4
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