K7M403225B K7M403625B Preliminary K7M401825B 128Kx36 & 128Kx32 & 256Kx18 Flow-Through NtRAMTM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Flow Through NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. May. 15. 2001 Preliminary 0.1 1. Changed DC parameters Icc ; from 300mA to 250mA at -65, from 280mA to 230mA at -75, from 260mA to 210mA at -80, from 240mA to 190mA at -90, June. 12. 2001 Preliminary Aug. 11. 2001 Preliminary I SB ; from 140mA from 130mA from 120mA from 110mA 0.2 to to to to 130mA at -65, 120mA at -75, 110mA at -80, 100mA at -90, I SB1 ; from 100mA to 80mA 1. Add x32 org. and industrial temperature The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K7M401825B 128Kx36 & 128Kx32 & 256Kx18 Flow-Through NtRAMTM 4Mb NtRAM(Flow Through / Pipelined) Ordering Information Org. Part Number K7M401825B-QC(I)65/75/80 256Kx18 K7N401801B-QC(I)16/13 Mode VDD Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) FlowThrough 3.3 6.5/7.5/8.0 ns Pipelined 3.3 167/133 MHz K7N401809B-QC(I)25/22/20 Pipelined 3.3 250/225/200 MHz K7M403225B-QC(I)65/75/80 FlowThrough 3.3 6.5/7.5/8.0 ns Pipelined 3.3 167/133 MHz K7N403209B-QC(I)25/22/20 Pipelined 3.3 250/225/200 MHz K7M403625B-QC(I)65/75/80 FlowThrough 3.3 6.5/7.5/8.0 ns Pipelined 3.3 167/133 MHz Pipelined 3.3 250/225/200 MHz 128Kx32 K7N403201B-QC(I)16/13 128Kx36 K7N403601B-QC(I)16/13 K7N403609B-QC(I)25/22/20 -2- PKG Q :100TQFP Temp C (Commercial Temperature Range) I: (Industrial Temperature Range) Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K7M401825B 128Kx36 & 128Kx32 & 256Kx18 Flow-Through NtRAMTM 128Kx36 & 128Kx32 & 256Kx18-Bit Flow-Through NtRAMTM FEATURES GENERAL DESCRIPTION * V DD=3.3V+0.165V/-0.165V Power Supply. * V DDQ Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. * Byte Writable Function. * Enable clock and suspend operation. * Single READ/WRITE control pin. * Self-Timed Write Cycle. * Three Chip Enable for simple depth expansion with no data contention * A interleaved burst or a linear burst mode. * Asynchronous output enable control. * Power Down mode. * TTL-Level Three-State Outputs. * 100-TQFP-1420A Package. * Operating in commeical and industrial temperature range. The K7M403625B, K7M403225B and K7M401825B are 4,718,592-bit Synchronous Static SRAMs. The NtRAM TM , or No Turnaround Random Access Memory utilizes all bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incomming signals. For read cycles, Flow-Through SRAM allows output data to simply flow freely from the memory array. The K7M403625B, K7M403225B and K7M401825B are implemented with SAMSUNGs high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce. FAST ACCESS TIMES PARAMETER Symbol -65 -75 -80 Unit Cycle Time tCYC 7.5 8.5 10 ns Clock Access Time tCD 6.5 7.5 8.0 ns Output Enable Access Time tOE 3.5 3.5 4.0 ns LOGIC BLOCK DIAGRAM LBO A [0:16]or A [0:17] CKE ADDRESS REGISTER CO NTRO L LOG IC CLK A 0~A 1 ADV WE BWx A0~A1 128Kx36/32 , 256Kx18 MEMORY ARRAY A 2~ A16 or A 2~A 17 WRITE ADDRESS REGISTER K K C O N T RO L R E G IS TE R CS1 CS2 CS2 BURST ADDRESS COUNTER DATA-IN REGISTER CONTROL LOGIC (x=a,b,c,d or a,b) BUFFER OE ZZ 36 /32or 18 DQa0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd NtR A M TM and No Turnaround Random Access Memory are trademarks of Samsung, -3- Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K 7 M 4 0 1 8 2 5 B 1 2 8 K x 3 6 & 1 2 8 K x 3 2 & 2 5 6 K x 1 8 F l o w - T h r o u g h N tR A M T M VDD V SS CL K WE CK E OE AD V N.C . N.C . A8 A9 89 88 87 86 85 84 83 82 81 BW d 90 15 16 V DD V SS CS 2 V DD 91 13 14 BW a D Q c7 Vss 92 11 12 BW b V DDQ D Q c6 93 10 BW c V SSQ 94 8 9 95 D Q c4 D Q c5 CS 2 6 7 96 D Q c2 D Q c3 CS 1 5 97 V SSQ A7 3 4 98 D Q c1 V DDQ A6 1 2 99 DQPc/NC D Q c0 100 PIN CONFIGURATION(TOP VIEW) 100 Pin TQFP (20mm x 14mm) 17 DQd0 DQd1 18 19 V DDQ 20 21 V SSQ DQd2 K7M403625B(128Kx36) /K7M403225B(128Kx32) 80 DQPb/NC 79 78 DQb7 DQb6 77 V DDQ 76 75 V SSQ DQb5 74 73 DQb4 DQb3 72 DQb2 71 70 V SSQ V DDQ 69 68 DQb1 67 DQb0 V SS 66 65 V SS V DD 64 63 ZZ 62 DQa7 DQa6 61 60 V DDQ V SSQ 42 43 44 45 46 47 48 49 50 N .C . A 10 A 11 A 12 A 13 A 14 A 15 A 16 41 VDD N .C . 40 DQPa/NC V SS 51 39 30 N .C . DQPd/NC 38 DQa1 DQa0 N .C . 53 52 37 28 29 A0 DQd6 DQd7 36 V SSQ V DDQ A1 54 35 27 A2 V DDQ 34 DQa2 A3 56 55 33 25 26 A4 DQd5 V SSQ 32 DQa4 DQa3 31 DQa5 58 57 A5 59 23 24 LBO 22 DQd3 DQd4 PIN NAME SYMBOL A 0 - A 16 PIN NAME Address Inputs TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO. 32,33,34,35,36,37 V DD Power Supply(+3.3V) 15,16,41,65,91 44,45,46,47,48,49 V SS Ground 14,17,40,66,67,90 50,81,82,99,100 N.C. No Connect 38,39,42,43,83,84 Data Inputs/Outputs 52,53,56,57,58,59,62,63 ADV Address Advance/Load 85 WE Read/Write Control Input 88 D Q a 0~a7 CLK Clock 89 D Q b 0~b7 68,69,72,73,74,75,78,79 CKE Clock Enable 87 D Q c 0~ c 7 2,3,6,7,8,9,12,13 C S1 Chip Select 98 D Q d 0~d7 18,19,22,23,24,25,28,29 C S2 Chip Select 97 DQPa~P d 51,80,1,30 C S2 Chip Select 92 /NC BW x(x=a,b,c,d) Byte Write Inputs 93,94,95,96 V DDQ OE Output Enable 86 ZZ Power Sleep Mode 64 LBO Burst Mode Control 31 Notes : Output Power Supply 4,11,20,27,54,61,70,77 (2.5V or 3.3V) V SSQ Output Ground 5,10,21,26,55,60,71,76 1. The pin 83 is reserved for address bit for the 8Mb NtRAM. 2. A 0 a n d A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. 3. DQPa~Pd pins are NC for K7N403225B - 4 - Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K 7 M 4 0 1 8 2 5 B 1 2 8 K x 3 6 & 1 2 8 K x 3 2 & 2 5 6 K x 1 8 F l o w - T h r o u g h N tR A M T M VDD V SS CL K WE CK E OE AD V N.C . N.C . A8 A9 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP (20mm x 14mm) 17 DQb4 DQb3 18 19 V DDQ 20 21 V SSQ DQb2 CS 2 15 16 V DD V SS 91 V DD BW a 13 14 92 DQb5 V SS BW b 11 12 93 V DDQ DQb6 N .C. 10 94 V SSQ 95 8 9 N.C . DQb8 DQb7 CS 2 6 7 96 N.C. N.C. CS 1 5 97 V SSQ A7 3 4 98 N.C. V DDQ A6 1 2 99 N.C. N.C. 100 PIN CONFIGURATION(TOP VIEW) K7M401825B(256Kx18) 80 A 10 79 78 N.C. N.C. 77 V DDQ 76 75 V SSQ N.C. 74 73 DQa0 DQa1 72 DQa2 71 70 V SSQ V DDQ 69 68 DQa3 67 DQa4 V SS 66 65 V SS V DD 64 63 ZZ 62 DQa5 DQa6 61 60 V DDQ V SSQ 50 A 17 46 A 13 49 45 A 12 A 16 44 A 11 48 43 N .C . A 15 42 N .C . 47 41 VDD A 14 40 N.C. V SS 51 39 30 N .C . N.C. 38 N.C. N.C. N .C . 53 52 37 28 29 A0 N.C. N.C. 36 V SSQ V DDQ A1 54 35 27 A2 V DDQ 34 N.C. A3 56 55 33 25 26 A4 N.C. V SSQ 32 DQa8 N.C. 31 DQa7 58 57 A5 59 23 24 LBO 22 DQb1 DQb0 PIN NAME SYMBOL A 0 - A 17 PIN NAME Address Inputs TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO. 32,33,34,35,36,37,44 V DD Power Supply(+3.3V) 15,16,41,65,91 45,46,47,48,49,50,80 V SS Ground 14,17,40,66,67,90 81,82,99,100 N.C. No Connect 1,2,3,6,7,25,28,29,30,38,39, ADV Address Advance/Load 85 42,43,51,52,53,56,57,75,78, WE Read/Write Control Input 88 79,83,84,95,96 CLK Clock 89 CKE Clock Enable 87 D Q a 0~a8 C S1 Chip Select 98 D Q b 0~b8 C S2 Chip Select 97 C S2 Chip Select 92 BW x(x=a,b) Byte Write Inputs 93,94 OE Output Enable 86 ZZ Power Sleep Mode 64 LBO Burst Mode Control 31 Notes : V DDQ Data Inputs/Outputs 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24 Output Power Supply 4,11,20,27,54,61,70,77 (2.5V or 3.3V) V SSQ Output Ground 5,10,21,26,55,60,71,76 1. The pin 83 is reserved for address bit for the 8Mb NtRAM. 2. A 0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. - 5 - Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K 7 M 4 0 1 8 2 5 B 1 2 8 K x 3 6 & 1 2 8 K x 3 2 & 2 5 6 K x 1 8 F l o w - T h r o u g h N tR A M T M FUNCTION DESCRIPTION T h e K 7 M 4 0 3 6 / 3 2 2 5 B a n d K 7 M 4 0 1 8 2 5 B a r e Nt R A M TM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of O E , L B O and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable(C K E ) pin allows the operation of the chip to be suspended as long as necessary. When C K E is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtR A M TM l a t c h e s e x t e r n a l a d d r e s s a n d i n i t i a t e s a c y c l e , w h e n C K E , A D V a r e d r i v e n t o l o w a n d a l l t h r e e c h i p e n a b l e s (C S 1, C S 2, C S 2 ) are active . Output Enable(O E ) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the a d d r e s s r e g i s t e r , C K E i s d r i v e n l o w , a l l t h r e e c h i p e n a b l e s (C S 1 , C S2, C S 2) a r e a c t i v e , t h e w r i t e e n a b l e i n p u t s i g n a l s W E a r e d r i v e n high, and ADV driven low. Data appears at the outputs within the same clock cycle as the address for the data. Also during read operation O E must be driven low for the device to drive out the requested data. Write operation occurs when W E is driven low at the rising edge of the clock. B W [d:a] can be used for byte write operation. The Flow T h r o u g h N tR A M TM uses a late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, W E and address are registered, and the data associated with that address is required one cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the L B O pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time. BURST SEQUENCE TABLE L B O PIN ( I n t e r l e a v e d B u r s t , L B O= H i g h ) Case 1 HIGH First Address Fourth Address Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 0 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0 N o t e s : 1. L B O p i n m u s t b e t i e d t o H i g h o r L o w , a n d F l o a t i n g S t a t e m u s t n o t b e a l l o w e d . BQ TABLE LBO PIN (Linear Burst, LBO = L o w ) Case 1 LOW First Address Fourth Address Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 N o t e s : 1. L B O p i n m u s t b e t i e d t o H i g h o r L o w , a n d F l o a t i n g S t a t e m u s t n o t b e a l l o w e d . - 6 - Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K 7 M 4 0 1 8 2 5 B 1 2 8 K x 3 6 & 1 2 8 K x 3 2 & 2 5 6 K x 1 8 F l o w - T h r o u g h N tR A M T M S T A T E D I A G R A M F O R N tR A M TM WRITE READ READ BEGIN BEGIN READ WRITE DS RE AD W BURST E IT R E DS W R AD BURST BURST READ WRITE COMMAND DS TE T B UR DESELECT W RI ST DS DS BURST TE BU R S D R EA DS RI WRITE BURST ACTION DESELECT READ BEGIN READ WRITE BEGIN WRITE BEGIN READ BURST BEGIN WRITE CONTINUE DESELECT Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) - 7 - Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K 7 M 4 0 1 8 2 5 B 1 2 8 K x 3 6 & 1 2 8 K x 3 2 & 2 5 6 K x 1 8 F l o w - T h r o u g h N tR A M T M TRUTH TABLES SYNCHRONOUS TRUTH TABLE C S1 C S2 C S2 ADV WE BWx OE CKE CLK ADDRESS ACCESSED OPERATION H X X L X X X L N/A Not Selected X L X L X X X L N/A Not Selected X X H L X X X L N/A Not Selected X X X H X X X L N/A Not Selected Continue L H L L H X L L External Address Begin Burst Read Cycle X X X H X X L L Next Address Continue Burst Read Cycle L H L L H X H L External Address NOP/Dummy Read X X X H X X H L Next Address Dummy Read L H L L L L X L External Address Begin Burst Write Cycle X X X H X L X L Next Address Continue Burst Write Cycle L H L L L H X L N/A NOP/Write Abort X X X H X H X L Next Address Write Abort X X X X X X X H Current Address Ignore Clock N o t e s : 1 . X m e a n s " D o nt C a r e " . 2 . T h e r i s i n g e d g e o f c l o c k i s s y m b o l i z e d b y ( ). 3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. W R I T E = L m e a n s W r i t e o p e r a t i o n i n W R I T E T R U T H T A B L E . WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and O E ). W R I T E T R U T H T A B L E( x 3 6 / 3 2 ) WE BWa BWb BW c BW d OPERATION H X X X X READ L L H H H WRITE BYTE a L H L H H WRITE BYTE b L H H L H WRITE BYTE c L H H H L WRITE BYTE d L L L L L WRITE ALL BYTEs L H H H H WRITE ABORT/NOP N o t e s : 1 . X m e a n s " D o n t Care". 2 . A l l i n p u t s i n t h i s t a b l e m u s t m e e t s e t u p a n d h o l d t i m e a r o u n d t h e r i s i n g e d g e o f C L K ( ) . W R I T E T R U T H T A B L E( x 1 8 ) WE BWa BWb OPERATION H X X READ L L H WRITE BYTE a L H L WRITE BYTE b L L L WRITE ALL BYTEs L H H WRITE ABORT/NOP N o t e s : 1 . X m e a n s " D o nt C a r e " . 2 . A l l i n p u t s i n t h i s t a b l e m u s t m e e t s e t u p a n d h o l d t i m e a r o u n d t h e r i s i n g e d g e o f C L K ( ) . - 8 - Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K 7 M 4 0 1 8 2 5 B 1 2 8 K x 3 6 & 1 2 8 K x 3 2 & 2 5 6 K x 1 8 F l o w - T h r o u g h N tR A M T M ASYNCHRONOUS TRUTH TABLE OPERATION ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Notes 1 . X m e a n s " D o n t Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current Read depends on cycle time. ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT V DD -0.3 to 4.6 V V o l t a g e o n V D D S u p p l y R e l a t i v e t o V SS V o l t a g e o n V D D Q S u p p l y R e l a t i v e t o V SS V DDQ V DD V V o l t a g e o n I n p u t P i n R e l a t i v e t o V SS V IN - 0 . 3 t o V D D+ 0 . 3 V Voltage on I/O Pin Relative to VSS V IO - 0 . 3 t o V D D Q+ 0 . 3 V Power Dissipation PD 1.4 W T STG -65 to 150 C T OPR 0 to 70 C T OPR -40 to 85 C T BIAS -10 to 85 C Storage Temperature Commercial Operating Temperature Industrial Storage Temperature Range Under Bias *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. O P E R A T I N G C O N D I T I O N S a t 3 . 3 V I / O (0 C T A 7 0 C ) PARAMETER SYMBOL MIN Typ. MAX UNIT V DD 3.135 3.3 3.465 V V DDQ 3.135 3.3 3.465 V VSS 0 0 0 V Supply Voltage Ground O P E R A T I N G C O N D I T I O N S a t 2 . 5 V I / O (0 C T A 7 0 C ) PARAMETER SYMBOL MIN Typ. MAX UNIT V DD 3.135 3.3 3.465 V V DDQ 2.375 2.5 2.9 V VSS 0 0 0 V Supply Voltage Ground C A P A C I T A N C E *( T A = 2 5 C , f = 1 M H z ) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION MIN MAX UNIT C IN V I N= 0 V - 5 pF C OUT V OUT= 0 V - 7 pF *Note : Sampled not 100% tested. - 9 - Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K 7 M 4 0 1 8 2 5 B 1 2 8 K x 3 6 & 1 2 8 K x 3 2 & 2 5 6 K x 1 8 F l o w - T h r o u g h N tR A M T M D C E L E C T R I C A L C H A R A C T E R I S T I C S (V D D = 3 . 3 V + 0 . 1 6 5 V / - 0 . 1 6 5 V , T A = 0C t o + 7 0 C ) PARAMETER SYMBOL Input Leakage Current(except ZZ) I IL V D D = M a x ; V IN = V SS t o V DD Output Leakage Current I OL Output Disabled, Operating Current I CC I SB Standby Current TEST CONDITIONS MIN MAX UNIT -2 +2 A A -2 +2 V DD= M a x -65 - 250 IOUT= 0 m A -75 - 230 C y c l e T i m e t CYC M i n -80 - 210 D e v i c e d e s e l e c t e d , I OUT= 0 m A , -65 - 130 Z Z V IL , f = M a x , -75 - 120 A l l I n p u t s 0 . 2 V o r V DD - 0 . 2 V -80 - 110 - 80 mA - 50 mA 0.4 V mA NOTES 1,2 mA D e v i c e d e s e l e c t e d , I OUT = 0 m A , Z Z 0 . 2 V , f = 0 , ISB1 All Inputs=fixed (VDD-0.2V or 0.2V) D e v i c e d e s e l e c t e d , I O U T = 0 m A , Z Z V D D - 0 . 2 V , ISB2 f = M a x , A l l I n p u t s V IL o r V IH Output Low Voltage(3.3V I/O) V OL I OL = 8 . 0 m A - Output High Voltage(3.3V I/O) VOH IOH= - 4 . 0 m A 2.4 - V Output Low Voltage(2.5V I/O) V OL I OL = 1 . 0 m A - 0.4 V Output High Voltage(2.5V I/O) VOH IOH= - 1 . 0 m A Input Low Voltage(3.3V I/O) V IL Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O) 2.0 - V -0.3* 0.8 V VI H 2.0 V DD+0.3** V V IL -0.3* 0.7 V VI H 1.7 V DD+0.3** V 3 3 Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3 . I n C a s e o f I / O P i n s , t h e M a x . V IH = VD D Q + 0 . 3 V V IH V SS V S S -1 . 0 V 2 0 % tC Y C ( M I N ) TEST CONDITIONS (V DD=3.3V+0.165V/-0.165V ,V DDQ=3.3V+0.165V/-0.165V or V DD=3.3V+0.165V/-0.165V,V DDQ=2.5V+0.4V/-0.125V, T A =0to70C) PARAMETER VALUE Input Pulse Level(for 3.3V I/O) 0 to 3.0V Input Pulse Level(for 2.5V I/O) 0 to 2.5V Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) 1.0V/ns Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) 1.0V/ns Input and Output Timing Reference Levels for 3.3V I/O 1.5V Input and Output Timing Reference Levels for 2.5V I/O V DDQ /2 Output Load See Fig. 1 - 10 - Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K7M401825B 128Kx36 & 128Kx32 & 256Kx18 Flow-Through NtRAMTM Output Load(A) Output Load(B), (for tLZC, tLZOE , tHZOE & tHZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O RL=50 Dout Zo=50 30pF* VL=1.5V for 3.3V I/O V DDQ /2 for 2.5V I/O 319 / 1667 Dout 353 / 1538 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS (VDD=3.3V+0.165V/-0.165V, T A=0C to +70C) -65 PARAMETER Symbol Min -75 Max Min -80 Max Min Max UNIT Cycle Time tCYC 7.5 - 8.5 - 10 - ns Clock Access Time tCD - 6.5 - 7.5 - 8.0 ns Output Enable to Data Valid tOE - 3.5 - 3.5 - 4.0 ns Clock High to Output Low-Z tLZC 2.5 - 2.5 - 2.5 - ns Output Hold from Clock High tOH 2.5 - 2.5 - 2.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 3.5 - 3.5 - 4.0 ns Clock High to Output High-Z tHZC - 3.5 - 3.5 - 3.5 ns Clock High Pulse Width tCH 2.5 - 3.0 - 3.0 - ns Clock Low Pulse Width tCL 2.5 - 3.0 - 3.0 - ns Address Setup to Clock High tAS 1.5 - 2.0 - 2.0 - ns CKE Setup to Clock High tCES 1.5 - 2.0 - 2.0 - ns Data Setup to Clock High tDS 1.5 - 2.0 - 2.0 - ns Write Setup to Clock High (WE, BW X ) tWS 1.5 - 2.0 - 2.0 - ns Address Advance Setup to Clock High tADVS 1.5 - 2.0 - 2.0 - ns Chip Select Setup to Clock High tCSS 1.5 - 2.0 - 2.0 - ns Address Hold from Clock High tAH 0.5 - 0.5 - 0.5 - ns CKE Hold from Clock High tCEH 0.5 - 0.5 - 0.5 - ns Data Hold from Clock High tDH 0.5 - 0.5 - 0.5 - ns Write Hold from Clock High (WE , BWE X) tWH 0.5 - 0.5 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.5 - 0.5 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.5 - 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registerd into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 4. To avoid bus contention, At a given vlotage and temperature tLZC is more than tHZC. The soecs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions (0C,3.465V) than tH Z C, which is a Max. parameter(worst case at 70C,3.135V) It is not possible for two SRAMs on the same board to be at such different voltage and temperatue. - 11 - Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K7M401825B 128Kx36 & 128Kx32 & 256Kx18 Flow-Through NtRAMTM SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SB2 . The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, I SB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during t PUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE. SLEEP MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SLEEP MODE CONDITIONS SYMBOL ZZ V IH ISB2 MIN MAX 10 UNITS mA ZZ active to input ignored tPDS 2 cycle ZZ inactive to input sampled tPUS 2 cycle ZZ active to SLEEP current tZZI ZZ inactive to exit SLEEP current tRZZI 2 cycle 0 SLEEP MODE WAVEFORM K t PDS ZZ setup cycle tPUS ZZ recovery cycle ZZ t ZZI Isupply ISB2 tRZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z DON T CARE - 12 - Aug 2001 Rev 0.2 - 13 - Data Out OE ADV CS WRITE Address CKE Clock A1 tLZOE tOE tADVH tCSH tWH tAH Q 1-1 tHZOE A2 tCEH Q 2-1 tCD tOH Q2-2 Q 2-3 NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L tADVS tCSS tWS tAS tCES tCL tCYC tCH Q2-4 A3 TIMING WAVEFORM OF READ CYCLE Q 3-1 Q 3-2 Q3-3 Q3-4 tHZC Un defined Do n t Care K7M403225B K7M403625B Preliminary K7M401825B 128Kx36 & 128Kx32 & 256Kx18 Flow-Through NtRAMTM Aug 2001 Rev 0.2 - 14 - Data Out Data In OE ADV CS WRITE Address CKE Clock tHZOE D1-1 A2 tCYC D2-1 tCL D2-2 NOTES : WRITE = L means WE = L, a nd BWx = L CS = L me ans CS1 = L, CS2 = H a nd CS 2 = L CS = H mean s CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Q0-4 A1 tCES tCEH tCH D2-3 D2-4 A3 TIMING WAVEFORM OF WRTE CYCLE D3-1 tDS D3-2 tDH D3-3 D3-4 Undefined Dont Ca re K7M403225B K7M403625B Preliminary K7M401825B 128Kx36 & 128Kx32 & 256Kx18 Flow-Through NtRAMTM Aug 2001 Rev 0.2 - 15 - Data In Data Out OE ADV CS WRITE Address CKE Clock Q1 A2 tDS D2 A3 tDH Q3 A4 NOTES : WRITE = L means WE = L, a nd BWx = L CS = L me ans CS1 = L, CS2 = H a nd CS 2 = L CS = H mean s CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L tOE tLZOE A1 tCES tCEH Q4 A5 D5 A6 Q6 A7 TIMING WAVEFORM OF SINGLE READ/WRITE tCH Q7 tCYC tCL Undefined Dont Car e K7M403225B K7M403625B Preliminary K7M401825B 128Kx36 & 128Kx32 & 256Kx18 Flow-Through NtRAMTM Aug 2001 Rev 0.2 - 16 - Data In tCD tLZC A1 tCES tCEH Q1 A2 tHZC tDS D2 A3 tDH NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L Data Out OE ADV CS WRITE Address CKE Clock Q3 A4 TIMING WAVEFORM OF CKE OPERATION tCH Q4 tCYC tCL A5 Undefined Dont Care K7M403225B K7M403625B Preliminary K7M401825B 128Kx36 & 128Kx32 & 256Kx18 Flow-Through NtRAMTM Aug 2001 Rev 0.2 - 17 - Data In Data Out OE ADV CS WRITE Address CKE Clock tOE tLZOE A1 tCEH Q1 A2 Q2 tHZC A3 D3 tDS tDH NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L tCES tCD tLZC A4 Q4 TIMING WAVEFORM OF CS OPERATION A5 D5 tCH tCYC tCL Undefined Dont Care K7M403225B K7M403625B Preliminary K7M401825B 128Kx36 & 128Kx32 & 256Kx18 Flow-Through NtRAMTM Aug 2001 Rev 0.2 K7M403225B K7M403625B Preliminary K7M401825B 128Kx36 & 128Kx32 & 256Kx18 Flow-Through NtRAMTM PACKAGE DIMENSIONS 100-TQFP-1420A Units ; millimeters/Inches 22.00 0.30 20.00 0.20 0~8 0.127 +- 0.10 0.05 16.00 0.30 14.00 0.20 0.10 MAX (0.83) 0.50 #1 0.65 0.30 0.10 0.10 MAX 0.10 (0.58) 1.40 0.50 0.10 - 18 - 0.10 1.60 MAX 0.05 MIN Aug 2001 Rev 0.2