A8514-DS, Rev. 8
MCO-0000151
FEATURES AND BENEFITS
• AEC-Q100 qualified
• Wide input voltage range of 5 to 40 V for start/stop, cold
crank and load dump requirements
• Fully integrated LED current sinks and boost converter
with 60 V DMOS
• Sync function to synchronize boost converter switching
frequency up to 2.3 MHz, allowing operation above the
AM band
• Excellent input voltage transient response
• Single resistor primary OVP minimizes VOUT leakage
• Internal secondary OVP for redundant protection
• LED current of 80 mA per channel
• Drives up to 12 series LEDs in 4 parallel strings
• 0.7% to 0.8% LED to LED matching accuracy
• PWM and analog dimming inputs
• 5000:1 PWM dimming at 200 Hz
• Provides driver for external PMOS input disconnect switch
• Extensive protection against:
▫Shortedboostswitchorinductor
▫ShortedFSETorISETresistor
▫Shortedoutput
▫OpenorshortedLEDpin
▫OpenboostSchottky
▫Overtemperature(OTP)
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
PACKAGE:
Figure 1: Typical Application Circuit
Not to scale
A8514
Continued on the next page…
GATE SW
Q1
Optional D1
L1
CVDD
OVP
VOUT
ROVP COUT
RSC
RADJ
VSENSE
VIN
VDD
PWM/EN
APWM
ISET
FSET/SYNC
AGND PGND
COMP
CPRZ
CZ
LED4
LED1
LED2
LED3
FAULT
PAD
A8514
150 Ω
VC
10 µH 2 A / 60 V
137 kΩ
0.033 Ω
249 Ω
100 kΩ
RISET
8.25 kΩ RFSET
10 kΩ
4.7 µF
50 V
CIN
4.7 µF
50 V
CC
22 nF
RC
20 Ω
0.1 µF
0.47 µF
120 pF
VIN
8 to 16 V
DESCRIPTION
The A8514 is a multi-output white LED driver for small-size
LCD backlighting. It integrates a current-mode boost converter
with internal power switch and four current sinks. The boost
converter can drive up to 48 LEDs, 12 LEDs per string, at
80 mA. The LED sinks can be paralleled together to achieve
even higher LED currents, up to 320 mA. The A8514 can
operate with a single power supply, from 5 to 40 V, which
allows the part to withstand load dump conditions encountered
in automotive systems.
The A8514 can drive an external P-FET to disconnect the input
supply from the system in the event of a fault. The A8514
provides protection against output short and overvoltage,
open or shorted diode, open or shorted LED pin, shorted
boost switch or inductor, shorted FSET or ISET resistor, and
IC overtemperature. A dual level cycle-by-cycle current limit
function provides soft start and protects the internal current
switch against high current overloads.
The A8514 has a synchronization pin that allows PWM
switching frequencies to be synchronized in the range of
580 kHz to 2.3 MHz. The high switching frequency allows
the A8514 to operate above the AM radio band.
APPLICATIONS:
LCD backlighting or LED lighting for:
• Automotive infotainment
• Automotive cluster
• Automotive center stack
20-pin TSSOP with exposed thermal pad (suffix LP)
March 13, 2019
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ABSOLUTE MAXIMUM RATINGS [2]
Characteristic Symbol Notes Rating Unit
LEDx Pins –0.3 to 55 V
OVP Pin –0.3 to 60 V
VIN, VSENSE, GATE Pins VSENSE and GATE pins should not exceed VIN
by more than 0.4 V –0.3 to 40 V
SW Pin Continuous –0.6 to 62 V
t < 50 ns –1.0 V
¯
F
¯
¯
A
¯¯¯U ¯¯L
¯
¯
T
¯
Pin -0.3 to 40 V
ISET, FSET, APWM, COMP Pins –0.3 to 5.5 V
All Other Pins –0.3 to 7 V
Operating Ambient Temperature TARange K –40 to 125 °C
Maximum Junction Temperature TJ(max) 150 °C
Storage Temperature Tstg –55 to 150 °C
2 Stresses beyond those listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical
Characteristics table is not implied. Exposure to Absolute Maximum-rated conditions for extended periods may affect device reliability.
SELECTION GUIDE
Part Number Packing [1]
A8514KLPTR-T 4000 pieces per 13-in. reel
1 Contact Allegro™ for additional packing options
Table of Contents
Specifications 2
Thermal Characteristics 3
Pin-out Diagram and Terminal List 3
Characteristic Performance 8
Functional Description 11
Enabling the IC 11
Powering up: LED pin short-to-ground check 11
Soft start function 13
Frequency selection 13
Sync 14
LED current setting and LED dimming 16
PWM dimming 16
APWM pin 17
Analog dimming 19
LED short detect 19
Overvoltage protection 20
Boost switch overcurrent protection 22
Input overcurrent protection and disconnect switch 23
DESCRIPTION (CONTINUED)
TheA8514isprovidedina20-pinTSSOPpackage(suffixLP)with
anexposedpadforenhancedthermaldissipation.Itislead(Pb)free,
with 100% matte-tin leadframe plating.
Setting the current sense resistor 24
Input UVLO 24
VDD 24
Shutdown 24
Fault protection during operation 25
Application Information 27
Design Example for Boost Configuration 27
Design Example for SEPIC Configuration 31
Package Outline Drawing 35
Appendix A. Feedback Loop Calculations A-1
Power Stage Transfer Function A-1
Output to Control Transfer Function A-2
Stabilizing the Closed Loop System A-4
Measuring the Feedback Loop Gain and Phase Margin A-6
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Pinout Diagram
Terminal List Table
Number Name Function
1 GATE Output gate driver pin for external P-channel FET control.
2 VSENSE
Connect this pin to the negative sense side of the current sense resistor RSC. The threshold
voltage is measured as VIN – VSENSE . There is also a fixed current sink to allow for trip
threshold adjustment.
3 VIN Input power to the A8514 as well as the positive input used for current sense resistor.
4¯
F
¯
¯
A
¯¯¯U ¯¯L
¯
¯
T
¯
Indicates a fault condition. Connect a 100 kΩ resistor between this pin and the required logic
level voltage. The pin is an open drain type configuration that will be pulled low when a fault
occurs.
5 COMP Output of the error amplifier and compensation node. Connect a series RZ-CZ network from
this pin to ground for control loop compensation.
6 APWM Analog trimming option for dimming. Applying a digital PWM signal to this pin adjusts the
internal ISET current.
7 PWM/EN PWM dimming pin, used to control the LED intensity by using pulse width modulation. Also
used to enable the A8514.
8 FSET/SYNC
Frequency/synchronization pin. A resistor RFSET from this pin to ground sets the switching
frequency. This pin can also be used to synchronize two or more A8514s in the system. The
maximum synchronization frequency is 2.3 MHz.
9 ISET Connect the RISET resistor between this pin and ground to set the 100% LED current.
10 AGND LED signal ground.
11,12,13,14 LEDx Connect the cathodes of the LED strings to these pins.
15 VDD Output of internal LDO; connect a 0.1 µF decoupling capacitor between this pin and ground.
16,17.18 PGND Power ground for internal DMOS device.
19 OVP Overvoltage Condition (OVP) sense; connect the ROVP resistor from VOUT to this pin to
adjust the overvoltage protection.
20 SW The drain of the internal DMOS switch of the boost converter.
–PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be
connected to the ground plane(s) of the PCB with at least 8 vias, directly in the pad.
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions [1] Value Unit
Package Thermal Resistance RθJA
On 2-layer PCB, 3 in.
240.0 °C/W
On 4-layer PCB based on JEDEC standard
(estimated) 29.0 °C/W
1 Additional thermal information available on the Allegro website.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GATE
VSENSE
VIN
FAULT
COMP
APWM
PWM/EN
FSET/SYNC
ISET
AGND
SW
OVP
PGND
PGND
PGND
VDD
LED1
LED2
LED3
LED4
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Functional Block Diagram
VDD
Regulator
UVLO
Internal
Soft Start
Enable
PWM
Thermal
Shutdown
Open/Short
LED Detect
ISET
Fault
LED
Driver
1.235 V
Ref
Driver
Circuit
Internal VCC
Internal VCC
VREF
Internal VCC
VREF
VREF
ISS
ISS
IADJ
GOFF
100 kΩ
AGND
Current
Sense
Input Current
Sense Amplifier
PMOS
Driver
Diode
Open
Sense
OVP
Sense
Oscillator
SW
VIN
FSET/SYNC
COMP
VSENSE
GATE
PWM/EN
APWM
PAD
PGND AGND
ISET
OVP
LED4
LED1
LED2
LED3
FAULT
AGND
PGND
∑
+
–
+
–
+
–
+
–
+
–
Fault
Fault
Fault
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
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Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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ELECTRICAL CHARACTERISTICS [1][2]: Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by design and
characterization over the full operating temperature range with TA = TJ = –40°C to 125°C, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
INPUT VOLTAGE SPECIFICATIONS
Operating Input Voltage Range [3] VIN 5 – 40 V
UVLO Start Threshold VUVLOrise VIN rising −– 4.35 V
UVLO Stop Threshold VUVLOfall VIN falling −– 3.90 V
UVLO Hysteresis [2] VUVLOHYS 300 450 600 mV
INPUT CURRENTS
Input Quiescent Current IQPWM/EN = VIH ; SW = 2 MHz, no load −5.5 10 mA
Input Sleep Supply Current IQSLEEP VIN = 16 V, VPWMEN = VFSETSYNC = 0 V −2 10.0 μA
INPUT LOGIC LEVELS (PWM/EN AND APWM)
Input Logic Level-Low VIL VIN throughout operating input voltage range – – 400 mV
Input Logic Level-High VIH VIN throughout operating input voltage range 1.5 – – V
PWM/EN Pin Open Drain
Pull-Down Resistor RPWMEN PWM/EN = 5 V 60 100 140 kΩ
APWM Pull-Down Resistor RAPWM PWM/EN = VIH 60 100 140 kΩ
APWM
APWM Frequency [2] fAPWM VIH = 2 V, VIL = 0 V 20 −1000 kHz
ERROR AMPLIFIER
Open Loop Voltage Gain AVOL 44 48 52 dB
Transconductance gmΔICOMP = ±10 μA 750 990 1220 μA/V
Source Current IEA(SRC) VCOMP = 1.5 V −–350 − μA
Sink Current IEA(SINK) VCOMP = 1.5 V −350 − μA
COMP Pin Pull-Down Resistance RCOMP ¯
F
¯
¯
A
¯
U ¯¯L
¯
¯
T
¯
= 0 −2000 − Ω
OVERVOLTAGE PROTECTION
Overvoltage Threshold VOVP(th) OVP connected to VOUT 7.7 8.1 8.5 V
OVP Sense Current IOVPH 188 199 210 μA
OVP Leakage Current IOVPLKG ROVP = 40.2 kΩ, VIN = 16 V, PWM/EN = VIL −0.1 1 μA
Secondary Overvoltage Protection VOVP(sec) 53 55 58 V
BOOST SWITCH
Switch On-Resistance RSW ISW = 0.750 A, VIN = 16 V 75 300 600 mΩ
Switch Leakage Current ISWLKG VSW = 16 V, PWM/EN = VIL −0.1 1 µA
Switch Current Limit ISW(LIM) 3.0 3.5 4.2 A
Secondary Switch Current Limit [2] ISW(LIM2)
Higher than ISW(LIM)(max) for all conditions,
device latches when detected −7.00 −A
Soft Start Boost Current Limit ISWSS(LIM) Initial soft start current for boost switch −700 −mA
Minimum Switch On-Time tSWONTIME 60 85 111 ns
Minimum Switch Off-Time tSWOFFTIME 30 47 68 ns
Continued on the next page…
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
OSCILLATOR FREQUENCY
Oscillator Frequency fSW
RFSET = 10 kΩ 1.8 2 2.2 MHz
RFSET = 20 kΩ 0.9 1 1.1 MHz
RFSET = 35.6 kΩ 520 580 640 kHz
FSET/SYNC Pin Voltage VFSET RFSET = 10 kΩ − 1.00 −V
FSET Frequency Range fFSET 580 −2500 kHz
SYNCHRONIZATION
Synchronized PWM Frequency fSWSYNC 580 −2300 kHz
Synchronization Input
Minimum Off-Time tPWSYNCOFF 150 − − ns
Synchronization Input
Minimum On-Time tPWSYNCON 150 − − ns
SYNC Input Logic Voltage VSYNC(H) FSET/SYNC pin, high level 2.0 −– V
VSYNC(L) FSET/SYNC pin, low level – −0.4 V
LED CURRENT SINKS
LEDx Accuracy ErrLED ISET = 120 µA − − 3 %
LEDx Matching ΔLEDx ISET = 120 µA − − 3 %
LEDx Regulation Voltage VLED VLED1=VLED2=VLED3 =VLED4, ISET = 120 µA 600 700 800 mV
ISET to ILEDx Current Gain AISET ISET = 120 µA 633 653 672 A/A
ISET Pin Voltage VISET 0.988 1.003 1.018 V
Allowable ISET Current ISET 20 −120 µA
VLED Short Detect VLEDSC
While LED sinks are in regulation, sensed
from LEDx pin to ground 4.6 5.1 5.6 V
Soft Start LEDx Current ILEDSS
Current through each enabled LEDx pin
during soft start −2.0 – mA
Maximum PWM Dimming
Until Off-Time [2] tPWML
Measured while PWM/EN = low, during
dimming control and internal references
are powered-on (exceeding tPWML results in
shutdown)
−32,750 −fSW
cycles
Minimum PWM On-Time tPWMH First cycle when powering-up device −0.75 2 µs
PWM High to LED-On Delay tdPWM(on)
Time between PWM enable and LED current
reaching 90% of maximum −0.5 1 µs
PWM Low to LED-Off Delay tdPWM(off)
Time between PWM enable going low and
LED current reaching 10% of maximum −360 500 ns
ELECTRICAL CHARACTERISTICS [1][2] (continued): Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by
design and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Continued on the next page…
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ELECTRICAL CHARACTERISTICS [1][2] (continued): Valid at VIN = 16 V, TA = 25°C, indicates specifications guaranteed by
design and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
GATE PIN
GATE Pin Sink Current IGSINK VGS = VIN − −104 − µA
Gate Fault Shutdown Greater than
2× Current [2] tGFAULT2 − − 3 µs
Gate Fault Shutdown Greater than
1–2× Current tGFAULT1 −10,000 −fSW
cycles
Gate Voltage VGS
Gate to source voltage measured when gate
is on −–6.7 −V
VSENSE Pin
VSENSE Pin Sink Current IADJ 18.8 20.3 21.8 µA
VSENSE Trip Point VSENSEtrip1
Measured between VIN and VSENSE,
RADJ = 0 Ω 94 104 114 mV
VSENSE 2× Trip [2] VSENSEtrip2
2× VSENSEtrip , instantaneous shutdown,
RADJ = 0 Ω −180 −mV
¯
F
¯
¯
A
¯
¯
U ¯¯L
¯
¯
T
¯
PIN
¯
F
¯
¯
A
¯
U ¯¯L
¯
¯
T
¯
Pull-Down Voltage VFAULT IFAULT = 1 mA − − 0.5 V
¯
F
¯
¯
A
¯
U ¯¯L
¯
¯
T
¯
Pin Leakage Current IFAULTLKG VFAULT = 5 V − − 1 µA
THERMAL PROTECTION (TSD)
Thermal Shutdown Threshold [2] TSD Temperature rising −165 −°C
Thermal Shutdown Hysteresis [2] TSDHYS −20 −°C
1 For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing); positive current is defined as
going into the node or pin (sinking).
2 Ensured by design and characterization, not production tested.
3 Minimum VIN = 5 V is only required at startup. After startup is completed, the IC is able to function down to VIN = 4 V.
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
7.7
7.6
7.8
7.9
8.0
8.1
8.2
8.3
8.4
VOVP(th) (V)
190
192
194
196
198
200
202
204
206
208
210
IOVPH (µA)
3.60
3.61
3.62
3.63
3.64
3.65
3.66
3.67
3.68
3.69
3.70
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
f
SW
(MHz)
Switching Frequency
OVP Pin Sense Current OVP Pin Overvoltage Threshold
4.00
4.05
4.10
4.15
4.20
4.25
4.30
4.35
4.40
V
UVLOrise
(V)V
UVLOfall
(V)
0
1
2
3
4
5
6
7
8
9
10
IQSLEEP (µA)
VIN Input Sleep Mode Current
versus Ambient Temperature
VIN UVLO Start Threshold Voltage
VIN UVLO Stop Threshold Voltage
versus Ambient Temperature
versus Ambient Temperature versus Ambient Temperature
versus Ambient Temperature versus Ambient Temperature
Temperature (°C)
Temperature (°C)
Temperature (°C)
Temperature (°C)
Temperature (°C)
Temperature (°C)
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
CHARACTERISTIC PERFORMANCE
TA = TJ
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
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Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
20.0
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
IADJ (µA)
VSENSE Pin Sink Current
-6.9
-6.8
-6.7
-6.6
-6.5
-6.4
-6.3
V
GS
(V)
Input Disconnect Switch
Voltage
Gate to Source
Temperature (°C) Temperature (°C)
versus Ambient Temperature versus Ambient Temperature
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
-50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 110 120 1300
3
2
1
0
-1
-2
-3
ΔLEDx (%)
LED to LED Matching Accuracy
670
665
660
655
650
645
640
A
ISET
(A/A)
I
SET
to LED Current Gain
versus Ambient Temperature
83
82
81
80
79
78
77
76
75
ILED (mA)
Temperature (°C) Temperature (°C)
ISET = 120 µA
Temperature (°C)
LED Current
versus Ambient Temperature
versus Ambient Temperature
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
10
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
100
95
90
85
80
75
100
95
90
85
80
75
Efficiency (%) Efficiency (%)
InputVoltage, VIN (V)
Efficiency for Various 4-String Configuraons
ILED = 70 mA, LED Vf ≈ 3.2 V
Efficiency for Various 4-String Configuraons
ILED = 80 mA, LED Vf ≈ 3.2 V
InputVoltage, VIN (V)
5 7 9 11 13 15 17
5 7 9 11 13 15 17
6 series LEDs each string
7 series LEDs each string
8 series LEDs each string
6 series LEDs each string
7 series LEDs each string
8 series LEDs each string
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
11
Allegro MicroSystems, LLC
955 Perimeter Road
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www.allegromicro.com
The A8514 incorporates a current-mode boost controller with
internal DMOS switch, and four LED current sinks. It can be
used to drive four LED strings of up to 12 white LEDs in series,
with current up to 80 mA per string. For optimal efficiency,
the output of the boost stage is adaptively adjusted to the mini-
mum voltage required to power all of the LED strings. This is
expressed by the following equation:
VOUT=max(VLED1 ,..., VLED4)+VREG (1)
where
VLEDx is the voltage drop across LED strings 1 through 4, and
VREGistheregulationvoltageoftheLEDcurrentsinks(typi-
cally0.7VatthemaximumLEDcurrent).
Enabling the IC
The IC turns on when a logic high signal is applied on the
PWM/EN pin with a minimum duration of tPWMH for the first
clock cycle, and the input voltage present on the VIN pin is
greaterthanthe4.35VnecessarytocleartheUVLO(VUVLOrise)
threshold. The power-up sequence is shown in Figure 2. Before
the LEDs are enabled, the A8514 driver goes through a system
check to determine if there are any possible fault conditions that
might prevent the system from functioning correctly. Also, if the
FSET/SYNC pin is pulled low, the IC will not power-up. More
information on the FSET/SYNC pin can be found in the Sync
section of this datasheet.
Powering up: LED pin short-to-ground check
The VIN pin has a UVLO function that prevents the A8514
from powering-up until the UVLO threshold is reached. After
the VIN pin goes above UVLO, and a high signal is present on
the PWM/EN pin, the IC proceeds to power-up. As shown in
Figure 3, at this point the A8514 enables the disconnect switch
and checks if any LEDx pins are shorted to ground and/or are not
used.
The LED detect phase starts when the GATE voltage of the
disconnect switch is equal to VIN – 4.5 V. After the voltage
threshold on the LEDx pins exceeds 120 mV, a delay of between
3000 and 4000 clock cycles is used to determine the status of the
pins. Thus, the LED detection duration varies with the switching
frequency, as shown in the following table:
Switching Frequency
(MHz)
Detection Time
(ms)
2 1.5 to 2
1 3 to 4
0.800 3.75 to 5
0.600 5 to 6.7
The LED pin detection voltage thresholds are as follows:
LED Pin Voltage LED Pin Status Action
<70 mV Short-to-ground Power-up is halted
150 mV Not used LED removed from operation
325 mV LED pin in use None
FUNCTIONAL DESCRIPTION
Figure 3: Power-up diagram; shows VDD (ch1, 2 V/div.), FSET/SYNC (ch2,
1 V/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 2 V/div.) pins,
time = 200 µs/div.
t
VDD
PWM/EN
FSET/SYNC
ISET
C1
C3
C4
C2
Figure 2: Power-up diagram; shows the relationship of an LEDx pin with
respect to the gate voltage of the disconnect switch (if used) during the
LED detect phase, as well as the duration of the LED detect phase for a
switching frequency of 2 MHz; shows GATE (ch1, 5 V/div.), LED (ch2,
500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins,
time = 500 µs/div.
t
GATE
GATE = VIN – 4.5 V
LED detection period
PWM/EN
LEDx
ISET
C1
C3
C4
C2
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
12
Allegro MicroSystems, LLC
955 Perimeter Road
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Figure 4A: An LED detect occurring when both LED pins are selected to
be used; shows LED1 (ch1, 500 mV/div.), LED2 (ch2, 500 mV/div.), ISET
(ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins, time = 500 µs/div.
Figure 4B: Example with LED2 pin not being used; the detect voltage is
about 150 mV; shows LED1 (ch1, 500 mV/div.), LED2 (ch2, 500 mV/div.),
ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins, time = 500 µs/div.
Figure 4C: Example with one LED shorted to ground. The IC will not proceed
with power-up until the shorted LED pin is released, at which point the LED is
checked to see if it is being used; shows LED1 (ch1, 500 mV/div.), LED2 (ch2,
500 mV/div.), ISET (ch3, 1 V/div.), and PWM/EN (ch4, 5 V/div.) pins,
time = 1 ms/div.
t
LED detection period
PWM/EN
LED2
LED1
ISET
C1
C3
C4
C2
t
Pin shorted
Short removed
PWM/EN
LED2
LED1
ISET
C1
C3
C4
C2
t
LED detection period
PWM/EN
LED2
LED1
ISET
C1
C3
C4
C2
Wide Input Voltage Range, High Efficiency
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A8514
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Allunusedpinsshouldbeconnectedwitha2.37kΩresistorto
ground, as shown in Figure 5. The unused pin, with the pull-down
resistor, will be taken out of regulation at this point and will not
contribute to the boost regulation loop.
If a LEDx pin is shorted to ground the A8514 will not proceed
with soft start until the short is removed from the LEDx pin. This
prevents the A8514 from powering-up and putting an uncon-
trolled amount of current through the LEDs.
Soft start function
DuringsoftstarttheLEDxpinsaresettosink(ILEDSS)andthe
boost switch current is reduced to the ISWSS(LIM) level to limit
the inrush current generated by charging the output capacitors.
When the converter senses that there is enough voltage on the
LEDx pins the converter proceeds to increase the LED current to
the preset regulation current and the boost switch current limit is
switched to the ISW(LIM) level to allow the A8514 to deliver the
necessary output power to the LEDs. This is shown in Figure 6.
Frequency selection
The switching frequency on the boost regulator is set by the resis-
tor connected to the FSET/SYNC pin. The switching frequency
can be can be anywhere from 580 kHz to 2.3 MHz. Figure 7
shows the typical switching frequencies for various resistor
values, with the relationship between RFSET and typical switching
frequency given as:
fSW=k/(RFSET+RINT
),or (2)
RFSET = k / fSW – RINT
where RFSETisininkΩ,fSW is in megahertz, k = 20.9 and RINT
(internalresistanceofFSETpin)=0.6kΩ.
Figure 5: Channel select setup: (left) using only LED1, LED2, and LED3,
and (right) using all four channels.
2.37 kΩ
LED1
LED2
LED3
LED4
GND
A8514
LED1
LED2
LED3
LED4
GND
A8514
10 12 14 16 18 20 22 24 26 28 30 32 34 36
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
Switching Frequency, fSW (MHz)
Resistance for RFSET (kΩ)
Figure 6: Startup diagram showing the input current, output voltage, and
output current; shows IOUT (ch1, 200 mA/div.), IIN (ch2, 1 A/div.), VOUT
(ch3, 20 V/div.), and PWM/EN (ch4, 5 V/div.), time = 1 ms/div.
Figure 7: Typical Switching Frequency versus value of RFSET resistor
t
Inrush current caused by
enabling the disconnect
switch (when used) Operation during
ISWSS(lim)
Normal operation
ISW(lim)
PWM/EN
IIN
IOUT
VOUT
C1
C3
C4
C2
In case during operation a fault occurs that will increase the
switching frequency, the FSET/SYNC pin is clamped to a
maximum switching frequency of no more than 3.5 MHz. If the
FSET/SYNC pin is shorted to GND the part will shut down. For
more details see the Fault Mode table later in this datasheet.
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SYNC
The A8514 can also be synchronized using an external clock
on the FSET/SYNC pin. Figure 8 shows the correspondence
of a sync signal and the FSET/SYNC pin, and Figure 9 shows
the result when a sync signal is detected: the LED current does
not show any variation while the frequency changeover occurs.
At power-up if the FSET/SYNC pin is held low, the IC will not
power-up. Only when the FSET/SYNC pin is tri-stated to allow
the pin to rise, to about 1 V, or when a synchronization clock is
detected, will the A8514 try to power-up.
The basic requirement of the sync signal is 150 ns minimum on-
time and 150 ns minimum off time, as indicated by the specifica-
tions for tPWSYNCON and tPWSYNCOFF
. Figure 10 shows the timing
for a synchronization clock into the A8514 at 2.2 MHz. Thus any
pulse with a duty cycle of 33% to 66% at 2.2 MHz can be used to
synchronize the IC.
The SYNC pulse duty cycle ranges for selected switching fre-
quencies are:
SYNC Pulse Frequency
(MHz)
Duty Cycle Range
(%)
2.2 33 to 66
2 30 to 70
1 15 to 85
0.800 12 to 88
0.600 9 to 91
If during operation a sync clock is lost, the IC will revert to the
preset switching frequency that is set by the resistor RFSET. Dur-
ing this period the IC will stop switching for a maximum period
of about 7 µs to allow the sync detection circuitry to switch over
to the externally preset switching frequency.
If the clock is held low for more than 7 µs, the A8514 will shut
t
SW node
2 MHz operation 1 MHz operation
FSET/SYNC
IOUT
VOUT
C1
C3
C4
C2
t
SW node
FSET/SYNC
IOUT
VOUT
C1
C3
C4
C2
Figure 8: Diagram showing a synchronized FSET/SYNC pin and switch
node; shows VOUT (ch1, 20 V/div.), IOUT (ch2, 200 mA/div.), FSET/SYNC
(ch3, 2 V/div.), and SW node (ch4, 20 V/div.), time = 2 µs/div.
Figure 9: Transition of the SW waveform when the SYNC pulse is detect-
ed. The A8514 switching at 2 MHz, applied SYNC pulse at 1 MHz; shows
VOUT (ch1, 20 V/div.), IOUT (ch2, 200 mA/div.), FSET/SYNC (ch3, 2 V/div.),
and SW node (ch4, 20 V/div.), time = 5 µs/div.
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
A8514
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down. In this shutdown mode the IC will stop switching, the
input disconnect switch is open, and the LEDs will stop sinking
current. To shutdown the IC into low power mode, the user must
disable the IC using the PWM pin, by keeping the pin low for a
period of 32,750 clock cycles. If the FSET/SYNC pin is released
at any time after 7 µs, the A8514 will proceed to soft start.
To prevent generating a fault when the external SYNC signal is
stuck at low, the circuit shown in Figure 11 can be used. When
the external SYNC signal goes low, the A8514 will continue to
operate normally at the switching frequency set by RFSET. No
FAULT flag is generated.
If it is necessary to switch over between internal oscillator and
external sync during operation, ensure the transition takes place
at least 500 ns after the previous PWM = H rising edge. Alterna-
tively, execute the switchover during PWM = L only. This restric-
tion does not apply if PWM dimming is not being used.
150 ns
150 ns
T = 454 ns
154 ns
t PWSYNCON
t PWSYNCOFF
A8514
Schottky
Barrier
Diode
FSET
RFSET
10.2 kΩ
220 pF
External
Synchronization
Signal
Figure 10: SYNC pulse on and o󰀨 time requirements.
Figure 11: Countermeasure to prevent external sync signal stuck-at-low
fault.
Figure 12: Avoid switching over between Internal Oscillator and External
Sync in highlighted region
PWM
Ext_Sync
/ FSET
Internal
Clock
1 V
Internal oscillator External Sync
500 ns
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LED current setting and LED dimming
The maximum LED current can be up to 80 mA per channel,
and is set through the ISET pin. To set the ILED current, connect
a resistor, RISET, between this pin and ground, according to the
following formula:
RISET=(1.003×653)/ILED (3)
where ILED is in A and RISETisinΩ.Thissetsthemaximumcur-
rent through the LEDs, referred to as the 100% current. Standard
RISET values, at gain equals 653, are as follows:
Standard Closest RISET
Resistor Value
(kΩ)
LED current per LED, ILED
(mA)
8.25 80
10.2 65
16.5 40
22.1 30
PWM dimming
The LED current can be reduced from the 100% current level
by PWM dimming using the PWM/EN pin. When the PWM/EN
pin is pulled high, the A8514 turns on and all enabled LEDs sink
100% current. When PWM/EN is pulled low, the boost converter
andLEDsinksareturnedoff.Thecompensation(COMP)pinis
floated, and critical internal circuits are kept active. The typi-
cal PWM dimming frequencies fall between 200 Hz and 1 kHz.
Figure 13A to Figure 13D provide examples of PWM switching
behavior.
Figure 13A: Typical PWM diagram showing VOUT, ILED, and COMP pin as
well as the PWM signal. PWM dimming frequency is 500 Hz at 50% duty
cycle; shows VOUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3,
5 V/div.), and ILED (ch4, 50 mA/div.), time = 500 µs/div.
Figure 13B: Typical PWM diagram showing VOUT, ILED, and COMP pin as
well as the PWM signal. PWM dimming frequency is 500 Hz at 1% duty
cycle ; shows VOUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3,
5 V/div.), and ILED (ch4, 50 mA/div.), time = 500 µs/div.
Figure 13C: Delay from rising edge of PWM signal to LED current; shows
PWM (ch1, 2 V/div.), and ILED (ch2, 50 mA/div.), time = 200 ns/div.
Figure 12D. Delay from falling edge of PWM signal to LED current turn off;
shows PWM (ch1, 2 V/div.), and ILED (ch2, 50 mA/div.), time = 200 ns/div.
t
ILED
PWM
C1
C2
t
ILED
PWM
COMP
VOUT
C1
C3
C4
C2
t
ILED
PWM
COMP
VOUT
C1
C3
C4
C2
t
ILED
PWM
C1
C2
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Another important feature of the A8514 is the PWM signal to
LED current delay. This delay is typically less than 500 ns, which
allows greater accuracy at low PWM dimming duty cycles, as
shown in Figure 14.
APWM pin
TheAPWMpinisusedinconjunctionwiththeISETpin(see
Figure 15. This is a digital signal pin that internally adjusts
the ISET current. When this pin is not used it should be tied to
ground.
The typical input signal frequency is between 20 kHz and 1 MHz.
The duty cycle of this signal is inversely proportional to the per-
centageofcurrentthatisdeliveredtotheLEDs(Figure 16).
To use this pin for a trim function, the user should set the maxi-
mum output current to a value higher than the required current by
at least 5%. The LED ISET current is then trimmed down to the
appropriate value. Another consideration that also is important
is the limitation of the user APWM signal duty cycle. In some
cases it might be preferable to set the maximum ISET current to be
25% to 50% higher, thus allowing the APWM signal to have duty
cycles that are between 25% and 50%.
APWM
Current
Adjust
ISET
Current
Mirror
LED
Driver
ISET
RISET
PWM
A8514
0
10
20
30
40
50
60
70
80
0 20 40 60 80 100
IOUT (mA)
APWM Duty Cycle (%)
IOUT = 80 mA
IOUT = 65 mA
APWM Duty Cycle (%)
0
2
4
6
8
10
12
0 20 40 60 80 100
%ErrLED
IOUT = 80 mA
IOUT = 65 mA
Figure 14: Percentage Error of the LED current versus PWM duty cycle
(at 200 Hz PWM frequency).
10
8
6
4
2
0
ErrLED (%)
PWM Duty Cycle, D (%)
0.1 1 10 100
Worst-case
Typical
Figure 15: Output current versus duty cycle; 200 kHz APWM signal.
Figure 16: Simplied block diagram of the APWM and ISET circuit.
Figure 17: Percentage Error of the LED current versus PWM duty cycle;
200 kHz APWM signal.
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Figure 18: Diagram showing the transition of LED current from 60 mA
to 80 mA, when a 25% duty cycle signal is removed from the APWM pin.
PWM = 1; shows ILED (ch1, 50 mA/div.), APWM (ch2, 10 V/div.), and
PWM/EN (ch3, 5 V/div.), time = 500 µs/div.
t
ILED
APWM
PWM/EN
C1
C3
C2
As an example, a system that delivers a full LED current of
80 mA per LED would deliver 60 mA of current per LED when
anAPWMsignalisappliedwithadutycycleof25%(Figure
18 and Figure 19).
Although the order in which APWM and the PWM signal are
enabled does not matter, when enabling the A8514 into low cur-
rent output while PWM and APWM dimming, the APWM signal
should be enable before or at the same time as the PWM signal.
This sequence will prevent the light output intensity from chang-
ing during power up of the IC.
Figure 20 shows the sequencing of the APWM and PWM signal
during power-up to prevent inadvertent light intensity changes.
The full intensity light output with no APWM or PWM dimming
is 80 mA per channel.
t
IOUT
APWM
PWM/EN
C1
C3
C2
t
ILED
APWM
PWM/EN
VOUT
C1
C4
C3
C2
t
ILED
APWM
PWM/EN
C1
C3
C2
Figure 19: Diagram showing power-up sequencing LED current of 5 mA
per channel with a 10% duty cycle PWM signal and a 95% duty cycle
APWM signal; shows APWM (ch1, 5 V/div.), ILED (ch2, 50 mA/div.),
PWM/EN (ch3, 5 V/div.), and VOUT (ch4, 10 V/div.), time = 500 µs/div.
Figure 20: Diagram showing the transition of LED current from 80 mA
to 60 mA, when a 25% duty cycle signal is applied to the APWM pin;
PWM = 1; shows ILED (ch1, 50 mA/div.), APWM (ch2, 10 V/div.), and
PWM/EN (ch3, 5 V/div.), time = 500 µs/div.
Figure 21: Transition of output current level when a 50% duty cycle signal
is applied to the APWM pin, in conjunction with a 50% duty cycle PWM
dimming being applied to the PWM pin; shows IOUT (ch1, 50 mA/div.),
APWM (ch2, 10 V/div.), and PWM/EN (ch3, 5 V/div.), time = 500 µs/div.
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Although the APWM dimming function has a wide frequency
range, if this function is used strictly as an analog dimming
function it is recommended to use frequency ranges between
50 and 500 kHz for best accuracy. The frequency range must be
considered only if the user is not using this function as a closed
loop trim function. Another limitation is that the propagation
delay between this APWM signal and IOUT takes several milli-
seconds to change the actual LED current. This effect is shown in
Figure 18, Figure 19, and Figure 21.
Analog dimming
The A8514 can also be dimmed by using an external DAC or
another voltage source applied either directly to the ground side
of the RISET resistor or through an external resistor to the ISET
pin(seeFigure 20).Thelimitofthistypeofdimmingdepends
on the range of the ISET pin. In the case of the A8514 the limit is
20 to 125 µA.
•Forasingleresistor(panelAofFigure 22),theISETcurrentis
controlled by the following formula:
ISET =
VISET – VDAC
R
ISET
(4)
where VISET is the ISET pin voltage and VDAC is the DAC output
voltage.
When the DAC voltage is 0 V the LED current will be at its
maximum. To keep the internal gain amplifier stable, the user
should not decrease the current through the RISET resistor to less
than 20 µA
•Foradual-resistorconfiguration(panelBofFigure 22),theISET
current is controlled by the following formula:
ISET =–
V
ISET
R
ISET
VDAC – VISET
R
1
(5)
The advantage of this circuit is that the DAC voltage can be
higher or lower, thus adjusting the LED current to a higher or
lower value of the preset LED current set by the RISET resistor:
▫VDAC = 1.003 V; the output is strictly controlled by RISET
▫VDAC > 1.003 V; the LED current is reduced
▫VDAC < 1.003 V; the LED current is increased
LED short detect
Both LEDx pins are capable of handling the maximum VOUT
that the converter can deliver, thus providing protection from the
LEDx pin to VOUT in the event of a connector short.
An LEDx pin that has a voltage exceeding VLEDSC will be
removedfromoperation(seeFigure 23).ThisistopreventtheIC
from dissipating too much power by having a large voltage pres-
ent on an LEDx pin.
Figure 22: Simplied diagrams of voltage control of ILED: typical applica-
tions using a DAC to control ILED using a single resistor (upper), and dual
resistors (lower).
Figure 23: Example of the disabling of an LED string when the LED pin
voltage is increased above 4.6 V; shows IOUT (ch1, 200 mA/div.), LED1
(ch2, 5 V/div.), and PWM/EN (ch3, 5 V/div.), time = 10 µs/div.
t
IOUT
LED1
PWM/EN
C1
C3
C2
GND
DAC
VDAC
GND
A8514
ISET
GND
DAC
VDAC
GND
A8514
ISET
R
ISET
R1
R
ISET
(A)
(B)
Wide Input Voltage Range, High Efficiency
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t
VOUT
PWM
SW node
Output disconnect
event detected
IOUT
C1
C3
C4
C2
While the IC is being PWM-dimmed, the IC rechecks the dis-
abled LED every time the PWM signal goes high, to prevent false
tripping of an LED short event. This also allows some self-cor-
rection if an intermittent LED pin short to VOUT is present.
Overvoltage protection
TheA8514hasovervoltageprotection(OVP)andopenSchottky
diode(D1inFigure 1)protection.TheOVPprotectionhasa
default level of 8.1 V and can be increased up to 53 V by con-
necting resistor ROVP between the OVP pin and VOUT
. When
thecurrentintotheOVPpinexceeds199μA(typical),theOVP
comparator goes low and the boost stops switching.
The following equation can be used to determine the resistance
for setting the OVP level:
ROVP=(VOUTovp – VOVP(th)
)/IOVPH (6)
where:
VOUTovp is the target overvoltage level,
ROVPisthevalueoftheexternalresistor,inΩ,
VOVP(th) is the pin OVP trip point found in the Electrical Charac-
teristics table, and
IOVPH is the current into the OVP pin.
There are several possibilities for why an OVP condition would
be encountered during operation, the two most common being: a
disconnected output, and an open LED string. Examples of these
are provided in Figure 24 and Figure 25.
Figure 24 illustrates when the output of the A8514 is discon-
nected from load during normal operation. The output voltage
instantly increases up to OVP voltage level and then the boost
stops switching to prevent damage to the IC. If the output is
drained off, eventually the boost might start switching for a short
duration until the OVP threshold is hit again.
Figure 25 displays a typical OVP event caused by an open LED
string. After the OVP condition is detected, the boost stops
Figure 24: OVP protection in an output disconnect event; shows VOUT
(ch1, 10 V/div.), SW node (ch2, 50 V/div.), PWM (ch3, 5 V/div.), and
IOUT (ch4, 200 mA/div.), time = 1 ms/div.
Figure 25: OVP protection in an open LED string event; shows VOUT
(ch1, 10 V/div.), SW node (ch2, 50 V/div.), PWM (ch3, 5 V/div.), and
IOUT (ch4, 200 mA/div.), time = 500 µs/div.
t
VOUT
PWM
SW node
IOUT
C1
C3
C4
C2
LED string open
condition detected
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switching, and the open LED string is removed from operation.
Afterwards VOUT is allowed to fall, and eventually the boost will
resume switching and the A8514 will resume normal operation.
A8514 also has built-in secondary overvoltage protection to
protect the internal switch in the event of an open diode condi-
tion. Open Schottky diode detection is implemented by detecting
overvoltage on the SW pin of the device. If voltage on the SW
pin exceeds the device safe operating voltage rating, the A8514
disables and remains latched. To clear this fault, the IC must be
shut down either by using the PWM/EN signal or by going below
the UVLO threshold on the VIN pin. Figure 26 illustrates this.
Assoonastheswitchnodevoltage(SW)exceeds60V,theIC
shuts down. Due to small delays in the detection circuit, as well
as there being no load present, the switch node voltage will rise
above the trip point voltage.
Figure 27 illustrates when the A8514 is being enabled during an
open diode condition. The IC goes through all of its initial LED
detection and then tries to enable the boost, at which point the
open diode is detected.
Figure 26: OVP protection in an open Schottky diode event, while the IC is
in normal operation; shows PWM (ch1, 5 V/div.), SW node (ch2, 50 V/div.),
VOUT (ch3, 20 V/div.), and IOUT (ch4, 200 mA/div.), time = 1 µs/div.
Figure 27: OVP protection when the IC is enabled during an open diode
condition; shows PWM (ch1, 5 V/div.), SW node (ch2, 50 V/div.), VOUT
(ch3, 10 V/div.), and IOUT (ch4, 200 mA/div.), time = 500 µs/div.
t
VOUT
PWM
SW node
Open diode
condition detected
IOUT
C1
C3
C4
C2
t
VOUT
PWM
SW node
Open diode
condition detected
IOUT
C1
C3
C4
C2
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Figure 28: Normal operation of the switch node (SW); inductor current (IL)
and output voltage (VOUT) for 9 series LEDs in each of four strings con-
guration; shows SW node (ch1, 20 V/div.), inductor current IL (ch2, 1 A/
div.), VOUT (ch3, 10 V/div.), and PWM/EN (ch4, 5 V/div.),
time = 2 µs/div.
Figure 29: Cycle-by-cycle current limiting; inductor current (yellow trace, IL),
note reduction in output voltage as compared to normal operation with the
same conguration (Figure 27); shows SW node (ch1, 20 V/div.), inductor
current IL (ch2, 1 A/div.), VOUT (ch3, 10 V/div.), and PWM/EN (ch4, 5 V/div.),
time = 2 µs/div.
Figure 30: Secondary boost switch current limit; when this limit is hit, the
A8514 immediately shuts down; shows PWM (ch1, 5 V/div.), VOUT (ch2,
5 V/div.), SW node (ch3, 50 V/div.), and inductor current IL (ch4, 2 A/div.),
time = 100 ns/div.
t
VOUT
PWM/EN
SW node
IL
C1
C3
C4
C2
t
VOUT
PWM/EN
SW node
IL
C1
C3
C4
C2
t
IL
PWM/EN
SW node
C1
C3
C4
C2
FAULT
Boost switch overcurrent protection
The boost switch is protected with cycle-by-cycle current limiting
set at a minimum of 3.0 A. There is also a secondary current limit
that is sensed on the boost switch. When detected this current
limit immediately shuts down the A8514. The level of this cur-
rent limit is set above the cycle-by-cycle current limit to protect
the switch from destructive currents when the boost inductor is
shorted. Various boost switch overcurrent conditions are shown in
Figure 28, Figure 29, and Figure 30.
Wide Input Voltage Range, High Efficiency
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Input overcurrent protection and disconnect switch
The primary function of the input disconnect switch is to protect
the system and the device from catastrophic input currents during
a fault condition. The external circuit implementing the discon-
nect is shown in Figure 31. If the input disconnect switch is not
used, the VSENSE pin must be tied to VIN and the GATE pin
must be left open.
When selecting the external PMOS, check for the following
parameters:
• Drain-source breakdown voltage V(BR)DSS > –40 V
•Gatethresholdvoltage(makesureitisfullyconductingat
VGS=–4V,andcut-offat–1V)
• RDS(on): Make sure the on-resistance is rated at VGS = –4.5 V or
similar, not at –10 V; derate it for higher temperature
The input disconnect switch has two modes of operation:
• 1× mode When the input current is between one and two times
the preset current limit value, the disconnect switch enters a con-
stant-current mode for a maximum duration of 10,000 cycles or
5 ms at 2 MHz. During this time, the Fault flag is set immediately
and the disconnect switch goes into a linear mode of operation,
in which the input current will be limited to a value approximate
tothe1×currenttrippointlevel(Figure 32).Ifthefaultcorrects
itself before the expiration of the timer, the Fault flag will be
removed and normal operation will resume.
The user can also during this time decide whether to shut down
the A8514. To immediately shut down the device, pull the FSET/
SYNC pin low for more than 7 µs. After the FSET/SYNC pin has
been low for a period longer than 7 µs, the IC will stop switching,
the input disconnect switch will open, and the LEDx pins will
stop sinking current. The A8514 can be powered-down into low
power mode. To do so, disable the IC by keeping the PWM/EN
pin low for a period of 32,750 clock cycles. To keep the discon-
nectswitchstablewhilethedisconnectswitchisin1×mode,use
a 22 nF capacitor for CCanda20ΩresistorforRC.
Figure 31: Typical circuit (left) with the input disconnect feature implemented, and (right) without the input disconnect feature.
GATE
RADJ
RCCC
RSC
To L1
VSENSE
VIN
GATE
To L1
VSENSE
VIN
A8514 A8514
Q1
VIN VIN
Figure 32: Showing typical wave forms for a 3-A, 1X current limit under a
fault condition; shows fSW = 800 kHz, ¯
F
¯
¯
A
¯
U ¯¯L
¯
¯
T
¯
(ch1, 5 V/div.), IIN (ch2, 2 A/
div.), GATE (ch3, 5 V/div.), and PWM/EN (ch4, 5 V/div.), time = 5 ms/div.
t
GATE
PWM/EN
IIN
C1
C3
C4
C2
FAULT
(1) Initial fault
detected
(2) Disconnect switch
goes into a linear mode
(4) After 12.5 ms,
disconnect switch
shuts down
(3) IIN limited to 3 A
Figure 33: 2× mode, secondary overcurrent fault condition. IIN is the input
current through the switch. The Fault ag is set at the 1× current limit, and
when the 2× current limit is reached the A8514 disables the gate of the
disconnect switch (GATE); shows ¯
F
¯
¯
A
¯
U ¯¯L
¯
¯
T
¯
(ch1, 5 V/div.), GATE (ch2, 10 V/
div.), IIN (ch3, 2 A/div.), and PWM/EN (ch4, 5 V/div.), time = 5 µs/div.
t
GATE
PWM/EN
IIN
C1
C3
C4
C2
FAULT
Fault flag set at
1× trip point
A8514 shuts down at
2× trip point
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• 2× current limitIftheinputcurrentlevelgoesabove2×ofthe
preset current limit threshold, the A8514 will shut down in less
than3µsregardlessofuserinput(Figure 33).Thisisalatched
condition. The Fault flag is also set to indicate a fault. This
feature is meant to prevent catastrophic failure in the system due
to inductor short to ground, switch pin short to ground, or output
short to ground.
Setting the current sense resistor
The typical threshold for the current sense circuit is 104 mV,
when RADJis0Ω.ThisvoltagecanbetrimmedbytheRADJ
resistor. Thetypical1×trippointshouldbesetatabout3A,
which coincides with the cycle-by-cycle current limit minimum
threshold.
For example, given 3 A of input current, and the calculated maxi-
mum value of the sense resistor, RSC=0.033Ω.
The RSCchosenis0.03Ω,astandard.
Also:
RADJ=(VSENSETRIP – VADJ)/IADJ (7)
The trip point voltage is calculated as:
VADJ = 3.0 A × 0.03Ω=0.090V
RADJ=(0.104–0.09V)/(20.3µA)=731Ω
Input UVLO
When VIN and VSENSE rise above the VUVLOrise threshold, the
A8514 is enabled. A8514 is disabled when VIN falls below the
VUVLOfallthresholdformorethan50μs.Thissmalldelayisused
to avoid shutting down because of momentary glitches in the
input power supply. When VIN falls below 4.35 V, the IC will
shutdown(seeFigure 33).
VDD
The VDD pin provides regulated bias supply for internal circuits.
Connect the capacitor CVDDwithavalueof0.1μForgreaterto
this pin. The internal LDO can deliver no more than 2 mA of cur-
rent with a typical VDD of about 3.5 V, enabling this pin to serve
as the pull-up voltage for the ¯
F
¯
¯
A
¯
¯
U
¯
¯
L
¯
¯
T
¯
pin.
Shutdown
If the PWM/EN pin is pulled low for more than tPWML(32,750
clockcycles),thedeviceentersshutdownmodeandclearsall
Figure 34: Shutdown showing a falling input voltage (VIN); shows VIN
(ch1, 2 V/div.), IOUT (ch2, 200 mA/div.), VDD (ch3, 5 V/div.), and PWM/EN
(ch4, 2 V/div.), time = 5 ms/div.
Figure 35: Shutdown using the enable function, showing the 16 ms delay
between the PWM/EN signal and when the VDD and GATE of the discon-
nect switch turns o󰀨; shows GATE (ch1, 10 V/div.), IOUT (ch2, 200 mA/
div.), VDD (ch3, 5 V/div.), and PWM/EN (ch4, 2 V/div.), time = 5 ms/div.
t
IOUT
PWM/EN
VIN
VDD
C1
C2
C3
C4
t
IOUT
PWM/EN
GATE
VDD
C2
C1
C3
C4
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A8514
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internal fault registers. As an example, at a 2 MHz clock fre-
quency, it will take approximately 16.3 ms to shut down the IC
intothelowpowermode(Figure 35).WhentheA8514isshut
down, the IC will disable all current sources and wait until the
PWM/EN signal goes high to re-enable the IC. If faster shut
down is required, the FSET/SYNC pin can be used.
Fault protection during operation
The A8514 constantly monitors the state of the system to deter-
mine if any fault conditions occur during normal operation. The
response to a triggered fault condition is summarized in the Fault
Mode table.
The possible fault conditions that the device can detect are: Open
LED pin, LED pin shorted to ground, shorted inductor, VOUT
short to ground, SW pin shorted to ground, ISET pin shorted to
ground, and input disconnect switch source shorted to ground.
Note the following:
• Some of the protection features might not be active during
startup, to prevent false triggering of fault conditions.
• Some of these faults will not be protected if the input disconnect
switch is not being used. An example of this is VOUT short to
ground.
Fault Mode Table
Fault Name Type Active
Fault
Flag
Set
Description Boost Disconnect
switch
Sink
driver
Primary switch
overcurrent protection
(cycle-by-cycle
current limit)
Auto-restart Always No This fault condition is triggered by the cycle-by-
cycle current limit, ISW(LIM).
Off for
a single
cycle
On On
Secondary switch
current limit Latched Always Yes
When the current through the boost switch exceeds
secondary current SW limit (ISW(LIM2)) the device
immediately shuts down the disconnect switch,
LED drivers, and boost. The Fault flag is set. To re-
enable the device, the PWM/EN pin must be pulled
low for 32,750 clock cycles.
Off Off Off
Input disconnect
current limit Latched Always Yes
The device is immediately shut off if the voltage
across the input sense resistor is 2X the preset
current value. The Fault flag is set. If the input
current limit is between 1X and 2X, the Fault flag
is set but the IC will continue to operate normally
for tGFAULT1 or until it is shut down. To re-enable
the device the PWM/EN pin must be pulled low for
32,750 clock cycles.
Off Off Off
Secondary OVP Latched Always Yes
Secondary overvoltage protection is used for open
diode detection. When diode D1 opens, the SW pin
voltage will increase until VOVP(SEC) is reached. This
fault latches the IC. The input disconnect switch is
disabled as well as the LED drivers, and the Fault
flag is set. To re-enable the part the PWM pin must
be pulled low for 32,750 clock cycles.
Off Off Off
Continued on the next page…
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
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Fault Mode Table (continued)
Fault Name Type Active
Fault
Flag
Set
Description Boost Disconnect
Switch
Sink
driver
LED Pin Short
Protection Auto-restart Startup No
This fault prevents the device from starting-up if
either of the LEDx pins are shorted. The device
stops soft-start from starting while either of the
LEDx pins are determined to be shorted. After the
short is removed, soft-start is allowed to start.
Off On Off
LED Pin open Auto-restart Normal
Operation No
When an LEDx pin is open the device will determine
which LED pin is open by increasing the output
voltage until OVP is reached. Any LED string not
in regulation will be turned off. The device will then
go back to normal operation by reducing the output
voltage to the appropriate voltage level.
On On
Off for
open
pins.
On
for all
others.
ISET Short Protection Auto-restart Always No
This fault occurs when the ISET current goes above
150% of the maximum current. The boost will stop
switching, the disconnect switch will turn off, and
the IC will disable the LED sinks until the fault is
removed. When the fault is removed the IC will try
to to regulate to the preset LED current.
Off On Off
FSET/SYNC Short
Protection Auto-restart Always Yes
Fault occurs when the FSET/SYNC current goes
above 150% of maximum current, about 180 µA.
The boost will stop switching, the disconnect switch
will turn off, and the IC will disable the LED sinks
until the fault is removed. When the fault is removed
the IC will try to restart with soft-start.
Off Off Off
Overvoltage
Protection Auto-restart Always No
Fault occurs when OVP pin exceeds VOVP(th)
threshold. The A8514 will immediately stop
switching to try to reduce the output voltage. If the
output voltage decreases then the A8514 will restart
switching to regulate the output voltage.
Stop
during
OVP
event.
On On
LED Short Protection Auto-restart Always No
Fault occurs when the LED pin voltage exceeds
VLEDSC. When the LED short protection is detected
the LED string that is above the threshold will be
removed from operation.
On On
Off for
shorted
pins.
On
for all
others.
Overtemperature
Protection Auto-restart Always No Fault occurs when the die temperature exceeds the
overtemperature threshold, 165°C. Off Off Off
VIN UVLO Auto-restart Always No Fault occurs when VIN drops below VUVLO
, 3.90 V
maximum. This fault resets all latched faults. Off Off Off
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A8514
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Design Example for Boost Configuration
This section provides a method for selecting component values
when designing an application using the A8514. The resulting
design is diagrammed in Figure 36.
Assumptions: For the purposes of this example, the following are
given as the application requirements:
• VBAT: 10 to 14 V
• Quantity of LED channels, #CHANNELS : 4
• Quantity of series LEDs per channel, #SERIESLEDS : 10
• LED current per channel, ILED
: 60 mA
• Vf at 60 mA: 3.2 V
• fSW
: 2 MHz
• TA(max):65°C
• PWM dimming frequency: 200 Hz, 1% duty cycle
Procedure: The procedure consists of selecting the appropriate
configuration and then the individual component values, in an
ordered sequence.
Step 1: Connect LEDs to pins LED1 and LED2.
Step 2: Determining the LED current setting resistor RISET:
RISET =(VISET×AISET)/ILED (7)
=(1.003(V)×653)/60mA=10.92kΩ
Choosea11.00kΩresistor.
Step 3: Determining the OVP resistor. The OVP resistor is
connected between the OVP pin and the output voltage of the
converter.
Step 3a: The first step is determining the maximum voltage
based on the LED requirements. The regulation voltage, VLED ,
of the A8514 is 700 mV. A constant term, 2 V, is added to give
margin to the design due to noise and output voltage ripple.
VOUT(OVP) = #SERIESLEDS × Vf+VLED+2(V) (8)
= 10 ×3.2V+0.7V+2V
= 34.7 V
Then the OVP resistor is:
ROVP=(VOUT(OVP)– VOVP(th))/IOVPH (9)
=(34.7(V)–8.1(V))/199(µA)=133.67kΩ
where both IOVPH and VOVP(th) are taken from the Electrical
Characteristics table.
Chose a value of resistor that is higher value than the calculated
ROVP.Inthiscaseavalueof137kΩwasselected.Belowisthe
actual value of the minimum OVP trip level with the selected
resistor:
VOUT(OVP)=137(kΩ)×199(µA)+8.1(V)=35.36V
Step 3b: At this point a quick check must be done to see if the
conversion ratio is acceptable for the selected frequency.
Dmaxofboost = 1 – tSWOFFTIME × fSW (10)
=1–68(ns)×2.0(MHz)=86.4%
wheretheminimumoff-time(tSWOFFTIME)isfoundintheElectri-
cal Characteristics table.
The Theoretical Maximum VOUT is then calculated as:
VOUT(max) Vd
= –
1 – Dmaxofboost
V
IN
(min)
0.4 (V) 73.13 V
= =–
1 – 0.864
10 (V)
(11)
where Vd is the diode forward voltage.
The Theoretical Maximum VOUT value must be greater than the
value VOUT(OVP) . If this is not the case, the switching frequency
of the boost converter must be reduced to meet the maximum
duty cycle requirements.
Step 4: Selecting the inductor. The inductor must be chosen such
that it can handle the necessary input current. In most applica-
tions, due to stringent EMI requirements, the system must operate
in continuous conduction mode throughout the whole input volt-
age range.
APPLICATION INFORMATION
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Step 4a: Determining the duty cycle, calculated as follows:
D(max) Vd
=+
VIN(min)
VOUT(OVP)
72.04%
= =
1 –
1 –
10 (V)
(12)
Step 4b: Determining the maximum and minimum input current
to the system. The minimum input current will dictate the induc-
tor value. The maximum current rating will dictate the current
rating of the inductor. First, the maximum input current, given:
IOUT
=
#CHANNELS ILED
0.240 A
= =
4 0.060 (A)
(13)
then:
IIN(max) =
VIN(min)
VOUT(OVP) IOUT
η
0.94 A
= =
35.36 (V)
10 (V) 0.90
240 (mA)
(14)
whereηisefficiency.
Next, calculate minimum input current, as follows:
IIN(min) =
VIN(max)
V
OUT(OVP)
I
OUT
η
0.67 A
= =
35.36 (V)
14 (V) 0.90
240 (mA)
(15)
Agoodapproximationofefficiency,η,canbetakenfromthe
efficiency curves located in the datasheet. A value of 90% is a
good starting approximation.
Step 4c: Determining the inductor value. To ensure that the
inductor operates in continuous conduction mode, the value of
the inductor must be set such that the ½ inductor ripple current is
not greater than the average minimum input current. A first past
assumes Iripple to be 40% of the maximum inductor current:
ΔIL = IIN(max)× Iripple (16)
= 0.94 × 0.40 = 0.376 A
then:
L=
V
IN
(min)
D(max)
fSW
ΔIL
9.57 µH
0.376 (A)
==
0.72
10 (V)
2 (MHz)
(17)
Step 4d: Double-check to make sure the ½ current ripple is less
than IIN(min):
IIN(min)> 1/2ΔIL (18)
0.67 A > 0.19 A
A good inductor value to use would be 10 µH.
Step 4e: This step is used to verify that there is sufficient slope
compensation for the inductor chosen. The slope compensation
value is determined by the following formula:
2 10
6
Slope Compensation = =
f
SW
3.6
3.6 A /µs
(19)
Next insert the inductor value used in the design:
=
VIN(min)
D(max)
fSW
Lused
ΔILused
10 (µH) 0.36 A
= =
0.72
10 (V)
2.0 (MHz)
(20)
Calculate the minimum required slope:
=
(1 – D(max))
(1 – 0.72)
f
SW
Required Slope (min) ΔI
Lused
0.36 (A)
1
1
1
10
–6
1 10
–6
= = 2.57 A/µs
2.0 (MHz)
(21)
If the minimum required slope is greater than the calculated slope
compensation, the inductor value must be increased.
Note: The slope compensation value is in A/µs, and 1×10
–6 is a
constant multiplier.
Step 4f: Determining the inductor current rating. The inductor
current rating must be greater than the IIN(max)valueplusthe
ripplecurrentΔIL, calculated as follows:
L(min)=IIN(max)+1/2 ΔILused (22)
=0.94(A)+0.36(A)/2=1.12A
Step 5: Determining the resistor value for a particular switching
frequency. Use the RFSET values shown in Figure 7. For example,
a10kΩresistorwillresultina2MHzswitchingfrequency.
Step 6: Choosing the proper switching diode. The switching
diode must be chosen for three characteristics when it is used in
LED lighting circuitry. The most obvious two are: current rating
of the diode and reverse voltage rating.
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The reverse voltage rating should be such that during operation
condition, the voltage rating of the device is larger than the maxi-
mum output voltage. In this case it is VOUT(OVP).
The peak current through the diode is calculated as:
Idp = IIN(max)+1/2 ΔILused (23)
=0.94(A)+0.36(A)/2=1.12A
The third major component in deciding the switching diode is the
reverse current, IR , characteristic of the diode. This characteristic
is especially important when PWM dimming is implemented.
During PWM off-time the boost converter is not switching. This
results in a slow bleeding off of the output voltage, due to leakage
currents. IR can be a large contributor, especially at high tempera-
tures. On the diode that was selected in this design, the current
varies between 1 and 100 µA.
Step 7: Choosing the output capacitors. The output capacitors
must be chosen such that they can provide filtering for both the
boost converter and for the PWM dimming function. The biggest
factors that contribute to the size of the output capacitor are:
PWM dimming frequency and PWM duty cycle. Another major
contributor is leakage current, ILK
. This current is the combina-
tion of the OVP leakage current as well as the reverse current of
the switching diode. In this design the PWM dimming frequency
is 200 Hz and the minimum duty cycle is 1%. Typically, the volt-
age variation on the output, VCOUT , during PWM dimming must
be less than 250 mV, so that no audible hum can be heard. The
capacitance can be calculated as follows:
COUT =
fPWM(dimming)
1 – D(min)
1 – 0.01
200 Hz
ILK
200 µA 3.96 µF
= =
0.250 V
VCOUT
(24)
A capacitor larger than 3.96 µF should be selected due to degra-
dation of capacitance at high voltages on the capacitor. A ceramic
4.7 µF 50 V capacitor is a good choice to fulfill this requirement.
Corresponding capacitors include:
Vendor Value Part number
Murata 4.7 µF 50 V GRM32ER71H475KA88L
Murata 2.2 µF 50 V GRM31CR71H225KA88L
The rms current through the capacitor is given by:
ICOUTrms =
1 – D(max)
D(max) + ∆ILused
IOUT
0.240 (A) 0.39 A
× 12
= =
IIN(max)
1 – 0.72
0.72 + 0.36 (A)
0.94 (A)
× 12
(25)
The output capacitor must have a current rating of at least
390 mA. The capacitor selected in this design was a 4.7 µF 50 V
capacitor with a 3 A current rating.
Step 8: Selecting input capacitor. The input capacitor must be
selected such that it provides a good filtering of the input voltage
waveform. To reduce the switching frequency noise, a good rule
ofthumbistosettheinputvoltagehighfrequencyrippleΔVIN to
be 1% of the minimum input voltage. The minimum input capaci-
tor requirements are as follows:
CIN =
fSW
0.36 (A)
∆I
Lused
0.23 µF
8
= =
∆VIN
2 (MHz) 0.1 (V)
8
(26)
The rms current through the capacitor is given by:
CINrms = =
∆ILused /
12 0.104 A
(27)
A good ceramic input capacitor with ratings of 2.2 µF 50 V or
4.7 µF 50 V will suffice for this application. Corresponding
capacitors include:
Vendor Value Part number
Murata 4.7 µF 50 V GRM32ER71H475KA88L
Murata 2.2 µF 50 V GRM31CR71H225KA88L
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Selecting the electrolytic input capacitor according to dimming
transient
During a PWM dimming transient, unless an adequate input
capacitor is used, the input voltage drops significantly.
Theinputcapacitorripplecurrent,ΔI,duringthedimmingtran-
sient is the same as the input maximum DC current, and can be
calculated by:
∆I= =
VIN(min)
IINDC(max) η
IOUT
VOUT
(28)
where VIN(min)istheminimuminputvoltage,10V.
Considerthecasewhere:η=0.88,VIN(min)=10V,
VOUT = 33.1 V, IOUT = 0.24 A, then:
ΔI = IINDC(max)
=(33.1×0.24)/(10×0.88)=0.9A
Allowing VINtodropbyΔVIN = 0.5 V, and considering the feed-
back loop bandwidth, or cross over frequency, to be fC = 30 kHz,
theinputdropwilllastΔT,calculatedby:
ΔT = 1 / fC=33×10–6(second) (29)
The required electrolytic capacitor will be:
== ∆
VIN
CIN 59.4 µF
(
∆I ∆T ) 106
(30)
If this issue is important to the customer, it is recommended to
use a 50 V/ 68 µF, low ESR value electrolytic capacitor.
Step 9: Choosing the input disconnect switch components. Set
the input disconnect 1X current limit to 3 A by choosing a sense
resistor. The calculated maximum value of the sense resistor is:
RSC(max)=VSENSEtrip/3.0(A) (31)
=0.104(V)/3.0(A)=0.035Ω
The RSCchosenis0.033Ω,astandard.
The trip point voltage must be:
VADJ=3.0(A)×0.033(Ω)=0.099(V)
RADJ=(VSENSEtrip – VADJ)/IADJ(typ) (32)
RADJ=(0.104(V)–0.099(V))/20.3(µA)=246.31Ω
Avalueof249Ωwaschosenforthisdesign.
Step 10: See appendix A for a detailed description of how to
calculate RZ, CZ, and CP. Using L1 = 10 µH, COUT=(4.7µF+
2.2µF),andfC = 30 kHz, the calculation results for RZ
, CZ
, and
CP are: RZ=499Ω,CZ = 100 nF, and CP = 320 pF.
GATE SW
Q1
L1 D1
CVDD
OVP
VOUT
ROVP COUT1
RSC
RADJ
VSENSE
VIN
VDD
PWM/EN
APWM
ISET
FSET/SYNC
AGND PGND
COMP
CPRZ
CZ
FAULT
PAD
A8514
499 Ω
VC
10 µH 2 A / 60 V
137 kΩ
0.033 Ω
249 Ω
100 kΩ
RISET
11 kΩ RFSET
10 kΩ
4.7 µF
CIN
4.7 µF
CC
22 nF
RC
20 Ω
0.1 µF
100 nF
320 pF
VIN
10 to 14 V
LED4
LED1
10 LEDs each string
LED2
LED3
C
OUT2
2.2 µF
Figure 36: The schematic diagram showing calculated values from the design example above.
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Design Example for SEPIC Configuration
This section provides a method for selecting component values
whendesigninganapplicationusingtheA8514inSEPIC(Sin-
gle-EndedPrimary-InductorConverter)circuit.SEPICtopology
has the advantage that it can generate a positive output voltage
either higher or lower than the input voltage. The resulting design
is diagrammed in Figure 37.
Assumptions: For the purposes of this example, the following are
given as the application requirements:
• VBAT:6to14V(VIN(min):5VandVIN(max):16V)
• Quantity of LED channels, #CHANNELS : 4
• Quantity of series LEDs per channel, #SERIESLEDS : 4
• LED current per channel, ILED
: 60 mA
• LED Vfat60mA:≈3.3V
• fSW
: 2 MHz
• TA(max):65°C
• PWM dimming frequency: 200 Hz, 1% duty cycle
Procedure: The procedure consists of selecting the appropriate
configuration and then the individual component values, in an
ordered sequence.
Step 1: Connecting LEDs to LEDx pins. If only some of the LED
channels are needed, the unused LEDx pins should be pulled to
groundusinga1.5kΩresistor.
Step 2: Determining the LED current setting resistor RISET:
RISET =(VISET×AISET)/ILED (33)
=(1.003(V)×653)/0.60(A)=10.92kΩ
Choosean11.00kΩ1%resistor.
Step 3: Determining the OVP resistor. The OVP resistor is
connected between the OVP pin and the output voltage of the
converter.
Step 3a: The first step is determining the maximum voltage
based on the LED requirements. The regulation voltage, VLED ,
of the A8514 is 700 mV. A constant term, 2 V, is added to give
margin to the design due to noise and output voltage ripple.
VOUT(OVP) = #SERIESLEDS × Vf+VLED+2(V) (34)
= 4 ×3.3(V)+0.7(V)+2(V)=15.9V
Then the OVP resistor is:
ROVP=(VOUT(OVP)– VOVP(th))/IOVPH (35)
=(15.9(V)–8.1(V))/0.199(mA)=39.196kΩ
where both IOVPH and VOVP(th) are taken from the Electrical
Characteristics table.
Inthiscaseavalueof39.2kΩwasselected.Belowistheactual
value of the minimum OVP trip level with the selected resistor:
VOUT(OVP)=39.2(kΩ)×0.199(mA)+8.1(V)=15.9V
Step 3b: At this point a quick check must be done to determine if
the conversion ratio is acceptable for the selected frequency.
Dmax = 1 – tSWOFFTIME × fSW (36)
=1–68(ns)×2(MHz)=86.4%
wheretheminimumoff-time(tSWOFFTIME)isfoundintheElectri-
cal Characteristics table.
The Theoretical Maximum VOUT is then calculated as:
VOUT(max) =Vd
–
1 – Dmax
D
max
VIN(min)
0.4 (V) 30.3 V
= =–
1 – 0.86
0.86
5 (V)
(37)
where Vd is the diode forward voltage.
The Theoretical Maximum VOUT value must be greater than
the value VOUT(OVP) . If this is not the case, it may be necessary
to reduce the frequency to allow the boost to convert the volt-
age ratios.
Step 4: Selecting the inductor. The inductor must be chosen such
that it can handle the necessary input current. In most applica-
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tions, due to stringent EMI requirements, the system must operate
in continuous conduction mode throughout the whole input volt-
age range.
Step 4a: Determining the duty cycle, calculated as follows:
D(max) Vd
=+
Vd
+
VOUT(OVP)
+
VIN(min)
VOUT(OVP)
76.5%
= =
5 (V) + 15.9 (V) + 0.4 (V)
+ 0.4 (V)
15.9 (V)
(38)
Step 4b: Determining the maximum and minimum input current
to the system. The minimum input current will dictate the induc-
tor value. The maximum current rating will dictate the current
rating of the inductor. First, the maximum input current, given:
I
OUT
=
#CHANNELS ILED
0.240 A
= =
4 0.060 (A)
(39)
then:
IIN(max) =
VIN(min)
VOUT(OVP) IOUT
η
0.848 A
= =
15.9 (V)
5 (V) 0.90
0.24 (A)
(40)
whereηisefficiency.
Next, calculate minimum input current, as follows:
IIN(min) =
VIN(max)
VOUT(OVP)
I
OUT
η
0.265 A
= =
15.9 (V)
16 (V) 0.90
0.24 (A)
(41)
Step 4c: Determining the inductor value. To ensure that the
inductor operates in continuous conduction mode, the value of
the inductor must be set such that the ½ inductor ripple current
is not greater than the average minimum input current. As a first
pass assume Iripple to be 30% of the maximum inductor current:
ΔIL = IIN(max)× Iripple (42)
= 0.848 × 0.30 = 0.254 A
then:
L=
V
IN
(min)
D(max)
fSW
ΔIL
7.53 µH
0.254 (A)
==
0.765
5 (V)
2 (MHz)
(43)
Step 4d: Double-check to make sure the ½ current ripple is less
than IIN(min):
IIN(min)> 1/2ΔIL (44)
0.265 A > 0.127 A
A good inductor value to use would be 10 µH.
Step 4e: Next insert the inductor value used in the design to
determine the actual inductor ripple current:
=
VIN(min)
D
(max)
fSW
Lused
ΔILused
10 (µH) 0.191 A
= =
0.765
5 (V)
2.0 (MHz)
(45)
Step 4f: Determining the inductor current rating. The inductor
current rating must be greater than the IIN(max)valueplushalfof
theripplecurrentΔIL, calculated as follows:
L(min)=IIN(max)+1/2 ΔILused (46)
=0.848(A)+0.096(A)=0.944A
Step 5: Determining the resistor value for a particular switching
frequency. Use the RFSET values shown in Figure 7. For example,
a10kΩresistorwillresultina2MHzswitchingfrequency.
Step 6: Choosing the proper switching diode. The switching
diode must be chosen for three characteristics when it is used in
LED lighting circuitry. The most obvious two are: current rating
of the diode and reverse voltage rating.
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The reverse breakdown voltage rating for the output diode in a
SEPIC circuit should be:
VBD > VOUT(OVP)(max)+VIN(max) (47)
>15.9(V)+16(V)=31.9V
because the maximum output voltage in this case is VOUT(OVP).
The peak current through the diode is calculated as:
Idp = IIN(max)+1/2 ΔILused (48)
=0.848(A)+0.096(A)=0.944A
The third major component in deciding the switching diode is the
reverse current, IR , characteristic of the diode. This characteristic
is especially important when PWM dimming is implemented.
During PWM off-time the boost converter is not switching. This
results in a slow bleeding off of the output voltage, due to leakage
currents. IR can be a large contributor, especially at high tempera-
tures. On the diode that was selected in this design, the current
varies between 1 and 100 µA. It is often advantageous to pick a
diode with a much higher breakdown voltage, just to reduce the
reverse current. Therefore for this example, pick a diode rated for
a VBD of 60 V, instead of just 40 V.
Step 7: Choosing the output capacitors. The output capacitors
must be chosen such that they can provide filtering for both the
boost converter and for the PWM dimming function. The biggest
factors that contribute to the size of the output capacitor are:
PWM dimming frequency and PWM duty cycle. Another major
contributor is leakage current, ILK
. This current is the combina-
tion of the OVP leakage current as well as the reverse current of
the switching diode. In this design the PWM dimming frequency
is 200 Hz and the minimum duty cycle is 1%. Typically, the volt-
age variation on the output, VCOUT , during PWM dimming must
be less than 250 mV, so that no audible hum can be heard. The
capacitance can be calculated as follows:
COUT =
fPWM(dimming)
1 – D(min)
1 – 0.01
200 (Hz)
ILK
200 (µA) 3.96 µF
= =
0.250 (V)
VCOUT
(49)
A capacitor larger than 3.96 µF should be selected due to degra-
dation of capacitance at high voltages on the capacitor. Select a
4.7 µF capacitor for this application.
The rms current through the capacitor is given by:
ICOUTrms =
1 – D(max)
D(max)
IOUT
0.240 (A) 0.433 A
= =
1 – 0.765
0.765
(50)
The output capacitor must have a ripple current rating of at least
500 mA. The capacitor selected for this design is a 4.7 µF 50 V
capacitor with a 1.5 A current rating.
Step 8: Selecting input capacitor. The input capacitor must be
selected such that it provides a good filtering of the input voltage
waveform. A estimation rule is to set the input voltage ripple,
ΔVIN
, to be 1% of the minimum input voltage. The minimum
input capacitor requirements are as follows:
CIN =
fSW
0.191 (A)
∆ILused
0.24 µF
8
= =
∆VIN
2 (MHz) 0.05 (V)
8
(51)
The rms current through the capacitor is given by:
CINrms =
∆ILused
0.055 A
12
==
0.191 (A)
12
(52)
A good ceramic input capacitor with a rating of 2.2 µF 25 V will
suffice for this application.
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Step 9: Selecting coupling capacitor CSW. The minimum capaci-
tance of CSW is related to the maximum voltage ripple allowed
across it:
CSW =
fSW
0.24 (A) 0.765
IOUT DMAX
0.92 µF
= =
∆VSW
2 (MHz)0.1 (V)
(53)
The rms current requirement of the coupling capacitor is given
by:
ICSWrms =
1 – D(max)
D(max)
IIN(max)
0.848 (A) 0.47 A
= =
1 – 0.765
0.765
(54)
The voltage rating of the coupling capacitor must be greater than
VIN(max),or16Vinthiscase.Aceramiccapacitorratedfor
2.2 µF 25 V will suffice for this application.
Figure 37: Typical application showing SEPIC conguration, with accurate input current sense, and VSENSE
to ground protection.
GATE SW
Q1
2.2 µF
2.2 µF
4.7 µF
0.47 µF
120 pF
10 µH
10 µH
22 nF
0.1 µF
100 kΩ
10 kΩ
150 Ω
11 kΩ
20 Ω
39.2 kΩ
249 Ω
0.033 Ω
L1
2 A / 60 V
D1
CVDD
OVP
VOUT
COUT
RSC
RADJ
VSENSE
VIN
VDD
PWM/EN
APWM
ISET
FSET/SYNC
AGND PGND
COMP
CPRZ
CZ
FAULT
LED4
LED1
LED2
LED3
PAD
A8514
VC
RISET RFSET
CIN CC
RC
VIN
9 to 16 V
CSW
L2
ROVP
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Package LP, 20-Pin TSSOP with Exposed Thermal Pad
A
1.20 MAX
0.15
0.00
0.30
0.19
0.20
0.09
8º
0º
0.60 ±0.15
1.00 REF
C
SEATING
PLANE
C0.10
20X
0.65 BSC
0.25 BSC
21
20
6.50±0.10
4.40±0.103.00 3.00
4.12
4.12
6.40±0.20
GAUGE PLANE
SEATING PLANE
ATerminal #1 mark area
For Reference Only; not for tooling use (reference MO-153 ACT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
B
0.45
1.70
20
21
PCB Layout Reference View
B
6.10
0.65
CExposed thermal pad (bottom surface); dimensions may vary with device
Reference land pattern layout (reference IPC7351
SOP65P640X110-21M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
C
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Fault Tolerant LED Driver
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Allegro MicroSystems, LLC
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For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Number Date Description
5 May 20, 2013 Update application information, add appendix A
6 October 1, 2015 Added Figure 11, and renumbered subsequent figures
7 March 1, 2017 Corrected SYNC Input Logic Voltage values on page 6
8 March 13, 2019 Updated Sync section (page 15)
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