ALVD
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WITH VOLTAGE CONTROL
STANDARD SPECIFICATIONS:
APPLICATIONS:
• SONET, xDSL
• SDH, CPE
• STB
FEATURES:
• Based on a proprietary digital multiplier
• Tri-State Output
• Low Phase Jitter
• 3.3V +/- 5% operation
• Ceramic SMD, low profile package
7.0 x 5.0 x 1.8m m
Pb
RoHS
Compliant
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
30332
Esperanza, Rancho Santa Margarita, California
92688
tel 949-546-8000 |fax 949-546-8001 | www.abracon.com
Revised: 12.02.10
Visit www.abracon.com for Terms & Conditions of Sale
P
ABRACON P/N: ALVD Series
Frequency range: 750 KHz to 800 MHz
Operating temperature: 0°C to +70°C (see options)
Storage temperature: -55°C to +125°C
Overall frequency stability: ±50 ppm max. (see options)
Supply voltage (V dd ): 3.3V ± 10%
Voltage control (V C): 0.3VDC min, 1.65VDC typ, 3.0 VDC max.
Symmetry at 1/2 Vdd: 40/60% max.
Output Level: See options (PECL, CMOS, or LVDS)
Pullability: ± 50ppm (see option)
Tristate Function: "1" (V IH >= 0.7* Vdd) or open: Oscillation
"0" (V IL < 0.3* Vdd) : Hi Z
Aging per year: ±5 ppm max.
RMS Phase Jitter: 3ps typical, 5ps max. (12KHz~20MHz)
Period Jitter (peak to peak): 35 ps typical
Phase Noise: -112 dBc/Hz @ 1kHz Offset from 155.52MHz
-125 dBc/Hz @ 10kHz Offset from 155.52MHz
-123 dBc/Hz @ 100KHz Offset from 155.52MHz
-109 dBc/Hz @ 1kHz Offset from 622.08MHz
-110 dBc/Hz @ 10kHz Offset from 622.08MHz
-109 dBc/Hz @ 100KHz Offset from 622.08MHz
PECL:
Supply current (IDD):25mA max (for Fo<24MHz),65mA max (for 24MHz<Fo<96MHz),100mA max (96MHz<Fo<800MHz)
Output Logic High: Vdd -1.025V min, V
dd -0.880V max.
Output Logic Low: Vdd -1.810V min. Vdd -1.620V max.
Symmetry (Duty Cycle): 45% min, 50% typ, 55% max,
Rise time: 0.6nSec typ,1.5nS max
Fall time: 0.6nSec typ, 1.5nS max
CMOS:
Supply current (I DD):15 mA max (for Fo<24MHz),30mA max (for 24MHz<Fo<96MHz), 40mA max (96MHz<Fo<800MHz)
Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]: 1.2ns typ, 1.6ns max.
Output Clock Duty Cycle [Measured @ 50% VDD]: 45% min, 50% typical, 55% max
LVDS:
ARAMETERS
CERTIFIED
ABRACON IS
CERTIFIED
ABRACON IS
ISO9001:2008
CERTIFIED
Ω
Supply current (IDD):25 mA max (for Fo<24MHz),45mA max (for 24MHz<Fo<96MHz),80mA max (96MHz<Fo<800MHz)
Output Clock Duty Cycle @ 1.25V: 45% min, 50% typical, 55% max
Output Differential Voltage (VOD): 247mV min, 355mV typical, 454mV max
VDD Magnitude Change
∆
OD): -50mV min, 50mV max
Output High Voltage :
OH = 1.4V typical, 1.6V max.
Output Low Voltage:
OL = 0.9V min, 1.1V typical
Offset Voltage [R L = 100 Ω]: VOS = 1.125V min, 1.2V typical, 1.375V max
Offset Magnitude Change [
L = 100 Ω]:∆
OS = 0mV min, 3mV typical, 25mV max
Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V] = ±1
typical, ±10 µ
max.
Differential Clock Rise Time (tr) [RL=100 Ω, CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS,max
Differential Clock Fall Time (tf) [RL=100 Ω, CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS max