MCS9845CV-BA - ASIX Electronics Corporation

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MCS9845

PCI to Dual Serial and ISA Controller

Revision 2.01

Sep. 12th, 2012

MCS9845

PCI to Dual Serial and ISA Controller

Datasheet

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MCS9845

PCI to Dual Serial and ISA Controller

IMPORTANT NOTICE

DISCLAIMER

No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,

including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may

make changes to the product specifications and descriptions in this document at any time, without notice.

ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without

limitation warranties of merchantability, fitness for a particular purpose, and non-infringement.

Designers must not rely on the absence or characteristics of any features or registers marked “reserved”, “undefined”

or “NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or

incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before

starting a design of ASIX products.

TRADEMARKS

ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the

property of their respective owners.

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MCS9845

PCI to Dual Serial and ISA Controller

Table of Contents

1. General Description ................................................................................................................... 4

2. Features ...................................................................................................................................... 4

3. Applications ................................................................................................................................ 5

4. Ordering Information ................................................................................................................ 5

5. Application Schematic ............................................................................................................... 5

6. Evaluation Board ....................................................................................................................... 5

7. Software Support ........................................................................................................................ 6

8. Certifications .............................................................................................................................. 6

9. Block Diagram ........................................................................................................................... 7

10. Pin Diagram ............................................................................................................................. 8

11. Pin Descriptions ....................................................................................................................... 9

12. Architectural overview ........................................................................................................... 16

12.1 PCI Core ........................................................................................................................................ 16

12.2 UART Core .................................................................................................................................... 20

12.3 ISA Bridge ..................................................................................................................................... 21

12.4. External EEPROM ...................................................................................................................... 22

13. Extended Modes through EEPROM ..................................................................................... 23

14. EEPROM Contents ................................................................................................................ 24

15. Electrical Specifications ........................................................................................................ 27

16. Mechanical Specifications – QFP 128 .................................................................................. 29

Revision History ........................................................................................................................... 30

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MCS9845

PCI to Dual Serial and ISA Controller

1. General Description

The MCS9845CV-BA is a PCI based single function I/O Adapter. It has two 16C450/16C550

compatible UART channels and ISA style interface to add external UARTS and Parallel Ports.

The MCS9845CV-BA has 32-Byte transmit and receive FIFO for each UART channel.

MCS8935CV-BA performs serial-to-parallel conversions on data received from a Serial device,

and parallel-to-serial conversions on data received from its CPU.

ISA Style interface is designed to add additional Serial / Parallel Ports by using external ISA

peripherals. ISA interface can be used for Serial / Parallel port expansion through ISA : 4 Serial

or 2 Serial + 1 Parallel.

The MCS9845CV-BA is ideally suited for PC applications, such as Add-On COM ports and

Parallel Ports. It is available in 128-Pin QFP package & fabricated using an advanced

submicron CMOS process to achieve low power drain and high-speed requirements.

MCS9845CV-BA is designed to be pin compatible with previous version of MCS9845CV.

Existing designs of MCS9845 can be migrated to MCS9845CV-BA without any modification to

system design. Software compatibility is also maintained between MCS9845, MCS9845CV-BA.

2. Features

General

 5V Operation

 Low Power

 Fully compliant with PCI Local Bus Specification 2.3

 Re-map function for Legacy Ports

 Microsoft WHQL Complaint Drivers

 128 Pin QFP package, RoHS

 Commercial Grade, 0 to 70 deg C

 Advanced testability through scan addition

Serial Port

 Two 16C 450 / 550 compatible UARTs

 Supports RS232, RS485 & RS422 modes

 Bi-directional Speeds from 50 bps to 115200 bps / Port

 Full Serial modem control

 Supports Hardware Flow Control

 5, 6, 7, 8-bit Serial format support

 Even, Odd, None, Space & Mark parity supported

 On Chip 32 Byte FIFO’s in Transmit, Receive paths for both Serial Ports

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MCS9845

PCI to Dual Serial and ISA Controller

ISA Interface Bus

 ISA style I/O interface for extending UARTs & Parallel Ports

 8 bit data bus @ 8Mhz

 3 Address Lines

 4 Active-High Interrupts

 1 Active Low Interrupt

 4 External Chip Selects

Miscellaneous

 Four -Wire SPI Interface for EEPROM

 EEPROM read through PCI

3. Applications

 Generic Serial attached devices like Modem & Serial Mouse

 Serial Networking / Monitoring Equipment

 Data Acquisition System

 POS Terminal & Industrial PC

 Parallel / Printer Port based applications

 Add-On I/O Cards – Serial / Parallel

 Embedded systems – For I/O expansion

 Industrial Control

4. Ordering Information

 Part Number : MCS9845CV-BA

 128 Pin QFP

 ROHS

 Commercial Grade, 0 to 70 deg C

5. Application Schematic

 PCI to 2S + ISA(2S + 1 Parallel)

 PCI to 2S + ISA(4S)

 PCI to 2S + ISA (2P)

6. Evaluation Board

 MCS98XXCV-BA EVB – Combo

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MCS9845

PCI to Dual Serial and ISA Controller

7. Software Support

SW Driver Support

 Windows 95/98SE/ME

 Windows 32bit - 2000 /XP /NT /2003 Server

 Windows 64bit XP / 2003 Server

 Windows Vista / 2008 Server (32 & 64 bit)

 Windows 7 (32 & 64 bit)

 Linux Kernel 2.4.X / 2.6.X

 DOS-6.22

SW Utility Support

 Windows XP based Diagnostic Utility

 DOS based diagnostic Utility

8. Certifications

 WHQL Certification of device drivers for Windows XP, Windows Vista & Windows 7

Operating Systems.

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MCS9845

PCI to Dual Serial and ISA Controller

9. Block Diagram

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MCS9845

PCI to Dual Serial and ISA Controller

10. Pin Diagram

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MCS9845

PCI to Dual Serial and ISA Controller

11. Pin Descriptions

This section provides information on each Pin of MCS9845CV-BA

Name

Pin #

Direction

Drive

Strength

Description

CLK

122

I

33 MHz PCI System Clock input.

nRESET

121

I(PU)

PCI system Reset (active low).Resets

all internal registers, sequencers, and

signals to a consistent state. During

reset condition, AD[31-0] and nSERR

are tri-stated.

AD[31-29]

126-128

I/O

8mA

Multiplexed PCI Address/Data bus.

During the address phase, AD[31-0]

contain a physical address. Data is

stable and valid when nIRDY and

nTRDY are asserted (active).

AD[28-24]

2-6

I/O

8mA

See AD[31-29] description.

AD[23-16]

11-18

I/O

8mA

See AD[31-29] description.

AD[15-11]

34-38

I/O

8mA

See AD[31-29] description.

AD[10-8]

40-42

I/O

8mA

See AD[31-29] description.

AD[7-0]

46-53

I/O

8mA

See AD[31-29] description.

nFRAME

23

I

nFRAME is asserted by the current

Bus Master to indicate the beginning

of an transfer. nFRAME remains active

until the last Byte of the transfer is

to be processed.

nIRDY

24

I

Initiator Ready.

During a write, nIRDY asserted indicates

that the initiator is driving valid data onto

the data bus. During a read, nIRDY

asserted indicates that the initiator is

ready to accept data from the target

device.

nTRDY

25

O

8mA

Target Ready (three-state). Asserted

when the target is ready to complete

the current data phase.

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MCS9845

PCI to Dual Serial and ISA Controller

Name

Pin #

Direction

Drive

Strength

Description

nSTOP

27

O

8mA

Asserted to indicate that the target

wishes the initiator to stop the

transaction in progress on the current

data phase.

nLOCK

28

I

Indicates an atomic operation that may

require multiple transactions to

complete.

IDSEL

9

I

Initialization Device Select. Used as a

chip select during configuration read

and write transactions.

nDEVSEL

26

O

8mA

Device Select (three-state). Asserted

when the target has decoded one of its

addresses.

nPERR

29

I/O

8mA

Parity Error (three-state).

Used to report parity errors during all

PCI transactions except a special cycle.

The minimum duration of nPERR is one

clock cycle.

nSERR

30

O

8mA

System Error (open drain). This pin

goes low when address parity errors

are detected.

PAR

31

I/O

8mA

Parity.

Even Parity is applied across AD[31-

0] and nC/BE[3-0]. PAR is stable and

valid one clock after the address

phase. For the data phase, PAR is

stable and valid one clock after either

nIRDY is asserted on a write

transaction, or nTRDY is asserted on

a read transaction.

nC/BE3

8

I

Bus Command and Byte Enable. During

the address phase of a transaction,

nC/BE[3-0] defines the bus command.

During the data phase, nC/BE[3-0] are

used as Byte Enables. nC/BE3 applies

to Byte “3”.

nC/BE2

22

I

Bus Command and Byte Enable. During

the address phase of a transaction,

nC/BE[3-0] defines the bus command.

During the data phase, nC/BE[3-0] are

used as Byte Enables. nC/BE2 applies

to Byte “2”.

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MCS9845

PCI to Dual Serial and ISA Controller

Name

Pin #

Direction

Drive

Strength

Description

nC/BE1

32

I

Bus Command and Byte Enable. During

the address phase of a transaction,

nC/BE[3-0] defines the bus command.

During the data phase, nC/BE[3-0] are

used as Byte Enables. nC/BE1

applies to Byte “1”.

nC/BE0

43

I

Bus Command and Byte Enable. During

the address phase of a transaction,

nC/BE[3-0] defines the bus command.

During the data phase, nC/BE3-0 is

used as Byte Enables. nC/BE0 applies

to Byte “0”.

nINTA

120

O

12mA

PCI active low interrupt output (open-

drain). This signal goes low (active)

when an interrupt condition occurs.

EE-CS

115

O

4mA

External EEPROM chip select (active

high). After Power-On Reset, the

EEPROM is read, and the read-only

configuration registers are filled

sequentially from the first 64 Bytes in

the EEPROM.

EE-CLK

116

O

4mA

External EEPROM clock.

EE-DI

118

I

External EEPROM data input.

EE-DO

117

O

4mA

External EEPROM data output.

EE-EN

123

I(PU)

Enable EEPROM (active high, internal

pull-up). The external EEPROM can be

disabled when this pin is tied to GND or

pulled low. When the EEPROM is

disabled, default values for PCI

configuration registers will be used.

XTAL1

62

I

Crystal oscillator input or external clock

input pin (22.1184 MHz).This signal

input is used in conjunction with

XTAL2 to form a feedback circuit for

the internal timing. Two external

capacitors connected from each side of

the XTAL1 and XTAL2 to GND are

required to form a crystal oscillator

circuit.

XTAL2

61

O

Crystal oscillator output. See XTAL1

description.

UART_CLK

58

O

4mA

Master clock divided by 12 (1.8432

MHz). Standard UART clock for

115.2Kbps Baud rate.

Reserved

56

O

Reserved. No Connection, leave it as

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MCS9845

PCI to Dual Serial and ISA Controller

Name

Pin #

Direction

Drive

Strength

Description

NC at system level.

Reserved

55

O

Reserved. No Connection, leave it as

NC at system level.

ACLK

59

I(PU)

UART-A clock input. ACLK should be

connected to UART_CLK output pin.

BCLK

57

I(PU)

UART-B clock input. BCLK should be

connected to UART_CLK output pin.

TXA

105

O(PU)

12mA

UART-A serial Data Output.

nRTSA

107

O(PU)

12mA

UART-A Request-To-Send signal.

It is set high (inactive) after hardware

Reset or during internal Loop-Back

mode. When low, this indicates that

UART-A is ready to transfer data.

nRTSA has no effect on the transmitter

or receiver.

nDTRA

106

O(PU)

12mA

UART-A Data-Terminal-Ready signal.

It is set high (inactive) after hardware

Reset or during internal Loop-Back

mode. When low, this output indicates

to the modem or data set that UART-

A is ready to establish a

communication link. nDTRA has no

effect on the transmitter or receiver.

RXA

109

I(PU)

UART-A, serial Data Input.

nCTSA

111

I(PU)

UART-A Clear-To-Send signal.

When low, this indicates that the

modem or data set is ready to exchange

data. nCTSA has no effect on the

transmitter.

nDSRA

110

I(PU)

UART-A Data-Set-Ready signal.

When low, this indicates the modem or

data set is ready to establish a

communication link.

nCDA

112

I(PU)

UART-A Carrier-Detect signal.

When low, this indicates the modem or

data set has detected the data carrier.

nCDA has no effect on the transmitter.

nRIA

113

I(PU)

UART-A Ring-detect signal.

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MCS9845

PCI to Dual Serial and ISA Controller

Name

Pin #

Direction

Drive

Strength

Description

TXB

76

O(PU)

12mA

UART-B serial Data Output.

nRTSB

74

O(PU)

12mA

UART-B Request-To-Send signal.

It is set high (inactive) after a hardware

Reset or during internal Loop-Back

mode. When low, this indicates UART-

B is ready to exchange data. nRTSB

has no effect on the transmitter or

receiver.

nDTRB

75

O(PU)

12mA

UART-B Data-Terminal-Ready signal.

It is set high (inactive) after a hardware

Reset or during internal Loop-Back

mode. When low, this indicates to the

modem or data set that UART-B is

ready to establish a communication link.

nDTRB has no effect on the transmitter

or receiver.

RXB

73

I(PU)

UART-B, serial Data Input.

nCTSB

71

I(PU)

UART-B Clear-To-Send signal.

When low, this indicates the modem or

data set is ready to exchange data.

nCTSB has no effect on the

transmitter.

nDSRB

72

I(PU)

UART-B Data-Set-Ready signal.

When low, this indicates the modem or

data set is ready to establish a

communication link.

nCDB

70

I(PU)

UART-B Carrier-Detect signal.

When low, this indicates the modem

or data set has detected the Data

Carrier. nCDB has no effect on the

transmitter.

nRIB

69

I(PU)

UART-B ring-detect signal.

nCS3

103

O

4mA

Chip Select 3 (Active-Low).

nCS4

102

O

4mA

Chip Select 4 (Active-Low).

nCS5

101

O

4mA

Chip Select 5 (Active-Low).

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MCS9845

PCI to Dual Serial and ISA Controller

Name

Pin #

Direction

Drive

Strength

Description

nCS6

100

O

4mA

Chip Select 6 (Active-Low).

IRQ[5-2]

84-87

I

Active-High Interrupt inputs.

All unused interrupts must be

connected to GND for proper operation.

nIRQ6

83

I

Active-Low Interrupt input.

This pin should be tied to Vcc if it is not

used.

nIOR

81

O

12mA

External Peripheral Read signal

(Active-Low).

nIOW

80

O

12mA

External Peripheral Write signal

(Active-Low).

RST

79

O

12mA

External Peripheral Reset Signal

(Active-High).

nRST

78

O

12mA

External Peripheral Reset Signal

(Active-Low).

A[0:2]

63-65

O

4mA

External Peripheral Address Line

D[7-4]

98-95

I/O

12mA

External Peripheral Data Bus.

D[3-0]

93-90

I/O

12mA

External Peripheral Data Bus.

Test_Mode_N

67

I(PU)

Reserved.

SCAN_EN

124

I(PD)

Reserved.

NC

68

I(PU)

No Connection

GND

7,20,21,33,

44,45,60,77,

88,94,99,

108,119,125

Gnd

Power and Signal Ground.

Vcc

1,10,19,39,

54,66,82,89,

104,114

Pwr

Supply Voltage 5V

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MCS9845

PCI to Dual Serial and ISA Controller

Note: -

I (PU) - Input – Internal Pull Up

I (PD) - Input – Internal Pull Down

O (PU) - Output – Internal Pull Up

I/O - Bi-directional Signal

NC - No Connection

Pwr - Power

Gnd - Ground

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MCS9845

PCI to Dual Serial and ISA Controller

12. Architectural overview

Architecture of MCS9845CV-BA is mainly divided in to four parts

 PCI core

 UART core.

 PCI ISA Bridge core

 EEPROM

12.1 PCI Core

12.1.1 PCI Bus Operation

The execution of PCI Bus transactions take place in broadly five stages: address phase;

transaction claiming; data phase(s); final data transfer; and transaction completion.

12.1.2 Address Phase

Every PCI transaction starts with an address phase, one PCI clock period in duration. During

the address phase the initiator (also known as the current Bus Master) identifies the target

device (via the address) and type of transaction (via the command). The initiator drives the 32-

bit address onto the Address/Data Bus and a 4-bit command onto the Command/Byte-Enable

Bus. The initiator also asserts the nFRAME signal during the same clock cycle to indicate the

presence of valid address and transaction information on those buses. The initiator supplies the

starting address and command type for one PCI clock cycle. The target generates the

subsequent sequential addresses for burst transfers. The Address/Data Bus becomes the Data

Bus, and the Command/Byte-Enable Bus becomes the Byte-Enable Bus for the remainder of

the clock cycles in that transaction. The target latches the address and command type on the

next rising edge of PCI clock, as do all other devices on that PCI bus. Each device then

decodes the address and determines whether it is the intended target, and also decodes the

command to determine the type of transaction.

12.1.3 Claiming the transaction

When a device determines that it is the target of a transaction, it claims the transaction by

asserting nDEVSEL.

12.1.4 Data Phase(s)

The data phase of a transaction is the period during which a data object is transferred between

the initiator and the target. The number of data Bytes to be transferred during a data phase is

determined by the number of Command/Byte-Enable signals that are asserted by the initiator

during the data phase. Each data phase is at least one PCI clock period in duration. Both

initiator and target must indicate that they are ready to complete a data phase. If not, the data

phase is extended by a wait state of one clock period in duration. The initiator and the target

indicate this by asserting nIRDY and nTRDY respectively and the data transfer is completed at

the rising edge of the next PCI clock.

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MCS9845

PCI to Dual Serial and ISA Controller

12.1.5 Transaction Duration

The initiator, as stated earlier, gives only the starting address during the address phase. It does

not tell the number of data transfers in a burst transfer transaction.

The target will automatically generate the addresses for subsequent Data Phase transfers. The

initiator indicates the completion of a transaction by asserting nIRDY and de-asserting nFRAME

during the last data transfer phase. The transaction does not actually complete until the target

has also asserted the nTRDY signal and the last data transfer takes place. At this point the

nTRDY and nDEVSEL are de-asserted by the target.

12.1.6 Transaction Completion

When all of nIRDY, nTRDY, nDEVSEL, and nFRAME are in the inactive state (high state), the

bus is in idle state. The bus is then ready to be claimed by another Bus Master.

12.1.7 PCI Resource Allocation

PCI devices do not have “Hard-Wired” assignments for memory or I/O Ports like ISA devices do.

PCI devices use “Plug & Play” to obtain the required resources each time the system boots up.

Each PCI device can request up to six resource allocations. These can be blocks of memory

(RAM) or blocks of I/O Registers. The size of each resource block requested can also be

specified, allowing great flexibility. Each of these resource blocks is accessed by means of a

Base-Address-Register (BAR). As the name suggests, this is a pointer to the start of the

resource. Individual registers are then addressed using relative offsets from the Base-Address-

Register contents. The important thing to note is: plugging the same PCI card into different

machines will not necessarily result in the same addresses being assigned to it. For this reason,

software (drivers, etc.) must always obtain the specific addresses for the device from the PCI

System.

Each PCI device is assigned an entry in the PCI System’s shared “Configuration Space”. Every

device is allocated 256 Bytes in the Configuration Space. The first 64 Bytes must follow the

conventions of a standard PCI Configuration “Header”. There are several pieces of information

the device must present in specific fields within the header to allow the PCI System to properly

identify it. These include the Vendor-ID, Device-ID and Class-Code. These three fields should

provide enough information to allow the PCI System to associate the correct software driver with

the hardware device. Other fields can be used to provide additional information to further refine

the needs and capabilities of the device.

As part of the Enumeration process (discovery of which devices are present in the system) the

Base-Address-Registers are configured for each device. The device tells the system how many

registers (etc.) it requires, and the system maps that number into the system’s resource space,

reserving them for exclusive use by that particular device. No guarantees are made that any two

requests for resources will have any predictable relationship to each other. Each PCI System is

free to use its own allocation strategy when managing resources.

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MCS9845

PCI to Dual Serial and ISA Controller

12.1.8 Multi-Function Devices

ASIX uses the Subsystem-ID field to indicate how many Serial Ports and Parallel Ports are

provided by the current implementation. By changing the data in the Subsystem-ID field, and

stuffing only the appropriate number of external components, the same board could be used for

products with either one or two Ports. The least significant Hexadecimal digit of the Subsystem-

ID field indicates the number of Serial Ports that are currently being provided by the device.

The next higher digit indicates the number of Parallel Ports being provided. The table below

shows several different combinations and the types of Ports that would be enabled. Some ASIX

devices provide Serial Ports, some provide Parallel Ports, and some provide both types of Ports.

This field is used as an aid to the software Drivers, allowing them to easily determine how many

of each Port type to configure.

Subsystem-ID

Parallel Ports

Serial Ports

0001

0

1

0010

1

0

0012

1

2

This use of the term “Multi-Function Device” should not be confused with the more generic use

of that term by the PCI System. Each “Function” within a “Unit” (physical device) gets its own

Configuration Space Header. ASIX devices do not need this extra layer of complexity, the six

Base Address Registers provided by one PCI “Function” are more than adequate to allocate all

of the desired resources.

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MCS9845

PCI to Dual Serial and ISA Controller

12.1.9 PCI Configuration Space Header

Default values for several key fields are shown in the table below.

AD 31-24

AD 23-16

AD 15-8

AD 7-0

Offset(Hex)

Device ID (9845)

Vendor ID (9710)

00

Status

Command

04

Class Code (078000)

Revision ID (01)

08

BIST

Header Type

Latency Timer

Cache Size (08)

0C

Base Address Register (BAR) 0 – “UART-A” (U1)

10

Base Address Register (BAR) 1 – “UART-B” (U2)

14

Base Address Register (BAR) 2 – “nCS3” (E3)”

18

Base Address Register (BAR) 3 – “nCS4” (E4)”

1C

Base Address Register (BAR) 4 – “nCS5” (E5)”

20

Base Address Register (BAR) 5 – “nCS6” (E6)”

24

Reserved

28

Subsystem ID (0014)

Subsystem Vendor ID (1000)

2C

Reserved

30

Reserved

34

Reserved

38

Max Latency (00)

Min Grant (00)

Interrupt Pin (01)

Interrupt Line

3C

Reserved

Loading Timers

40

EEPROM Register

44

raidreg2

raidreg1

4’h0

Test Bus Sel

16’h9710

48

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MCS9845

PCI to Dual Serial and ISA Controller

Internal Address Select Configuration

The MCS9845 uses two Base Address Registers for its UARTs, and four for the ISA Bridge.

These essentially act as internal “Chip Select” logic.

Registers are addressed by using one of the Base Addresses plus an offset.

BAR

I/O Address Offset

Function

0 (U1)

00-07

UART-A

1 (U2)

00-07

UART-B

2 (E3)

00-07

External Chip Select 3

3 (E4)

00-07

External Chip Select 4

4 (E5)

00-07

External Chip Select 5

5 (E6)

00-07

External Chip Select 6

12.2 UART Core

12.2.1 Overview

There are 2 UARTs in the MCS9845 which are 16C450/16C550 specification. Both UARTs are

similar in operation and functionality, function of one UART described below.

Main features of Serial Port :

 Supports RS232, RS485 & RS422 modes

 Bi-directional Speeds from 50 bps to 115200 bps / port

 Full Serial modem control

 Supports hardware flow control

 5, 6, 7 and 8 bit serial format support

 Even, Odd, None, Space & Mark parity supported

12.2.2 Operational Modes

The UART is compatible with the 16C450, 16C550 mode of operation.. The operation of the port

depends upon the mode settings, which are described below. The modes, conditions &

corresponding FIFO depth are tabulated below.

UART mode

FIFO Size (Bytes)

FCR [0]

450

1

0

550

32

1

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MCS9845

PCI to Dual Serial and ISA Controller

12.2.3 450 Mode

After the hardware reset, bit 0 of the FIFO Control Register (FCR) is cleared, hence the UART is

compatible with the 16C450 mode of operation. The transmitter & receiver FIFO’s (referred to

as the "transmitting Holding register" & "receiver holding register" respectively) have a depth of

one byte. This mode of operation is known "Byte Mode".

12.2.4 550 Mode

After the hardware reset, writing a 1 to FCR [0] will increase the FIFO size to 32, providing

compatibility to 16C550 devices. In 16C550 mode of operation, the device has the following

features.

 RTS/CTS hardware flow control

 Deeper FIFO’s

12.3 ISA Bridge

A PCI to ISA Bridge allows the product designer to increase the number of I/O Ports through the

use of external components. Additional UARTs and Parallel Ports are easy to attach and

configure.

12.3.1 Chip Selects

Four external Chip Select signals (nCS3-nCS6) are provided. Each Chip Select has its own

Base Address Register (BAR) in the PCI Configuration Space. The Base Address Registers

each point to a block of eight I/O registers. When any of the eight registers in the block assigned

to one of the Base Address Registers are accessed, the Chip Select signal for that group will be

activated. The following table shows the relationship between the Base Address Registers and

the external Chip Select signals.

BAR

Offset

Chip Select

2 (E3)

00-07

nCS3

3 (E4)

00-07

nCS4

4 (E5)

00-07

nCS5

5 (E6)

00-07

nCS6

If BAR-3 contains the address 0xD800, then accessing any address between 0xD800 and

0xD807 will activate the nCS4 Chip Select line.

12.3.2 Common I/O Control Signals

In addition to the Chip Select signals, the other required ISA signals are also present. Separate

nIOR (I/O Read) and nIOW (I/O Write) signals are provided, simplifying the interface to external

components. An 8-bit bi-directional Data Bus is provided. Both Active-High and Active-Low

Reset signals are provided, simplifying the connection to external devices. Three Address Lines

(A0-2) allow each Chip Select to control eight registers.

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MCS9845

PCI to Dual Serial and ISA Controller

12.3.3 Interrupts

ISA style devices typically use Active-High Interrupt Request signals. Four Active-High Interrupt

Request inputs (IRQ2-5) are provided. A single Active-Low Interrupt Request input (nIRQ6) is

also available providing even more flexibility. There is no mechanism provided to directly

associate any of the Interrupt Request signals with any of the external Chip Select signals. The

Interrupt Requests are simply passed on to the PCI system. All I/O Ports or devices (including

those inside the chip) share a single PCI Interrupt Request line. The software Driver must poll

all of the devices to determine which one is the source of an interrupt.

2.3.4 Other Devices

While the primary purpose of the ISA Bridge is to allow products to provide additional UARTs or

Parallel Ports, it is not necessarily restricted to such devices. The signals provided should allow

the inclusion of most ISA style components into a custom design. If custom (or other standard

ISA) components are used, a custom software Driver will probably be required as well. The

ASIX Drivers only support additional UARTs and Parallel Ports.

12.4. External EEPROM

Data is read from the EEPROM immediately after a Hardware Reset, and the values obtained

are used to update the Configuration before the PCI System first sees the device on the Bus.

This allows an OEM Customers to customize the vendor and product ID’s in place of ASIX ID’s.

EEPROM can be used to arrive at different product combination by setting appropriate sub-

system ID’s. For this EE-EN (Pin#123) to be left as No Connect at system level.

If external EEPROM is disabled by connecting the EE-EN (Pin#123) to ground, after hardware

reset default values of configuration are loaded by the ASIC.

Following are main features of Serial EEPROM Interface:

 Supports Serial EEPROM of 1K Bit Size with 16bit communication capability

 Configuration Space contents can be modified through EEPROM

 Changing configuration values, different modes can be selected

 Inter Character Gap in multiples of 1bit duration can be set for UART-A & UART-B

Following EEPROM types confirmed at ASIX with MCS9845:

 Atmel AT93LC46B, AT93C46B

 MICROCHIP 93LC46B, 93AA46B, 93AA46C

 ST Micro Electronics M93C46-WMN

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MCS9845

PCI to Dual Serial and ISA Controller

13. Extended Modes through EEPROM

Mode supported by MCS9845 configuration without using external EEPROM.

 PCI to 2 Serial + ISA(2Serial + 1 Parallel)

By using external EEPROM more Peripheral configurations can be derived with MCS9845, few

such configurations listed below:

 PCI to 2 Serial + ISA(4 Serial)

 PCI to 2 Serial + ISA(2 Parallel)

Vendor ID, Product customizations can also be implemented in MCS9845, through external

EEPROM. Any change of Vendor ID, Product ID information requires customized device driver.

Note: EEPROM need to be programmed in external EEPROM burner, for all above

configuration support and for customizations.

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MCS9845

PCI to Dual Serial and ISA Controller

14. EEPROM Contents

Contents of the EEPROM (16-bit), values shown below are for 4S1P Mode

EEPROM

ADDRESS

LOCATION

HEX

Data

(Word)

Description of Contents

EEPROM

ADDRESS

LOCATION

HEX Data

(Word)

Description of

Contents

0x00

9845

Device ID

0x20

0000

0x01

0000

0x21

0000

0x02

9710

Vendor ID

0x22

0000

0x03

0000

0x23

0000

0x04

0000

{Intr_mask_reg[15:8],

icg_reg1[7:0]}

0x24

0000

0x05

0000

0x25

0000

0x06

0000

0x26

0000

0x07

0000

0x27

0000

0x08

0780

Class code(23-8)

0x28

0000

0x09

0000

0x29

0000

0x0A

0001

{class code (7-0),

Revision ID }

0x2A

0000

0x0B

0000

0x2B

0000

0x0C

0000

Header

0x2C

0014

Subsystem ID

(Changes

according to

mode)

0x0D

0000

0x2D

0000

0x0E

0000

0x2E

1000

Subsystem

Vendor ID

0x0F

0000

0x2F

0000

0x10

0000

ICG_reg2[7:0]

0x30

0000

0x11

0000

0x31

0000

0x12

0000

0x32

0000

0x13

0000

0x33

0000

0x14

0000

0x34

0000

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MCS9845

PCI to Dual Serial and ISA Controller

EEPROM

ADDRESS

LOCATION

HEX

Data

(Word)

Description of Contents

EEPROM

ADDRESS

LOCATION

HEX Data

(Word)

Description of

Contents

0x15

0000

0x35

0000

0x16

0000

0x36

0000

0x17

0000

0x37

0000

0x18

0000

0x38

0000

0x19

0000

0x39

0000

0x1A

0000

0x3A

0000

0x1B

0000

0x3B

0000

0x1C

0000

0x3C

0000

{Max_lat[7:0],

Min_gnt [7:0]}

0x1D

0000

0x3D

0000

0x1E

0000

0x3E

0100

Interrupt Pin

0x1F

0000

0x3F

0000

EEPROM Data Configuration Values

Description

EEPROM Address

Location

Word/Byte Data

Device ID

0x00

9845

Vendor ID

0x02

9710

Class code

0x08

0780

Class code Interface

0x0A (Most Significant

Byte)

00

Revision ID

0x0A (Least Significant

Byte)

01

Header

0x0C

(Least Significant Byte)

00

Subsystem ID

0x2C

0012

Subsystem Vendor ID

0x2E

1000

Interrupt pin

0x3E (Most Significant

Byte)

01

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MCS9845

PCI to Dual Serial and ISA Controller

Description

EEPROM Address

Location

Word/Byte Data

Icg_reg1[7:0]

Inter Character Gap setting

register for UART-A

0x04(Least Significant

Byte)

00 (This value is used to

put the delay between each

character).

Icg_reg2[7:0]

Inter Character Gap setting

register for UART-B

0x10(Least Significant

Byte)

00 (This value is used to

put the delay between each

character).

Intr_mask_reg[15:8]

0x04(Most Significant Byte)

00

Icg_reg1 & 2 : Inter Character Gap register is used to set Inter Character Gap in multiples of

1bit duration for UART-A & B Ports

Intr_mask_reg [15:0]: Interrupt Mask Register can be used to mask the interrupt from unused

Serial ports or ISA Bus.

Register(bit)

Value(Default for

2S+ ISA(2S+1P)

Description

Intr_mask_reg[8]

0

UART-A Interrupt Mask register. By setting

this bit to “1” interrupts can be disabled from

this Port.

Intr_mask_reg[9]

0

UART-B Interrupt Mask register. By setting

this bit to “1” interrupts can be disabled from

this Port.

Intr_mask_reg[10]

0

ISA Bus Interrupt Mask register. By setting

this bit to “1” interrupts can be disabled from

this Bus.

The EEPROM controller reads the least significant byte and then the most significant byte in the

16-bit format. Therefore, when writing to each address in the EEPROM, the least significant

byte must be written first, followed by the most significant byte. For example, to write 9845 into

address 0x00, the value would be written as 45 98, where 45 is the least significant byte and is

written first.

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MCS9845

PCI to Dual Serial and ISA Controller

15. Electrical Specifications

Absolute Maximum Ratings

Supply Voltage 6 Volts

Voltage at any pin GND - 0.3 V to VCC + 0.3 V

Junction Temperature (Tj) 0 °C to +115 °C

Operating Temperature 0 °C to +70 °C

Storage Temperature -40 °C to +150 °C

ESD HBM (MIL-STD 883E Method 3015-7 Class 2) 2000V

ESD MM (JEDEC EIA/JEDS22 A115-A) 200V

CDM (JEDEC JEDS22 C101-A) 500V

Latch up (JESD No. 78, March 1997) 200 mA, 1.5 x Vcc

Recommended Operating Conditions:

Symbol

Parameter

Min

Typ

Max

Unit

Condition

Vcc

Supply Voltage

4.75

5

5.25

V

Vin

Input Voltage

0

Vcc

Icc

Operating Current

70

mA

No Serial Load

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MCS9845

PCI to Dual Serial and ISA Controller

DC Electrical Characteristics: Ta = 0 to +70 °C, VCC = 4.75 to 5.25 V unless otherwise specified.

Symbol

Parameter

Min

Typ

Max

Unit

Condition

ViL

Input Voltage (Low)

0.3 *Vcc

V

CMOS

ViH

Input Voltage (High)

0.7 *Vcc

V

CMOS

ViL

Input Voltage (Low)

0.8

V

TTL

ViH

Input Voltage (High)

2.0

V

TTL

Vt-

Schmitt Trigger

Negative-Going Threshold Voltage

1.84

V

CMOS

Vt+

Schmitt Trigger

Positive-Going Threshold Voltage

3.22

V

CMOS

Vt-

Schmitt Trigger

Negative-Going Threshold Voltage

1.10

V

TTL

Vt+

Schmitt Trigger

Positive-Going Threshold Voltage

1.87

V

TTL

VoL

Output Voltage (Low)

0.4

V

IoL = 2 to 24 mA

VoH

Output Voltage (High)

3.5

V

IoH = 2 to 24mA

Ri

Input Pull-Up/Pull-Down

Resistance

50

KΩ

ViL = 0V or

ViH = Vcc

Thermal Characteristics:

Description

Symbol

Rating

Units

Thermal resistance of junction to case

ΘJC

18.8

°C/W

Thermal resistance of junction to

ambient

ΘJA

43

°C/W

Note:

JA



,

JC



defined as below

JA



=

PTT AJ 

,

JC



=

PTT CJ 

TJ: maximum junction temperature (°C) TA: ambient or environment temperature (°C)

TC: the top center of compound surface temperature (°C) P: input power (watts)

29

MCS9845

PCI to Dual Serial and ISA Controller

16. Mechanical Specifications – QFP 128

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MCS9845

PCI to Dual Serial and ISA Controller

Revision History

Revision

Date

Comment

0.1

16th Dec 2007

Initial release

1.0

1st May 2008

“Tentative Data Sheet” text removed in all pages & document version

updated to 1.0

1.1

9th March 2010

SW Support updated for Windows 7 and WHQL drivers availability

2.00

2011/08/05

1. Changed to ASIX Electronics Corp. logo, strings and contact

information.

2. Added ASIX copyright legal header information.

3. Modified the Revision History table format.

4. Updated the block diagram in Section 9.

2.01

2012/09/12

1. Added Junction Temperature (Tj) and Thermal Characteristics

information in Section 15.

31

MCS9845

PCI to Dual Serial and ISA Controller

4F, No. 8, Hsin Ann Rd., HsinChu Science Park,

HsinChu, Taiwan, R.O.C.

TEL: 886-3-5799500

FAX: 886-3-5799558

Sales Email: sales@asix.com.tw

Support Email: support@asix.com.tw

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