This document contains information on a product under development at Advanced Micro Devices. The information
is intended to h elp you evaluate t his product. AMD re serves the right to chan ge or discontinu e work on this proposed
product without notice.
Publication# 24218 Rev: BAmendment/1
Issue Date: March 15, 2001
Refer to AMD’s Website (www .a md.com) for the latest information.
DS42553
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL323D To p Boot 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
■Power su ppl y voltage of 2.7 to 3.3 volt
■High performance
— 90 ns maximum access time
■Package
— 73-Ball FBGA
■Operati ng Tem perature
— –25°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
■Simultaneous Read/ Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
■Secured Silicon (SecSi) Sector: Extra 64 KByte sector
—Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.
—Customer lockable: Can be read, programmed, or erased
just like other sectors. Once locked, data cannot be changed
■Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero
■Top boot block
■Manufacture d on 0.23 µm process te chnology
■Compatible with JEDEC standards
—Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
■High performance
—Access time as fast 70 ns
—Program time: 7 µs/word typical utilizing Accelerate function
■Ultra low pow er consumption (typical values)
—2 mA active read current at 1 MHz
—10 mA active read current at 5 MHz
—200 nA in standby or automatic sleep mode
■Minimum 1 millio n w r i te cycles gu aranteed per sector
■20 Year data rete nt io n at 125°C
—Reliable operation for the life of the system
SOFTWARE FEATURES
■Data Management Software (DMS)
—AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
—Eases sector erase limi tation s
■Supports Com m on Flash Memory Interfac e (CFI)
■Erase Suspend/Erase Resume
—Suspends erase operations to allow programming in same
bank
■Data# Polling and Toggle Bits
—Provides a software method of detecting the status of
program or erase cycles
■Unlock Bypas s Pro gr am comma nd
—Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
■Any combination of sectors can be erased
■Ready/Busy# output (RY/BY#)
—Hardware method for detecting program or erase cycle
completion
■Hardwar e reset pin (RESET#)
—Hardware method of resetting the internal state machine to
reading array data
■WP#/ACC input pin
—Write protect (WP#) function allows protection of two outermost
boot sectors, regardless of sector protect status
—Acceleration (ACC) function accelerates program timing
■Sector protect ion
—Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
—Temporary Sector Unprotect allows changing data in
protected sectors in-system
SRAM Features
■Power dissipation
—Operating: 50 mA maximum
—Standby: 7 µA maximum
■CE1s# an d C E2s Chip Select
■Power do w n fe at ures using C E1s# and CE2s
■Data retent io n supply voltage: 1.5 to 3.3 volt
■Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)
2 DS42553
GENERAL DESCRIPTION
Am29DL323 Features
The Am29DL323 is a 32 megabit, 3.0 volt-only flash
memory devices , organiz ed as 2,097 ,152 word s of 16
bits each or 4,194,304 bytes of 8 bits each. Word
mode data appears on DQ 0–DQ15; byte mode data
appears on DQ0–DQ7. The device is designed to b e
programmed in-system with the standard 3.0 volt VCC
supply, and can also be programmed in standard
EPROM pr ogrammers.
The device is av ailable with an access time of 90 ns.
The device is offered in a 73-ball FBGA package.
Standa rd contr ol pins—chip enable (CE#f), write en-
able (W E#), and out put enab le (OE #)—c ontrol n ormal
read and write operations, and avoid bus contention
issues.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally
generate d and reg ulated voltages are prov ided for the
program and erase operations.
Simultaneous Rea d/Write Ope rations with
Zero Latency
The Simultaneous Read/Write architecture pro vides
simultaneous operation by dividing the memory
space into two banks. The device can improve overall
system perfor m anc e b y all owi ng a host s y ste m to pro-
gram or erase in one bank, then immediately and
simulta neously read from the other bank, with zero la-
tency. This releases the system from wa iting for the
completion of program or erase operations.
The Am2 9DL323D has 8 Mb in Bank 1 and 24 Mb in
Bank 2.
The Secured Silicon (SecSi) Sector is an extr a 64
Kbit sector capable of being permanently locked by
AMD or customers. The SecSi Sector Indicator Bit
(DQ7) is permane ntly set to a 1 if the p art is factory
locked, and set to a 0 if customer lockable. This
way, custo mer lock abl e parts ca n nev er be us ed to r e-
place a factory locked part.
Factory locked parts provide several options. The
SecSi Sector may store a secure, rand om 16 byte
ESN (Electronic Serial Number). Customer Lockable
parts may utilize the SecSi Sector as bonus space,
reading and writing like any ot her flash sector, or may
permanently lock their own code there.
DMS (Data Management Software) allows systems
to easi ly take ad vantag e of the adv ance d archite cture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it wi ll perform all
functions necessary to modify data in f ile structures,
as opposed to single-byte modifica tions. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user onl y needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
is an advantage compared to systems where
user-written softwar e must kee p track of the ol d data
location, status, logical to physical translation of the
data onto the F lash memory de vice (or memor y de-
vices), and more. Using DMS, user-written software
does not need to interfac e with the Flash memory di-
rectly. Inste ad, t he u se r's software acc esse s t he Fl as h
memory by calling one of only s ix functio ns. AMD pr o-
vides this software to simplify system design and
software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EP ROM devi c es .
The host system can detect whether a program or
erase operat ion is complete by usi ng the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to reading array data.
The sector erase architecture allows memory sec-
tors to be eras ed and reprogr ammed wit hout affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measu res incl ude a low
VCC detector that automatically inhibits write opera-
tions during power trans itions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via
programmi ng equ ipm ent.
The device offers two power -saving features. Whe n
addres ses have been sta ble f or a spe cified amoun t of
time, the device enter s the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both modes.
DS42553 3
TABLE OF CONTENTS
Distinctive Characteristics . . . . . . . . . . . . . . . . . . 1
MCP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Flash Memory Features . . . . . . . . . . . . . . . . . . . . .1
Architectural Advantages . . . . . . . . . . . . . . . . . . .1
Performance Characteristics . . . . . . . . . . . . . . . .1
Software Features . . . . . . . . . . . . . . . . . . . . . . . .1
Hardware Features . . . . . . . . . . . . . . . . . . . . . . .1
SRAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description. . . . . . . . . . . . . . . . . . . . . . . . 2
Am29DL323 Features . . . . . . . . . . . . . . . . . . . . . .2
Simultaneous Read/Write Operations with Zero
Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package .7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Device Bus Operations—Flash Word
Mode, CIOf = VIH; SRAM Word Mode,
CIOs = VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 2. Device Bus Operations—Flash Word
Mode, CIOf = VIH; SRAM Byte Mode,
CIOs = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 3. Device Bus Operations—Flash Byte
Mode, CIOf = VIL; SRAM Byte Mode,
CIOs = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Word/Byte Configuration . . . . . . . . . . . . . . . . . . . 12
Requirements for Reading Array Data . . . . . . . . .12
Writing Commands/Command Sequences . . . . .12
Accelerated Program Operation . . . . . . . . . . . .12
Autoselect Functions . . . . . . . . . . . . . . . . . . . . .12
Simultaneous Read/Write Operations with Zero
Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . .13
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . .13
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . .13
Table 4. Device Bank Division . . . . . . . . . . . . . .13
Table 5. Sector Addresses for Top Boot Sector
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 6. SecSi Sector Addresses for Top
Boot Devices . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . 16
Sector/Sector Block Protection and Unprotection 16
Table 7. Top Boot Sector/Sector Block
Addresses for Protection/Unprotection . . . . . . .16
Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . .16
Temporary Sector/Sector Block Unprotect . . . . . .17
Figure 1. Temporary Sector Unprotect
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 2. In-Sys tem Se cto r/ Sector Blo ck
Protect and Unprotect Algorithms. . . . . . . . . . . 18
SecSi (Secured Silicon) Sector Flash Memory
Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Factory Locked: SecSi Sector Programmed
and Protected At the Factory . . . . . . . . . . . . . . 19
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory . . . . . 19
Hardware Data Protection . . . . . . . . . . . . . . . . . . 19
Low VCC Write Inhibit . . . . . . . . . . . . . . . . . . . . 19
Write Pulse “Glitch” Protection . . . . . . . . . . . . . 19
Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . 20
Common Flash Memory Interface (CFI) . . . . . . . 20
Table 8. CFI Query Identification String . . . . . . 20
Table 9. System Interface String . . . . . . . . . . . 21
Table 10. Device Geometry Definition . . . . . . . 21
Table 11. Primary Vendor-Specific Extended
Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Command Definitions. . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . 23
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . 23
Autoselect Command Sequence . . . . . . . . . . . . . 23
Enter SecSi Sector/Exit SecSi Sector
Command Sequence . . . . . . . . . . . . . . . . . . . . . . 24
Byte/Word Program Command Sequence . . . . . 24
Unlock Bypass Command Sequence . . . . . . . . 24
Figure 3. Program Operation. . . . . . . . . . . . . . . 25
Chip Erase Command Sequence . . . . . . . . . . . . 25
Sector Erase Command Sequence . . . . . . . . . . . 25
Erase Suspend/Erase Resume Commands . . . . 26
Figure 4. Erase Operation . . . . . . . . . . . . . . . . . 26
Table 12. DS42553 Command Definitions . . . . 27
Write Operation Status. . . . . . . . . . . . . . . . . . . . . 28
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 5. Data# Polling Algorithm . . . . . . . . . . . 28
RY/BY#: Ready/Busy#. . . . . . . . . . . . . . . . . . . . . 29
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 6. Toggle Bit Algorithm . . . . . . . . . . . . . . 29
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . 30
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . 30
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . 30
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . 30
Table 13. Write Operation Status . . . . . . . . . . . 31
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 32
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 32
Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . 32
VCCf/VCCs Supply Voltage . . . . . . . . . . . . . . . . . 32
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . 33
SRAM DC and Operating Characteristics. . . . . . 34
Zero-Power Flash . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. ICC1 Current vs. Time (Showing
Active and Automatic Sleep Currents). . . . . . . . 35
Figure 10. Typical ICC1 vs. Frequency . . . . . . . . 35
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Test Setup . . . . . . . . . . . . . . . . . . . . 36
Table 14. Test Specifications . . . . . . . . . . . . . . 36
4 DS42553
Key To Switching Waveforms. . . . . . . . . . . . . . . 36
Figure 12. Input Waveforms and
Measurement Levels . . . . . . . . . . . . . . . . . . . . 36
AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 37
SRAM CE#s Timing . . . . . . . . . . . . . . . . . . . . . . .37
Figure 13. Timing Diagram for Alternating
Between SRAM to Flash. . . . . . . . . . . . . . . . . . 37
Flash Read-Only Operations . . . . . . . . . . . . . . . .38
Figure 14. Read Operation Timings . . . . . . . . . 38
Hardware Reset (RESET#) . . . . . . . . . . . . . . . . .39
Figure 15. Reset Timings . . . . . . . . . . . . . . . . . 39
Flash Word/Byte Configuration (CIOf) . . . . . . . . .40
Figure 16. CIOf Timings for Read Operations . 40
Figure 17. CIOf Timings for Write Operations. . 40
Flash Erase and Program Operations . . . . . . . . .41
Figure 18. Program Operation Timings. . . . . . . 42
Figure 19. Accelerated Program Timing
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 20. Chip/Sector Erase Operation
Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 21. Back-to-back Read/Write Cycle
Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22. Data# Polling Timings (During
Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 44
Figure 23. Toggle Bit Timings (During
Embedded Algorithms) . . . . . . . . . . . . . . . . . . . 45
Figure 24. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . 45
Temporary Sector/Sector Block Unprotect . . . . . .46
Figure 25. Temporary Sector/Sector Block
Unprotect Timing Diagram . . . . . . . . . . . . . . . . 46
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram . . . . . . . . . . . . . . . . 47
Alternate CE#f Controlled Erase and Program
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 27. Flash Alternate CE#f Controlled
Write (Erase/Program) Operation Timings . . . . 49
SRAM Read Cycle . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 28. SRAM Read Cycle—Address
Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 29. SRAM Read Cycle . . . . . . . . . . . . . . 51
SRAM Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 30. SRAM Write Cycle—WE# Control . . 52
Figure 31. SRAM Write Cycle—CE1#s Control. 53
Figure 32. SRAM Write Cycle—UB#s and
LB#s Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Flash Erase And Programming Performance . . . 55
Flash Latchup Characteristics. . . . . . . . . . . . . . . 55
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 55
FLASH Data Retention . . . . . . . . . . . . . . . . . . . . . 55
SRAM Data Retention. . . . . . . . . . . . . . . . . . . . . . 56
Figure 33. CE1#s Controlled Data Retention
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 34. CE2s Controlled Data Retention
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57
FLB073—73-Ball Fine-Pitch Grid Array
8 x 11 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision A (October 9, 2000) . . . . . . . . . . . . . . . 58
Revision B (March 8, 2001) . . . . . . . . . . . . . . . . . 58
Global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Flash Memory Block Diagram . . . . . . . . . . . . . . 58
Table 7, Top Boot Sector/Sector Block
Addresses for Protection/Unprotection . . . . . . . 58
Sector/Sector Block Protection/Unprotection . . 58
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory . . . . . 58
Common Flash Memory Interface (CFI) . . . . . . 58
Command Definitions . . . . . . . . . . . . . . . . . . . . 58
Revision B+1 (March 15, 2001) . . . . . . . . . . . . . . 58
DS42553 5
PRODUCT SELECTOR GUIDE
MCP BLOCK DIAGRAM
Part Number DS42553
Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory SRAM
Max Access Time (ns) 90 85
CE# Access (ns) 90 85
OE# Access (ns) 40 45
V
SS
/V
SSQ
V
CC
s/V
CCQ
RESET#
WE#
CE#f
OE#
CE1#s
V
SS
V
CC
f
RY/BY#
LB#s
UB#s
CIOf
WP#/ACC
CE2s
SA
CIOs
4 M Bit
Static RAM
32 M Bit
Flash Memory DQ0 to DQ15/A
–
1
DQ0 to DQ15/A
–
1
DQ0 to DQ15/A
–
1
A0 to A20
A0 to A20
A0 to A19
A
–
1
A0 to A17
6 DS42553
FLASH MEMORY BLOCK DIAGRAM
V
CC
V
SS
Upper Bank Address
A0–A20
RESET#
WE#
CE#
BYTE#
DQ0–DQ15
WP#/ACC
STATE
CONTROL
&
COMMAND
REGISTER
RY/BY#
Upper Bank
X-Decoder
Y-Decoder
Latches and Control Logic
OE# BYTE#
DQ0–DQ15
Lower Bank
Y-Decoder
X-Decoder
Latches and
Control Logic
Lower Bank Address
OE# BYTE#
Status
Control
A0–A20
A0–A20
A0–A20A0–A20
DQ0–DQ15 DQ0–DQ15
DS42553 7
CONNECTION DIAGRAM
Special Handling Instructions for FBGA
Package
Special handling is required for F lash Memory prod-
ucts in FBGA pack ages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compro-
mised if the package body is exposed to temperatures
above 150°C for prolonged periods of time.
A1
B1
C1
F1
G1
L1
M1
D2
E2
F2
G2
H2
J2
C3
D3
E3
F3
G3
H3
J3
K3
C4
D4
E4
F4
G4
H4
J4
K4
B5
C5
D5
E5
H5
J5
K5
L5
B6
C6
D6
E6
H6
J6
K6
L6
C7
D7
E7
F7
G7
H7
J7
K7
C8
D8
E8
F8
G8
H8
J8
K8
D9
E9
F9
G9
H9
J9
A10
B10
F10
G10
L10
M10
NC
NC
NC
NC
NC
NC NC
NC
NC
A3
A2
A1
A0
CE#f
CE1#s
A7
A6
A5
A4
VSS
OE#
DQ0
DQ8
LB#
UB#
A18
A17
DQ1
DQ9
DQ10
DQ2
NC
WP#/ACC
RESET#
RY/BY#
DQ3
VCCf
DQ11
NC
WE#
CE2s
A20
DQ4
VCCs
CIOs
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
A11
A12
A13
A14
SA
DQ15/A-1
DQ7
DQ14
A15
NC
NC
A16
CIOf
VSS
NC
NC
NC
NC
NC
NC
SRAM only
Shared
Flash only
73-Ball FBGA
Top View
8 DS42553
PIN DESCRIPTION
A0–A17 = 18 Address Inputs (Common)
A-1, A18–A20 = 4 Address Inputs (Flash)
SA = Highest Order Address Pin (SRAM)
Byte mode
DQ0–DQ15 = 16 Data Inputs/Out pu ts (Commo n)
CE#f = Chip Enable (Flash)
CE#s = Chip Enable (SRAM)
OE# = Output Enable (Common)
WE# = Write Enable (Common)
RY/BY# = Ready/Busy Output
UB#s = Upper Byte Control (SRAM)
LB#s = Lower Byte Control (SRAM)
CIOf = I/O Configuration (Flash)
CIOf = VIH = Word mode (x16),
CIOf = VIL = Byte mode (x8)
CIOs = I/O Configuration (SRAM)
CIOs = VIH = Word mode (x16),
CIOs = VIL = Byte mode (x8)
RESET# = Hardware Reset Pin, Active Low
WP#/ACC = Hardware Write Protect/
Acceleration Pin (F lash)
VCCf = Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed option s and vo lta ge sup ply
tolerances)
VCCs = SRAM Power Su pply
VSS = Device Ground (Common)
NC = Pin Not Connected Internally
LOGIC SYMBOL
ORDERING INFORMATION
DEVICE BUS OPERATIONS
This section describe s the requirements and use of
the device bus operations, which are initiated through
the in ternal co mmand r egiste r. The c ommand r egist er
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the
commands, along with the address and data informa-
tion needed to exe cu te th e c omm and . The c on ten ts of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Tables 1 thr ough 3 lists the devic e bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections de-
scribe each of these operations in further detail.
18
16 or 8
DQ0–DQ15
A0–A17
CE#f
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
SA
A-1, A18–A20
LB#s
CIOf
CIOs
CE1#s
CE2s
Valid Com bin a tion
Order Number Package Marking
DS42553 DS42553
DS42553 9
Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
4. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
5. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
Operation
(Notes 1, 2) CE#f CE1#s CE2s OE# WE# SA LB#s UB#s RESET# WP#/ACC
(Note 3) DQ0– DQ7 DQ8–DQ15
Read from Flash L HX
LH X X X H L/H D
OUT DOUT
XL
Wr ite to Flas h L HX
H L X X X H (Note 3) DIN DIN
XL
Standby VCC ±
0.3 V HX
XX X X XVCC ±
0.3 V HHigh-ZHigh-Z
XL
Output Disable
HLH
HH X L X
H L/H High-Z High-Z
HH X X L
LHX
HH X X X
XL
Flash Ha rdware
Reset XHX
X X X X X L L/H High-Z High-Z
XL
Sector Protect
(Note 4) LHX
HL X X X V
ID L/H DIN X
XL
Sector Unprotec t
(Note 4) LHX
HL X X X V
ID (Note 5) DIN X
XL
Temporary Sector
Unprotect XHX
XX X X X V
ID (Note 5) DIN High-Z
XL
Read from SRA M H L H L H X
LL
HX
DOUT DOUT
HL High-Z D
OUT
LH D
OUT High-Z
Write to SRAM H L H X L X
LL
HX
DIN DIN
HL High-Z D
IN
LH D
IN High-Z
10 DS42553
Table 2. Device Bus Operations—Flash Wo rd Mode, CIOf = VIH; SRAM Byte Mode, CIOs = VSS
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP # /ACC = VHH, all sectors will be unprotected.
Operation
(Notes 1, 2) CE#f CE1#s CE2s OE# WE# SA LB#s
(Note 3) UB#s
(Note 3) RESET# WP#/ACC
(Note 4) DQ0–DQ7 DQ8–DQ15
Read from Flash L HX
LH X X X H L/H D
OUT DOUT
XL
Wri te to Flash L HX
H L L X X H (Note 3) DIN DIN
XL
Standby VCC ±
0.3 V HX
XX X X X VCC ±
0.3 V H High-Z High-Z
XL
Output Disable
HLH
HH X L X
H L/H High-Z High-Z
HH X X L
LHX
HH X X X
XL
Flash Ha rdware
Reset XHX
X X X X X L L/H High-Z High-Z
XL
Sector Protect
(Note 5) LHX
HL X X X V
ID L/H DIN X
XL
Sector Unprotect
(Note 5) LHX
HL X X X V
ID (Note 6) DIN X
XL
Temporary Sector
Unprotect XHX
XX X X X V
ID (Note 6) DIN High-Z
XL
Read from SRAM H L H L H SA X X H X DOUT High-Z
Write to SRAM H L H X L SA X X H X DIN High-Z
DS42553 11
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP # /ACC = VHH, all sectors will be unprotected.
Operation
(No tes 1, 2) CE#f CE1#s CE2s DQ15/
A–1OE#
WE# SA LB#s
(Note 3) UB#s
(No te 3) RESET# WP#/ACC
(Note 4) DQ0–DQ7 DQ8–DQ15
Read from Flash L HX
A–1LH X X X H L/H D
OUT High-Z
XL
Write to Flash L HX
A–1HL X X X H
(Note 3)
DIN High-Z
XL
Standby VCC ±
0.3 V HX XX X X X VCC ±
0.3 V H High-Z High-Z
XL
Output Disable
HLHXHHX L X
H L/H High-Z High-Z
HHXX X L
LHX
A–1HH X X X
XL
Flash Hardware
Reset XHXX X X X X X L L/H High-Z High-Z
XL
Sector Protect
(Note 5) LHX HL X X X V
ID L/H DIN X
XL
Sector Unprotect
(Note 5) LHX HL X X X V
ID (Note 6) DIN X
XL
Temporary
Sector Unprotect XHx XX X X X V
ID (Note 6) DIN High-Z
XL
Read from
SRAM HLHXLHSAX X H X D
OUT High-Z
Write to SRAM H L H X X L SA X X H X DIN High-Z
12 DS42553
Word/Byte Configuration
The CIOf pin controls whether the device data I/O pins
operat e in the byte or wo rd config uration. If the CIOf
pin is set at lo gic ‘1’, the de vice is in wor d config ura-
tion, DQ0–DQ15 are active and controlled by CE# and
OE#.
If the CIOf pin is set at l ogic ‘0’, t he devic e is i n byt e
config uration, and only data I/O pi ns DQ0–DQ7 are
active an d controlle d by CE# and OE#. T he data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive th e CE#f and OE# pins to VIL. CE#f i s the po wer
contro l and sele cts the de vice. O E# is the outpu t con-
trol and gates array data to the output pins. WE#
should remain at VIH. The CIOf pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon dev ice power -up, or after a hardwa re res et. Th is
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is n ecessary in this m ode to obtai n array data .
Stand ard micro process or read cyc les that as sert vali d
address es on t he devi ce add ress inputs produ ce va lid
data o n the device data ou tputs. Each bank rem ains
enabled for read ac cess until the co mmand register
contents are altered.
See “Requirements for Reading Array Data” for more
information. Refer to the AC Flash Read-Only Opera-
tions table for timing specifications and to Figure 14 for
the timing diagram. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes progra mming data to the dev ice and erasing
sectors of memor y), the system must dr ive WE# an d
CE#f to VIL, and OE# to VIH.
For program operations, the CIOf pin determines
whether the d evice ac cepts prog ram data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
The devic e fe atures a n Unlock Bypas s mode to facil-
itate faster programming. Once a bank enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Configuration” section has details on pro-
gramming data to the device using both standard and
Unlock Bypass command sequences.
An erase operation can erase one sector , multiple sec-
tors, or the entire device. Tables 5–6 indicate the
address space that each sector occupies. The device
address space is divided into two banks: Bank 1 con-
tains the boo t/par a mete r sec tors, and Bank 2 co ntai ns
the larger, code sectors of uniform size. A “bank ad-
dress” is t he address b its r equ ir ed t o un iqu ely s el ect a
bank. Similarly, a “sector address” is the address bits
required to uniquely select a sector.
ICC2 in the DC Charact eristics table repres ents the ac-
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. T his is one of two func tions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
If the system asserts VHH on th is pin, the de vice au to-
maticall y enters th e aforemention ed Unlock B ypass
mode, temporarily unprotects any protected sectors,
and u ses the h igher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as requir ed by the Unlock Bypass mo de. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. Note that the WP#/ACC pin must not
be at VHH for operations other than accelerated pro-
gramming, or de vice damage may result. In ad dition,
the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result.
Autoselect Fun ctions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselec t codes from the inter -
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more
information.
Simultaneous Rea d/Write Ope rations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memo ry. An eras e op erati on ma y al so be su s-
pended to rea d from or program to an other location
within the same bank (except the sector being
erase d). Figu re 21 shows how re ad and write cycl es
may be initiated for simultaneous operation with zero
late ncy. ICC6 and ICC7 in th e DC Character istics tab le
represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.
DS42553 13
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The devic e ente rs the CM OS stan dby m ode whe n the
CE#f and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE#f and RESET# are held at VIH, but not
within VCC ± 0.3 V, the device will be in the standby
mode, but th e standby cur rent wi ll b e greate r. Th e de-
vice requires standard access time (tCE) for read
acces s when the devic e is in either of the se standby
modes, before it is ready to read data.
If the device is deselecte d during eras ure or progra m-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standb y cu rren t spec if ic ati on.
Automatic Slee p Mode
The automatic sleep mode minimizes Flash device en-
ergy cons umption. The dev ice automatica lly enables
this mode w hen addr esses r emain s table f or tACC +
30 ns. The automa tic sleep mod e is indepe ndent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when
addresses are cha nged. While in sle ep mode, output
data i s latche d and a lways av ailable t o the s ystem.
ICC4 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Rese t Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP,
the device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. T he device also resets the i nternal state ma-
chine to r eading arra y data. The oper ation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS ± 0.3 V, the de-
vice draws CMOS standby current (ICC4). If RESET# is
held at V IL but no t within VSS ± 0.3 V, the standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether t he res et ope ration i s co mplete . If RES ET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of tREADY (not during Embed-
ded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram .
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 4. Device Bank Division
Device
Part Number
Bank 1 Bank 2
Megabits Sector Sizes Megabits Sector Sizes
Am29DL323D 8 Mbit Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword 24 Mbit Forty-eight
64 Kbyte/32 Kword
14 DS42553
Table 5. Sector Addresses for Top Boot Sector Devices
Am29DL323DT
Sector Sector Address
A20–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
Bank 2
SA0 000000xxx 64/32 000000h–00FFFFh 000000h–07FFFh
SA1 000001xxx 64/32 010000h–01FFFFh 008000h–0FFFFh
SA2 000010xxx 64/32 020000h–02FFFFh 010000h–17FFFh
SA3 000011xxx 64/32 030000h–03FFFFh 018000h–01FFFFh
SA4 000100xxx 64/32 040000h–04FFFFh 020000h–027FFFh
SA5 000101xxx 64/32 050000h–05FFFFh 028000h–02FFFFh
SA6 000110xxx 64/32 060000h–06FFFFh 030000h–037FFFh
SA7 000111xxx 64/32 070000h–07FFFFh 038000h–03FFFFh
SA8 001000xxx 64/32 080000h–08FFFFh 040000h–047FFFh
SA9 001001xxx 64/32 090000h–09FFFFh 048000h–04FFFFh
SA10 001010xxx 64/32 0A0000h–0AFFFFh 050000h–057FFFh
SA11 001011xxx 64/32 0B0000h–0BFFFFh 058000h–05FFFFh
SA12 001100xxx 64/32 0C0000h–0CFFFFh 060000h–067FFFh
SA13 001101xxx 64/32 0D0000h–0DFFFFh 068000h–06FFFFh
SA14 001110xxx 64/32 0E0000h–0EFFFFh 070000h–077FFFh
SA15 001111xxx 64/32 0F0000h–0FFFFFh 078000h–07FFFFh
SA16 010000xxx 64/32 100000h–10FFFFh 080000h–087FFFh
SA17 010001xxx 64/32 110000h–11FFFFh 088000h–08FFFFh
SA18 010010xxx 64/32 120000h–12FFFFh 090000h–097FFFh
SA19 010011xxx 64/32 130000h–13FFFFh 098000h–09FFFFh
SA20 010100xxx 64/32 140000h–14FFFFh 0A0000h–0A7FFFh
SA21 010101xxx 64/32 150000h–15FFFFh 0A8000h–0AFFFFh
SA22 010110xxx 64/32 160000h–16FFFFh 0B0000h–0B7FFFh
SA23 010111xxx 64/32 170000h–17FFFFh 0B8000h–0BFFFFh
SA24 011000xxx 64/32 180000h–18FFFFh 0C0000h–0C7FFFh
SA25 011001xxx 64/32 190000h–19FFFFh 0C8000h–0CFFFFh
SA26 011010xxx 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh
SA27 011011xxx 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh
SA28 011100xxx 64/32 1C0000h–1CFFFFh 0E0000h–0E7FFFh
SA29 011101xxx 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh
SA30 011110xxx 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh
SA31 011111xxx 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh
SA32 100000xxx 64/32 200000h–20FFFFh 100000h–107FFFh
SA33 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
SA34 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
SA35 100011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
SA36 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA37 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA38 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
SA39 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA40 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA41 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA42 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA43 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA44 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA45 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA46 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
SA47 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
DS42553 15
Note: The address range is A20:A-1 in byte mode (CIOf=VIL) or A20:A0 in word mode (CIOf=VIH). The bank addres s bits are A20
and A19 for Am29DL323DT.
Table 6. SecSi Sector Addresses for Top Boot Devices
Bank 1
SA48 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA49 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA50 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA51 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA52 110100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA53 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA54 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA55 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA56 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA57 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA58 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA59 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
SA60 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA61 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA62 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA63 111111000 8/4 3F0000h–3F1FFFh 1F8000h–1F8FFFh
SA64 111111001 8/4 3F2000h–3F3FFFh 1F9000h–1F9FFFh
SA65 111111010 8/4 3F4000h–3F5FFFh 1FA000h–1FAFFFh
SA66 111111011 8/4 3F6000h–3F7FFFh 1FB000h–1FBFFFh
SA67 111111100 8/4 3F8000h–3F9FFFh 1FC000h–1FCFFFh
SA68 111111101 8/4 3FA000h–3FBFFFh 1FD000h–1FDFFFh
SA69 111111110 8/4 3FC000h–3FDFFFh 1FE000h–1FEFFFh
SA70 111111111 8/4 3FE000h–3FFFFFh 1FF000h–1FFFFFh
Device Sector Address
A20–A12 Sector
Size (x8)
Address Range (x16)
Address Range
Am29DL323DT 111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFh
Table 5. Sector Addresses for Top Boot Sector Devices (Continued)
Am29DL323DT
Sector Sector Address
A20–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
16 DS42553
Autoselect Mode
The autos elect mode provid es manufacture r and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be
progra mmed with i ts corresp onding pro grammin g al-
gorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
comma nd regis ter, as shown in Table 12. This me tho d
does not require VID. Refer to the Autoselect Com-
mand Sequence section for more information.
Sector/S ec tor Block Protection and
Unprotection
(Note: For the foll owing discussi on, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
7).
T able 7. T op Boot Sector/Sector Block Addresses
for Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector . The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
secto rs. Note that the sector unprotec t algorithm un-
protect s all sectors in parallel. All previously protected
sectors must be individually re-protected. To change
data in protected sectors efficiently, the temporary
sector un protect function is available. See “Temporary
Sect or/Sector Bloc k Unpr ote ct ”.
Sector protection and unprotection can be imple-
mented as follows.
Sect or pr ot ec tion a nd unprotection re qui res VID on th e
RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2
shows the algorithms and Figure 26 shows the timing
diagram. T his method us es standar d microprocess or
bus cycl e timing. For sector un protect, al l unprotec ted
sectors must first be protected prior to the first sector
unprotect write cycle.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is pro-
tected or unprotected. See the Autoselect Mode
section for details.
Write Prot ect (WP#)
The Write Protect function provides a hardware
method of protecting certain boot sectors without
using VID. This function is one of two pr ovided by the
WP#/ACC pin.
If the sy stem as s erts VIL on the WP #/A CC p in, the de-
vice disabl es program and erase func tions in the two
“outermost” 8 Kbyte boot sectors independently of
whether those sectors were protected or unpr otected
using the method described in “Sector/Sector Block
Protection and Unprotection”. The two outermost 8
Kbyte boot sectors are the two sectors containing the
lowest addresses in the bottom-boot-configured
device.
If the system asser ts VIH on the WP#/A CC pi n, the de-
vice reverts to whether the two outermost 8 Kbyte boot
secto rs were l ast set to be pro tected or unprote cted.
That is , sec tor prote cti on or unp ro tect ion fo r thes e tw o
sectors depends on whether they were last protected
or unprotected using the method described in “Sec-
tor/Sector Block Protection and Unprotection”.
Sector A20–A12 Sector/
Sector Block Size
SA0 000000XXX 64 Kbytes
SA1-SA3 000001XXX,
000010XXX
000011XXX 192 (3x64) Kbytes
SA4-SA7 0001XXXXX 256 (4x64) Kbytes
SA8-SA11 0010XXXXX 256 (4x64) Kbytes
SA12-SA15 0011XXXXX 256 (4x64) Kbytes
SA16-SA19 0100XXXXX 256 (4x64) Kbytes
SA20-SA23 0101XXXXX 256 (4x64) Kbytes
SA24-SA27 0110XXXXX 256 (4x64) Kbytes
SA28-SA31 0111XXXXX 256 (4x64) Kbytes
SA32-SA35 1000XXXXX 256 (4x64) Kbytes
SA36-SA39 1001XXXXX 256 (4x64) Kbytes
SA40-SA43 1010XXXXX 256 (4x64) Kbytes
SA44-SA47 1011XXXXX 256 (4x64) Kbytes
SA48-SA51 1100XXXXX 256 (4x64) Kbytes
SA52-SA55 1101XXXXX 256 (4x64) Kbytes
SA56-SA59 1110XXXXX 256 (4x64) Kbytes
SA60-SA62 111100XXX,
111101XXX,
111110XXX 192 (4x64) Kbytes
SA63 111111000 8 Kbytes
SA64 111111001 8 Kbytes
SA65 111111010 8 Kbytes
SA66 111111011 8 Kbytes
SA67 111111100 8 Kbytes
SA68 111111101 8 Kbytes
SA69 111111110 8 Kbytes
SA70 111111111 8 Kbytes
Sector A20–A12 Sector/
Sector Block Size
DS42553 17
Note that the WP#/ACC pin must not be left floating or
unconne cted; inc onsistent be havior of the de vice may
result.
Temporary Sector/Sector Block Unprotect
(Note: For the foll owing discussi on, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
7).
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Secto r Unpro tect mo de is ac tiva ted by setti ng the R E-
SET# pi n to VID (8.5 V – 12.5 V). During this mode,
formerly protected sectors can be programmed or
erased by sel ectin g t he se ctor addres ses. Onc e VID is
removed from the RESET# pin, all the previously pro-
tected sectors are protected again. Figure 1 shows the
algorithm, and Figure 25 s hows the timin g diagrams,
for this feature.
Figure 1. Temporary Sector Unprotect Operation
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL,
outermost boot sectors will remain protected).
2. All previous ly protected sectors are pr ote cte d once
again.
18 DS42553
Note: The term “sector” in the figure applies to both sectors and sector blocks.
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Data = 00h?
Last sector
verified?
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
DS42553 19
SecSi (Secured Silicon) Sector Flash
Memory Region
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 64 Kbytes in length, and
uses a SecSi Sector Indicator Bit to indica te whether
or not the SecSi Secto r is lock ed when shipped from
the factory. This bit is permanently set at the factory
and can not be chan ged, which pr events cl oning of a
factory locked part. This ensures th e security of the
ESN once the product is shipped to the field.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The fac-
tory -locke d vers ion is always prot ected wh en sh ippe d
from the factor y, and has the SecSi Sector Indicator
Bit permane ntly set to a “1.” The customer-lockable
version is shipped with the unprotected, allowing cus-
tomers to utilize the that sector in any manner they
choose. The cus tomer -lock able ver sion has th e Sec Si
Sector Indicator Bit permanently set to a “0.” Thus, the
SecSi Se ctor In dicator Bit pr events cu stomer-l ockabl e
devices from being used to replace devices that are
factory locked.
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Se cto r Comman d Sequen ce ”). Afte r the system
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the
addresses normally occupied by the boot sectors. This
mode of operation continues until the system issues
the Exit SecSi Sector command sequence, or until
power is removed from the devic e. On power-up, or
following a hardware reset, the device reverts to send-
ing commands to the boot sectors.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In a factory locked device, the SecSi Sector is pro-
tected when the device is shipped from the factory.
The Se cSi S ector ca nnot b e mod ified in any way. T he
device is available preprogrammed with a random, se-
cure ESN only
In devices that have an ESN, the Top Boot starting ad-
dres s of the E SN wil l be at the bot tom of the low est 8
Kbyte boot sector at addresses 1F8000h–1F8007h in
word mode (or addresses 3F00 00h–3F000Fh in byte
mode).
Customer Loc kable : Sec Si Se ctor NOT
Programmed or Protected At the Factory
If the securit y feature is not r equired, the SecSi Sector
can be treated as an addi tional F l a s h m e m o r y spa c e ,
ex p an d i ng t h e s iz e of the avail able Flas h array by 64
Kbytes. The SecSi Sector can be read, programmed,
and erased as often as required. Note that the acceler-
ated programming (ACC) and unlock byp ass functions
are n ot ava ilab le wh en pro gram ming t he SecS i Se ctor.
The SecS i Sector area can be prot ected using one of th e
followin g procedure s:
■Write the three-cycle Enter SecSi Sector Region
command sequ enc e, and the n fol low the in- s yste m
sector protect algorithm as shown in Figure 2, ex-
cept that RES ET# may be at either VIH or VID. This
allows in-system protection of the without raising
any device pin to a high voltage. Note that this
method is only applicable to the SecSi Sector.
■Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the alternate
method of sector protection described in the “Sec-
tor/Sector Block Protection and Unprotection”.
Once the SecS i Sec tor is l ocked an d ver ified, t he sys-
tem must write the Exit SecSi Sector Region
command sequence to return to reading and writing
the remainder of the array.
The SecSi Sector protection must be used with cau-
tion since, once protected, there is no procedure
availa ble for unprotec ting the SecSi Se ctor area an d
none of the bits in the SecSi Sect or memory spa ce
can be modified in any way.
Hardware Data Protection
The comm and seq uenc e requirem ent of unlo ck cy cl es
for programming or erasing provides data protection
against inadver tent writes (refer to Table 12 for com-
mand definitions). In a ddition, the following hardware
data protection measures pr event accidental erasure
or progr ammi ng, whic h might ot herwi se be caus ed by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
Low VCC Write Inhibit
When V CC is less than VLKO, th e device does not ac-
cept any write cycles. T his protects data during VCC
power-up and power-d own. The command register
and all internal program/erase circuits are disabled,
and the device r esets to reading array data. Subse-
quent writes are ignored until VCC is greater than VLKO.
The system must provide the proper signals to the
control pins to prevent unintentional writes when VCC
is greater than VLKO.
Write Pulse “Glitch” Prote c t io n
Nois e pulse s of les s than 5 n s (typ ical) on OE# , CE#f
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# f = VIH or WE# = VIH. To initiate a write cycle,
20 DS42553
CE#f and WE# must be a logical zer o while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE#f = V IL and OE# = V IH during power up,
the device does not accept com mands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interfac e (CFI) spec ification out-
lines dev ice and host s ystem software in terrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent , JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This devi c e en ters t he CF I Que ry mode when t he s y s-
tem writes the CFI Qu ery command , 98h, to ad dress
55h in word mode (or address AAh in byte mode), any
time the dev ice is ready to read arra y data. The sys-
tem can read CFI i nformation at the addresses given
in Tables 8–11. To terminate reading CFI data, the sys-
tem must write the reset command. The CFI Query
mode is not acc essible wh en the de vice i s execu ting
an Embedded Program or embedded erase algorithm.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the address es given in Tables 8–11. T he
system must write the reset command to return the de-
vice to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the
World Wide Web at http://www.amd.com/prod-
ucts/nvd/overview/cfi.html. Alternatively, contact an
AMD representative for copies of these documents.
Table 8. CFI Query Identification String
Addresses
(Word Mod e) Addresses
(Byte Mode) Data Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h Query Unique ASCII string “QRY”
13h
14h 26h
28h 0002h
0000h Primary OEM Command Set
15h
16h 2Ah
2Ch 0040h
0000h Address for Primary Extended Table
17h
18h 2Eh
30h 0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah 32h
34h 0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
DS42553 21
Table 9. System Interface String
Table 10. Device Geometry Definition
Addresses
(Word Mod e) Addresses
(Byte Mode) Data Description
1Bh 36h 0027h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 38h 0036h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs
20h 40h 0000h Typical tim eou t for Min. si ze buffer write 2N µs (00h = not supported)
21h 42h 000Ah Typical timeout per individual block erase 2N ms
22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 46h 0005h Max. timeout for byte/word write 2N times typical
24h 48h 0000h Max. timeout for buffer write 2N times typical
25h 4Ah 0004h Max. timeout per individual block erase 2N times typical
26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
Addresses
(Word Mod e) Addresses
(Byte Mode) Data Description
27h 4Eh 0015h Device Size = 2N byte
28h
29h 50h
52h 0002h
0000h Flash Device Interface des cri pti on (refer to CFI publication 100)
2Ah
2Bh 54h
56h 0000h
0000h Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch 58h 0002h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Regi on 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
001Eh
0000h
0000h
0001h
Erase Block Region 2 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
22 DS42553
Table 11. Primary Vendor-Specific Extended Query
Note:
The number of sectors in Bank 2 is device dependent, Am29DL323 = 30h.
Addresses
(Word Mod e) Addresses
(Byte Mode) Data Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 86h 0031h Major version number, ASCII
44h 88h 0031h Minor version number, ASCII
45h 8Ah 0000h Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Nu mber (Bits 7-2)
46h 8Ch 0002h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 8Eh 0001h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 90h 0001h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 92h 0004h Sector Protect/Unprotect scheme
04 = 29 LV800 mode
4Ah 94h 00XXh
(See Note) Simultaneous Operation
00 = Not Supported, X= Number of Sectors in Bank 2 (Uniform Bank)
4Bh 96h 0000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 98h 0000h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh 9Ah 0085h ACC (Acc eler ation) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh 9Ch 0095h ACC (Acceleration) Suppl y Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh 9Eh 000Xh Top/Bottom Boot Sector Flag
02h = Bottom Boot D evice, 03h = Top Boot D evice
DS42553 23
COM MAND DEF I N I T I ONS
Writing specifi c address and data commands or se-
quences into the command register initiates device
operations. Table 12 define s the valid r egister com-
mand sequences. Writing incorrect address and
data values or writing them in the improper se-
quence resets the device to reading array data.
All addresses are latched on the falling e dge of WE#
or CE#f , whiche ver ha ppens l ater. Al l data i s latche d
on the rising edge of WE# or CE#f, whichever hap-
pens first. Refer to the AC Characteristics secti on for
timing diagrams.
Reading Array Data
The devi ce is automati cally set to read ing array dat a
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read
data from any non-erase-suspended sector with in the
same bank. After completing a programming operation
in the Erase Suspend mode, the system may once
again read array data with the same exception. See
the Erase Suspend/Erase Resume Commands sec-
tion for more information.
The syste m must issu e the re set c omm and to r eturn a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the
next section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Flash Read-Only Operations table provides the
read parameters, and Figure 14 shows the timing
diagram.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cy cl es in an er as e co mm and s equ ence before
erasin g begin s. This rese ts the b ank to w hich t he sys-
tem w as writing to reading a rray data. O nce erasu re
begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
which the system was writing to reading array data. If
the program comm and sequence i s written to a bank
that is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-sus-
pend-read mode. Once programming begins,
however, the device i gnore s reset c omman ds unti l the
operation is complete.
The reset command may be written between the se-
quen ce cycles in an aut oselect comm and sequen ce.
Once in the autoselect mode, the reset command
must be written to return to reading array data. If a
bank entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns
that bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to read-
ing array data (or erase-suspend-read mode if that
bank was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to acce ss the manufac ture r and de vice codes ,
and determ ine whether or not a sector is p rotecte d.
Table 12 shows the address and data requirements.
The autoselect command sequence may be written to
an addr ess within a ba nk that is eithe r in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively pro-
gramming or erasing in the other bank.
The au tosele ct c omman d seq uence is initi ated b y fir st
writing two unlock cycles. This is followed by a third
write cy cle t hat c on tains the ba nk add ress an d the au-
toselect command. The bank then enters the
autoselect mode. The system may read at any ad-
dress within the same bank any number of times
without initiating another autoselect command
sequence:
■A read cycle at address (BA)XX00h (where BA is
the bank address) returns the manufacturer code.
■A read cycle at address (BA)XX01h in word mode
(or (BA)XX02h in byte mode) returns the device
code.
■A read c ycle to an a ddress co ntaining a sector ad-
dress ( SA) within the same bank , and the address
02h on A7–A0 in word mode (or the address 04h on
A6–A-1 in byte mode) returns 01h if the sector is
protected, or 00h if it is unprotected. (Refer to Ta-
bles 5–6 for valid secto r addre ss es ).
The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
24 DS42553
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The syste m c an a cc ess the S ec Si Se ct or regio n by is -
suin g the three- cycle Ente r SecSi S ector comm and
sequence. The device continues to access the SecS i
Sector region until the system issues the four-cycle
Exit SecSi Sector command sequence. The Exit SecSi
Sector command sequence returns the device to nor-
mal oper ation. Ta ble 12 shows the addr ess and da ta
requi remen ts f or both com mand seq uenc es. Se e al so
“SecSi (Secured Silicon) Sector Flash Memory Re-
gion” for further information. Note that a hardware
rese t (RESET# =VIL) will reset the device to reading
array data.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the CIOf pin. Programming
is a four-bus-cycle operation. The program command
sequence is initiated by writing two unlock write cy-
cles, follo wed by the progra m set-up c ommand . The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or
timings. The device automatically provides internally
generated program pulses and verifies the pro-
grammed cell margin. Table 12 shows the address
and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
that bank then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by
using DQ 7, DQ6, or RY/BY#. Refe r to the Write Oper -
ation Status sectio n for information on these status
bits.
Any commands written to the device during the Em-
bedded Progr am Algorithm are ignor ed. Note that a
hardware reset immediatel y terminates the program
operation. The program command sequence should
be reini tiated onc e that bank has ret urned to rea ding
array data, to ensure data integrity.
Programming is allowed in any sequenc e and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operation was success-
ful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to a bank faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is fo llowed by a third write
cycle containing the unlock bypass command, 20h.
That bank then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all tha t i s req ui re d to prog ra m i n t his m ode . T he firs t
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed i n the same manner. Th is mode dis penses
with the initial two un lock cycl es required in the s tan-
dard program command sequence, resulting in faster
total programming time. Table 12 shows the require-
ments for the command sequence.
During the unlo ck bypas s mode, only t he Unlock By-
pass Program and Unlock Bypass Reset commands
are valid . To exit th e unlock by pass mod e, the syste m
must issue the two-cycle unlock bypass reset com-
mand seq uenc e. T he fir st cy cl e m us t conta in the b ank
address and the data 90h . The second cycle need
only contai n the data 00h. The bank then returns to
the reading array data.
The device offers accelerated program operations
through the WP#/ACC pin. W hen the sy stem asse rts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock By pass prog ram comman d
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH any operation
other than accelerated program ming, or dev ice dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; i nconsistent behavior
of the device may result.
Figure 3 illus tr ates the al gor it hm for the pr og ra m oper-
ation. Refer to the Flash Erase and Program
Operations table in the AC Characteristics section for
parameters, and Figure 18 for timing diagrams.
DS42553 25
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
comman d sequence i s initia ted by writi ng two unlo ck
cycle s, followed by a se t-up comm and. Two additio nal
unlock write cycles are then followed by the chip erase
command, which in turn inv ok es th e E mb edde d E ras e
algorithm. The devic e does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to e lectrical
eras e. The syst em is no t requir ed to prov ide any con-
trols or timings during these operations. Table 12
shows the ad dres s and data r equir ement s for the chi p
erase command sequence.
When the Embedded Erase algorithm is complete,
that bank re turns to re ading arr ay data and add ress es
are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. Refer to the Write Operation Status
section for information on these status bits.
Any commands written during the chip erase operation
are ignored . However, note that a hardw are res et im-
mediately terminates the erase operation. If that
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 4 illus trates the algorithm for the erase opera-
tion. Refer to the Flash Erase and Program
Operations tables in the AC Characteristics section for
parameters, and Figure 20 section for timing
diagrams.
Sector Erase Command Sequence
Sector e rase is a six bus cycle op eration. T he sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. T wo ad-
ditional unlock cycles are written, and are then
followed by the address of the sector to be erased,
and the sector erase command. Table 12 shows the
address and data requirements for the sec tor erase
command sequence.
The device does not require the system to preprogram
prior to eras e. The Embed ded Erase alg orithm au to-
matically programs and verifies the entire memory for
an all zero data patter n prior to electri cal erase . The
system is not required to provi de any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than
50 µs , oth er wis e er asur e m ay beg in. Any se cto r er ase
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mend ed tha t pro cessor interr upts be di sable d durin g
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period rese ts that bank to reading array
data. The system must rewrite the command se-
quence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase T imer .). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Emb edde d Eras e al gor it hm is com pl ete, the
bank r eturns to read ing arr ay data an d add resses a re
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-eras ing bank. The system c an de-
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note: See Table 12 for program command sequence.
26 DS42553
Refer to the Wr ite Op eration Statu s secti on for infor-
mation on these sta tus bits.
Once the sect or erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. Howev er, note tha t a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once that bank has returned to
reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Flash Erase and Program
Operations tables in the AC Characteristics section for
parameters, and Figure 20 section for timing
diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data fro m, or prog r am data to , a ny s ector n ot se lec te d
for erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase oper ation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chi p erase operation or Embedded P rogram
algorithm.
When the Eras e Suspend comm and is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is writ-
ten during the sector erase time-out, the device
immediately terminates the time-out period and sus-
pends the erase operation.
After the erase operation has been suspended, the
bank ent ers the erase-suspend -read mode . The sys-
tem can r ead d ata from or prog ram d ata to a ny sec tor
not selected for erasure. (The device “erase sus-
pends” all sectors selected for er asure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The sys tem
can use DQ 7, or DQ 6 and DQ2 tog eth er, to determ ine
if a sect or is actively erasing or is erase-suspended.
Refer to the Wr ite Op eration Statu s secti on for infor-
mation on these sta tus bits.
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard Byte Program operation.
Refer to the Write Ope ration Stat us sectio n for more
information.
In the erase-su spend- rea d mode, the syst em can also
issue t he a uto sel ec t com mand sequ ence. Refer to th e
Autoselect Mode and Autoselect Command Sequence
sections for details .
To resume the sector erase operation, the system
must write the Erase Resume command. The bank
address of the erase-suspended bank is required
when writing this command. Further writes of the Re-
sume comm and ar e igno red. Anot her Er ase Su spen d
command can be written after the chip has resumed
erasing.
Figure 4. Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Table 12 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
DS42553 27
Table 12. DS42553 Command Definitions
Legend:
X = Don’t care
RA = Address of the memo r y loc at ion to be r ea d.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch o n th e fallin g ed ge of the WE # o r C E# f p ul se, whi che ver ha pp en s
later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE#f pulse, whichever happens first.
SA = Addr e ss of the sec tor to be ver if ied (in au t os elect mode) or
erased. Address bits A20–A12 uniquely selec t any sector.
BA = Addr e ss of th e b an k th at is being s wi tch ed to au tos el ect mo de , is
in bypass mode, or is being erased.
Notes:
1. See Tables 1 through 3 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5. Unless otherwise noted, address bits A20–A11 are don’t cares.
6. No unlock or command cycles required when bank is in read
mode.
7. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
9. The data is 80h for factory locked and 00h for not factory locked.
10. The data is 00h for an unprotected sector/sector block and 01h
for a protected sector/sector block.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. The Erase Resume command is valid only during the Erase
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autoselect (Note 8)
Manufacturer ID Word 4555 AA 2AA 55 (BA)555 90 (BA)X00 01
Byte AAA 555 (BA)AAA
Device ID Word 4555 AA 2AA 55 (BA)555 90 (BA)X01
Byte AAA 555 (BA)AAA (BA)X02
SecSi Sector Factory
Protect (Note 9) Word 4555 AA 2AA 55 (BA)555 90 (BA)X03 81/01
Byte AAA 555 (BA)AAA (BA)X06
Sector Protect Verify
(Note 10) Word 4555 AA 2AA 55 (BA)555 90 (SA)X02 00/01
Byte AAA 555 (BA)AAA (SA)X04
Enter SecSi Sector Region Word 3555 AA 2AA 55 555 88
Byte AAA 555 AAA
Exit SecSi Sector Region Word 4555 AA 2AA 55 555 90 XXX 00
Byte AAA 555 AAA
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 11) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 12) 2 BA 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 13) 1 BA B0
Erase Resume (Note 14) 1 BA 30
CFI Query (Note 15) Word 155 98
Byte AA
28 DS42553
WRITE OPERATION STATUS
The devi ce provid es severa l bits to deter mine the s ta-
tus of a progr am or er ase o peration: DQ2, DQ3, D Q5,
DQ6, and DQ7. Table 13 and the following subsec-
tions describe the function of these bits. DQ7 and DQ6
each offer a method for de termining whether a pro-
gram or erase operation is comp lete or in progress.
The device also provides a hardware-based output
signal, RY/BY#, to determine whether an Embedded
Program or Erase operation is in progress or has been
completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Program or Erase
algorith m is in progress or completed, or wheth er a
bank is in Erase Suspend. Data# Polling is valid after
the rising edge of the final WE# pulse in the command
sequence.
During the Em bedded Program al gorithm, the devic e
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must pro vide the program add re ss to read v al id sta tus
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is activ e for
approximately 1 µs, then that bank returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
prod uces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The syste m mu st pr ov ide an a ddr ess within a ny of th e
sectors selected for erasure to read valid status infor-
mation on DQ7.
After an erase command sequence is written, if all
sect ors s el ec ted for e rasi ng ar e p rotec ted, Data# Pol l-
ing on DQ7 is active for approximately 100 µs, then
the bank returns to reading array data. If no t all se-
lected sectors are protected, the Embedded Erase
algorit hm eras es the un pr ote cted s ec tor s, and ig nor es
the selected sectors that are protected. However , if the
system reads DQ 7 at an address within a pr otected
sector, the status may not be valid.
Just p rior to the com pleti on of an E mbed ded P rogram
or Eras e op erati on, D Q7 m ay c hang e a syn chro nously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid da ta, the da ta output s on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on su c-
cessive read cycles.
Table 13 sho ws the outpu ts for Data# P ollin g on DQ7.
Figure 5 sh ows the Data # Polli ng algo rithm . Figure 22
in the AC Characteristics section shows the Data#
Polling timing diagram.
Figure 5. Data# Polling Algorithm
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the se ctor being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
DS42553 29
RY/ B Y#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which in dicate s w he ther an E mbe dded Al gor ithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready) , the d evice i s readi ng ar ray data , the s tandby
mode, or one of the banks is in the erase-sus-
pend-read mode.
Table 13 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ 6 indicate s whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedd ed Progra m or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE#f to con t rol th e r ead cy c les. W hen the oper at ion is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for ap proxim ately 10 0 µs, then ret urns to readi ng
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-su sp ended. Wh en the devi ce is ac tively er asin g
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stop s toggling. Howe ve r, th e s yst em
must also use DQ2 to determine which sectors are
erasing o r er ase-s uspend ed. Alte rnat ive ly, the s ystem
can use DQ7 (see the subsection on DQ7: Data#
Polling).
If a program address falls within a p rotected sector,
DQ6 toggles for approximately 1 µs after the prog ram
command s equenc e is wri tten, then returns to readin g
array data.
DQ6 also toggles during the erase-suspe nd-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 13 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 23 in
the “AC Character istics” se ction sh ows the tog gle bit
timing diagrams. Figure 24 shows the differences be-
tween DQ 2 and DQ6 in gr aphical form. See also th e
subsection on DQ2: Toggle Bit II.
Figure 6. Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ 6 and DQ2 for
more information.
30 DS42553
DQ2: Toggle Bit II
The “Toggle B it II” on DQ2, whe n u sed wi th DQ6, indi-
cates whether a particula r sector is a ctively erasin g
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within tho se secto rs that have been selecte d for era-
sure. (The system may use either OE# or CE#f to
control the read cycles.) But DQ2 cannot distinguish
wheth er the sector is act ively er asing or is e rase- sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode infor mation. R efer to Table 13 t o compare o ut-
puts for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
form, an d t he se ction “DQ2: To ggle Bit II” expl ains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 23 shows the toggle bit timing diagram. Figure
24 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. W hen-
ever the system initially begins reading toggle bit
status, it must r ead DQ7–DQ0 at least twic e in a row
to determi ne whe ther a tog gle bit i s tog gling . Typ ic ally,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would comp are th e new va lue of th e toggl e bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read c ycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it i s, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopp ed toggling
just as DQ5 went high. If the tog gle bit is no long er
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not complet ed the oper ation su ccessf ully, and
the sys tem mus t writ e the rese t comma nd to ret urn to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may conti nue to monitor
the toggle bit and DQ 5 through successive re ad cy-
cles, determining the status as described in the
previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system
must star t at the be gi nning of the algo rithm when it r e-
turns to deter mine the st atus of the ope ration (top of
Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time
has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1,” indicating
that the prog ram or eras e cycle was not s uccessfully
completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” t o a l ocat ion t hat wa s pr evious ly pr o-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to reading array data (or
to the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After wri ting a sect or erase comm and sequen ce, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase tim er does not
apply to the chip erase command.) If additional
sectors are s elected for erasure, the entire time- out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the s ector era se comman d is writte n, the syste m
should re ad th e st atu s o f DQ7 (D ata# Poll ing) or DQ 6
(Togg le Bit I) to ensure that th e device has acce pted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embed ded Eras e algorith m has beg un; all fur-
ther c ommands ( except Erase Suspend) are ig nored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 13 s hows the stat us of DQ3 rel ative to the other
status bits.
DS42553 31
Table 13. Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When readi ng write ope ration statu s bits, the sys tem must alwa ys provide the bank addres s where the Embe dded Algorith m
is in progress. The device outputs array data if the system addresses a non-busy bank.
Status DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) RY/BY#
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggl e 0 1 Toggle 0
Erase
Suspend
Mode
Erase-Suspend-
Read
Erase
Suspended Sector 1 No t oggle 0 N/A Toggle 1
Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
32 DS42553
ABSOLUTE MAXIMUM RATINGS
Storage Te mpe ra tur e
Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . –25°C to +85°C
Voltage with Respect to Ground
VCCf/VCCs (Note 1) . . . . . . . . . . . .–0.3 V to +4.0 V
A9, OE#, and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V
All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 7. D u ring vo lta ge transitions, inpu t or I/O pins
may overs hoot to VCC +2.0 V for peri ods up to 20 ns. Se e
Figure 8.
2. Minimum DC input voltage on pins OE#, RESET#, and
WP#/ACC is –0.5 V. During voltage transitions, OE#,
WP#/ACC, and RESET# may oversho ot VSS to –2.0 V
for periods of up to 20 ns. See Figure 7. Maximum DC
input voltage on pin RESET# is +12.5 V which may
overshoot to +14 .0 V for period s up to 20 ns. Maximum
DC input voltage on WP#/ACC is +9.5 V which may
overshoo t to +12.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stres s rating only; fu nctiona l operati on of the dev ice at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Tempera ture (TA) . . . . . . . . .–25°C to +85°C
VCCf/VCCs Supply Voltage
VCCf/VCCs for standard voltage range. . 2.7 V to 3.3 V
Operati ng ranges defin e those limits bet ween which the func-
tionality of the device is guaranteed.
Figure 7. Maximum Negative
Overshoot Waveform Figure 8. Maximum Positive
Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
DS42553 33
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT RESET# Input Load Current VCC = VCC ma x ; RESET# = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIA ACC Input Leakage Current VCC = VCC max,
WP#/ACC = VACC max 35 µA
ICC1fFlash VCC Active Read Current
(Notes 1, 2)
CE#f = VIL, OE# = VIH,
Byte Mode 5 MHz 10 16
mA
1 MHz 2 4
CE#f = VIL, OE# = VIH,
Word Mode 5 MHz 10 16
1 MHz 2 4
ICC2fFlash VCC Active Write Current
(Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL 15 30 mA
ICC3fFlash V
CC Standby Current (N ote 2) VCCf = VCC max, CE#f, RESET#,
WP#/ACC = VCCf ± 0.3 V 0.2 5 µA
ICC4fFlash V
CC Reset Current (Note 2) VCCf = VCC max, RESET# = VSS ±
0.3 V, WP#/ACC = VCCf ± 0.3 V 0.2 5 µA
ICC5fFlash VCC Current Automatic Sleep
Mode (Notes 2, 4) VCCf = VCC max, VIH = VCC ± 0.3 V ;
VIL = VSS ± 0.3 V 0.2 5 µA
ICC6fFlash VCC Active
Read-Whi le-Program Cu rrent (Notes
1, 2) CE#f = VIL, OE# = VIH
Byte 21 45 mA
Word 21 45
ICC7fFlash VCC Active Read-While-Erase
Current (Notes 1, 2) CE#f = VIL, OE# = VIH Byte 21 45 mA
Word 21 45
ICC8fFlash VCC Active
Program-While-Erase-Suspended
Current (Notes 2, 5) CE#f = VIL, OE#f = VIH 17 35 mA
IACC ACC Accelerated Program Current,
Word or By te CE#f = VIL, OE# = VIH ACC pin 5 10 mA
VCC pin 15 30 mA
ICC1sSRAM V
CC Active Current VCCs = VCC max,
CE1#s = VIL,
CE2s = VIH
10 MHz 45 mA
ICC2sSRAM V
CC Active Current CE1#s = 0. 2 V,
CE2s = VCCs – 0.2V 10 MHz 45 mA
1 MHz 5
ICC3sSRAM V
CC Standby Current 1) CE1#s = VIH, CE2s = VIH
2) CE2s = V IL 0.3 mA
ICC4sSRAM V
CC Standby Current CE1#s ≥ VCCs – 0.2V, CE2s ≥
VCCs – 0.2V 12 µA
ICC5sSRAM V
CC Standby Current CE2s ≤ 0.2V 12 µA
VIL Input Low Voltage –0.2 0.8 V
VIH Input High Voltage 2.4 VCC + 0.2 V
34 DS42553
Notes:
1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. T ypical sleep mode current is
200 nA.
5. Not 100% tested.
VHH
Voltage for WP#/ACC Program
Acceleration and Sector
Protection/Unprotection 8.5 9.5 V
VID
Voltage for Sector Protection,
Autoselect and Temporary Sector
Unprotect 8.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCCf = VCCs =
VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCCf = VCCs =
VCC min 0.85 x
VCC V
VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4
VLKO Flash Low VCC Lock-Out Voltage
(Note 5) 2.3 2.5 V
SRAM DC AND OPERATIN G CHARACTERISTICS
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
ILI Input Leakage Current VIN = VSS to VCC –1.0 1.0 µA
ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# =
VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA
ICC Operating Power Supply Current IIO = 0 mA, CE1#s = VIL, CE2s =
WE# = VIH, VIN = VIH or VIL 3mA
ICC1s Average Operating Current
Cycle time = 1 µs, 100% duty,
IIO = 0 mA, CE1#s ≤ 0.2 V,
CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
5mA
ICC2s Average Operating Current Cycle time = Min., IIO = 0 mA,
100% duty, CE1#s = VIL, CE2s =
VIH, VIN = VIL = or VIH
45 mA
VOL Output Low Voltage IOL = 2.1 mA 0.4 V
VOH Out put High Voltage IOH = –1.0 mA 2.4 V
ISB Standby Current (TTL) CE1#s = VIH, CE2 = VIL, Other
inputs = VIH or VIL 0.3 mA
ISB1 Standby Current (CMOS)
CE1#s ≥ VCC – 0. 2 V, CE2 ≥ VCC –
0.2 V (CE1#s controlled) or CE2 ≤
0.2 V (CE2s controlled), CIOs =
VSS or VCC, Other input = 0 ~ VCC
12 µA
DC CHARACTERISTICS (Continued)
CMOS Compatible
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
DS42553 35
DC CHARACTERISTICS
Zero-Power Flash
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
25
20
15
10
5
00 500 1000 1500 2000 2500 3000 3500 4000
Supply Current in mA
Time in ns
10
8
2
0
1 2345
Frequency in MHz
Supply Current in mA
Note: T = 25 °CFigure 10. Typical ICC1 vs. Frequency
2.7 V
3.3 V
4
6
12
36 DS42553
TEST CONDITIONS Table 14. Test Specifications
KEY TO SWITCHING WAVEFORMS
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Test
Test Condition 90 ns Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacitance) 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement reference
levels 1.5 V
Output timing measurement
reference levels 1.5 V
KS000010-PAL
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput
Figure 12. Input Waveforms and Measurement Levels
DS42553 37
AC CHARACTERISTICS
SRAM CE#s Timing
Figure 13. Timing Diagram for Alternating Between SRAM to Flash
Parameter
Description Test Setup Speed Unit
JEDEC Std 90
—tCCR CE#s Recover Time —Min 0 ns
E#f
tCCR tCCR
E1#s
E2s tCCR tCCR
38 DS42553
AC CHARACTERISTICS
Flash Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 1 1 and Table 14 for test specifications.
Parameter
Description Test Setup 90 ns Speed Unit
JEDEC Std Min Max
tAVAV tRC Read Cycle Time (Note 1) 90 ns
tAVQV tACC Address to Output Delay CE#f, OE# = VIL 90 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL 90 ns
tGLQV tOE Output Enable to Output D ela y 40 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) 16 ns
tGHQZ tDF Output Enable to Output High Z (Note 1) 16 ns
tAXQX tOH Output Hold Time From Addresses, CE#f or OE#,
Whichever Occurs First 0ns
tOEH Output Enable Hold T ime
(Not e 1)
Read 0 ns
Toggle and
Data# Polling 10 ns
tOH
tCE
Outputs
WE#
Addresses
CE#f
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tRH
tOE
tRH
0 V
RY/BY#
RESET#
tDF
Figure 14. Read Operation Timings
DS42553 39
AC CHARACTERISTICS
Hardware Reset (RESET# )
Note: Not 100% tested.
Parameter Description 90 ns Unit
JEDEC Std
tReady RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note) Max 20 µs
tReady RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH Reset High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
t
Ready
CE#f, OE#
t
RH
CE#f, OE#
Reset Timings during Embedded Algorithms
RESET#
t
RP
t
RB
Figure 15. Reset Timings
40 DS42553
AC CHARACTERISTICS
Flash Word/Byte Configuration (CIOf)
Parameter 90 ns Speed
JEDEC Std Description Min Typ Max Unit
tELFL/tELFH CE#f to CIOf Switching Low or High 5 ns
tFLQZ CIOf Switching Low to Output HIGH Z 30 ns
tFHQV CIOf Switching High to Output Active 90 ns
DQ15
Output
Data Output
(DQ0–DQ7)
CE#f
OE#
CIOf
tELFL
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFLQZ
CIOf
Switching
from word
to byte
mode
DQ15
Output
Data Output
(DQ0–DQ7)
CIOf
tELFH
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
tFHQV
CIOf
Switching
from byte
to word
mode
Figure 16. CIOf Timings for Read Operations
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 17. CIOf Timings for Write Operations
CE#f
WE#
CIOf
The falling edge of the last WE# signal
tHOLD (tAH)
tSET
(tAS)
DS42553 41
AC CHARACTERISTICS
Flash Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
Parameter 90 ns Speed Unit
JEDEC Std Description Min Typ Max
tAVAV tWC Write Cycle Time (Note 1) 90 ns
tAVWL tAS Address Setup Time (WE# to Address) 0 ns
tASO Address Setup Time to OE# or CE#f Low During Toggle Bit
Polling 15 ns
tWLAX tAH Address Hold Time (WE# to Address) 45 ns
tAHT Address Hold Time From CE#f or OE# High Duri ng Toggle Bit
Polling 0ns
tDVWH tDS Data Setup Time 45 ns
tWHDX tDH Data Hold Time 0 ns
tOEH OE# Hold Time Read 0 ns
Toggle and Data# Polling 10 ns
tOEPH Output Enable High During Toggle Bit Polling 20 20 20 ns
tGHEL tGHEL Read Recovery Time Before Write (OE# High to CE#f Low) 0 ns
tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) 0 ns
tWLEL tWS WE# Setup Time (CE#f to WE#) 0 ns
tELWL tCS CE#f Setup Time (WE# to CE#f) 0 ns
tEHWH tWH WE# Hold Time (CE#f to WE#) 0 ns
tWHEH tCH CE#f Hold Time (CE#f to WE#) 0 ns
tWLWH tWP Write Pulse Wi dth 35 ns
tELEH tCP CE#f Pulse Width 35 ns
tWHDL tWPH Write Pulse Width High 30 ns
tSR/W Latency Between Read and Write Operations 0 ns
tWHWH1 tWHWH1 Progra mmin g Ope rati on (Note 2) Byte 5 µs
Word 7
tWHWH1 tWHWH1 Accelerated Programming Operation,
Word or Byte (Note 2) 4µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) 0.7 sec
tVCS VCCf Setup Time (N ote 1) 50 µs
tRB Write Recovery Time From RY/BY# 0 ns
tBUSY Program/Erase Valid To RY/BY# Delay 90 ns
42 DS42553
AC CHARACTERISTICS
Figure 19. Accelerated Program Timing Diagram
OE#
WE#
CE#f
VCCf
Data
Addresses
tDS
tAH
tDH
tWP
PD
tWHWH1
tWC tAS
tWPH
tVCS
555h PA PA
Read Status Data (last two cycles)
A0h
tGHWL
tCS
Status DOUT
Program Command Sequence (last two cycles)
RY/BY#
tRB
tBUSY
tCH
PA
otes:
. PA = program address, PD = program data, DOUT is the true data at the program address.
. Illus tr ation shows device in word mode.
Figure 18. Program Operation Timings
WP#/ACC tVHH
VHH
VIL or VIH VIL or VIH
tVHH
DS42553 43
AC CHARACTERISTICS
OE#
CE#f
Addresses
VCCf
WE#
Data
2AAh SA
tGHWL
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
tRB
tBUSY
otes:
. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
. These waveforms are for the word mode.
Figure 20. Chip/Sector Erase Operation Timings
44 DS42553
AC CHARACTERISTICS
OE#
WE#
Addresses
tOH
Data
Valid
In Valid
In
Valid PA Valid RA
tWC
tWPH
tAH
tWP
tDS tDH
tRC
tCE
Valid
Out
tOE
tACC
tOEH tGHWL
tDF
Valid
In
CE#f Controlled Write CyclesWE# Controlled Write Cycle
Valid PA Valid PA
tCP
tCPH
tWC tWC
Read Cycle
tSR/W
CE#f
Figure 21. Back-to-back Read/Write Cycle Timings
WE#
CE#f
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
RY/BY#
tBUSY
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycl e.
Figure 22. Data# Polling Timings (During Embedde d Algorithms)
DS42553 45
AC CHARACTERISTICS
OE#
WE#
Addresses
tOEH
tDH
tAHT
tASO
tOEPH
tOE
Valid Data
(first read) (second read) (stops toggling)
tCEPH
tAHT
tAS
DQ6/DQ2 Valid Data
Valid
Status Valid
Status Valid
Status
RY/BY#
CE#f
Note: V A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle
Figure 23. Toggle Bit Timings (During Embedded Algorithms)
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Figure 24. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
46 DS42553
AC CHARACTERISTICS
Temporary Sector/Sector Block Unprotect
Note: Not 100% tested.
Parameter 90 ns Speed Unit
JEDEC Std Description
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tVHH VHH Rise and Fall Time (See Note) Min 250 ns
tRSP RESET# Setup Time for Temporary
Sector/Sec tor Bloc k Unprotec t Min 4 µs
tRRB RESET# Hold Time from RY/BY# High for
Temporary Sector /Sector Block Unprotect Min 4 µs
RESET#
tVIDR
VID
VSS, VIL,
or VIH
VID
VSS, VIL,
or VIH
CE#f
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
tRRB
Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram
DS42553 47
AC CHARACTERISTICS
Sector/Sector Block Protect: 150 µs,
Sector/Sector Block Unprotect: 15 ms
1 µs
RESET#
SA, A6,
A1, A0
Data
CE#f
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector/Sector Block Protect or Unprotect Verify
VID
VIH
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 26. Sector/Sector Block Protect and Unprotect T iming Diagram
48 DS42553
AC CHARACTERISTICS
Alternate CE#f Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
Parameter 90 ns Speed
JEDEC Std Description Min Typ Max Unit
tAVAV tWC Write Cycle Time (Note 1) 90 ns
tAVWL tAS Address Setup Time (WE# to Address) 0 ns
tASO Address Setup Time to CE#f Low During Toggle
Bit Polling 15 ns
tELAX tAH Address Hold Time 45 ns
tAHT Address Ho ld tim e from CE#f or OE # High During
Toggle Bit Polling 0ns
tDVEH tDS Data Setup Time 45 ns
tEHDX tDH Da t a Hold Time 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# High to WE# Low) 0ns
tWLEL tWS WE# Setup Time 0 ns
tEHWH tWH WE# Hold Time 0 ns
tELEH tCP CE#f Puls e Width 35 ns
tEHEL tCPH CE#f Pulse Width High 35 ns
tWHWH1 tWHWH1 Programming Operation
(Note 2) Byte 5 µs
Word 7
tWHWH1 tWHWH1 Accelerated Programming Operation,
Word or Byte (Note 2) 4µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) 0.7 sec
DS42553 49
AC CHARACTERISTICS
t
GHEL
t
WS
OE#
CE#f
WE#
RESET#
t
DS
Data
t
AH
Addresses
t
DH
t
CP
DQ7# D
OUT
t
WC
t
AS
t
CPH
PA
Data# Polling
A0 for program
55 for erase
t
RH
t
WHWH1 or 2
RY/BY#
t
WH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SA for sector erase
555 for chip erase
t
BUSY
Notes:
1. Figure indi cates last two bus cycles of a program or erase operation.
2. P A = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings
50 DS42553
AC CHARACTERISTICS
SRAM Read Cycle
Note: CE1#s = OE# = VIL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL
Figure 28. SRAM Read Cycle—Addre ss Co ntrol led
Parameter
Symbol Description Min Max Unit
tRC Re ad Cyc le Time 85 ns
tAA Address Access Time 85 n s
tCO1, tCO2 Chip Enab le to Out put 85 ns
tOE Output Enable Access Time 45 ns
tBA LB#s, UB#s to Valid Output 85 ns
tLZ1, tLZ2 Chip Enable (CE1#s Low and CE2s High) to Low-Z Output 10 ns
tBLZ UB#, LB# Enable to Low-Z Output 10 ns
tOLZ Output Enable to Low-Z Output 5 ns
tHZ1, tHZ2 Chip dis ab le to Hi gh-Z Outpu t 0 25 ns
tBHZ UB#s, LB#s Disable to High-Z Output 0 25 ns
tOHZ Output Disable to High-Z Output 0 25 ns
tOH Output Data Hold from Address Change 15 ns
ddress
ata Out Previous Data Valid Data Valid
tAA
tRC
tOH
DS42553 51
AC CHARACTERISTICS
Figure 29. SRAM Read Cycle
Notes:
1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing.
2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device
interconnection.
Data Valid
High-Z
tRC
CS#1
Address
UB#, LB#
OE#
Data Out
tOH
tAA
tCO1
tBA
tOE
tOLZ
tBLZ
tLZ
tOHZ
tBHZ
tHZ
CS2 tCO2
52 DS42553
AC CHARACTERISTICS
SRAM Write Cycle
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write. Figure 30. SRAM Write Cycle—WE# Control
Parameter
Symbol Description Min Max Unit
tWC Write Cycle Time 85 ns
tCw Chip Enable to End of Write 70 ns
tAS Address Setup Time 0 ns
tAW Address Valid to End of Write 70 ns
tBW UB#s, LB#s to End of Write 70 ns
tWP Write Pulse Time 60 ns
tWR Write Recove ry Time 0 ns
tWHZ Write to Output High-Z 0 25 ns
tDW Data to Write Time Overlap 35 ns
tDH Data Hold from Write Time 0 ns
tOW End Write to Output Low-Z 5 ns
Address
CS1#s
Data Undefined
UB#s, LB#s
WE#
Data In
Data Out
t
WC
t
CW
(See Note 1)
t
AW
High-Z High-Z
Data Valid
CS2s t
CW
(See Note 1)
t
BW
t
WP
(See Note 4)
t
AS
(See Note 3)
t
WR
(See Note 2)
t
BW
t
DW
t
DH
t
OW
DS42553 53
AC CHARACTERISTICS
Notes:
1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write. Figure 31. SRAM Write Cycle—CE1#s Control
Address
Data Valid
UB#s, LB#s
WE#
Data In
Data Out High-Z High-Z
t
WC
CE1#s
CE2s
t
AW
t
AS
(See Note 2 )
t
BW
t
CW
(See Note 3) t
WR
(See Note 4)
t
WP
(See Note 5)
t
DW
t
DH
54 DS42553
AC CHARACTERISTICS
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write. Figure 32. SRAM Write Cycle—UB#s and LB#s Control
Address
Data Valid
UB#s, LB#s
WE#
Data In
Data Out High-Z High-Z
t
WC
CE1#s
CE2s
t
AW
t
BW
t
DW
t
DH
t
WR
(See Note 3)
t
AS
(See Note 4)
t
CW
(See Note 2)
t
CW
(See Note 2)
t
WP
(See Note 5)
DS42553 55
Flash Erase And Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,0 00 cy cl es. Additiona lly,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V , 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
12 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
FLASH LATCHUP CHARACTERISTICS
Note: Inclu des all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Note: 7.Te st conditions TA = 25 °C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.7 15 sec Excludes 00h program ming
prior to erasure (Note 4)
Chip Erase Time 49 sec
Byte Program Time 5 150 µs
Excl ude s sy stem level
overhead (Note 5)
Word Program Time 7 210 µs
Accelerated Byte/Word Program Time 4 120 µs
Chip P rogram Time
(Note 3) Byte Mode 21 63 sec
W ord Mo de 14 42
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including OE#, and RESET#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 11 14 pF
COUT Output Capa cit anc e VOUT = 0 12 16 pF
CIN2 Control Pin Capacitance VIN = 0 14 16 pF
CIN3 WP#/ACC Pin Capacitance VIN = 0 17 20 pF
Parameter Description Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C10Years
125°C20Years
56 DS42553
SRAM DATA RETENTION
Note: CE1#s ≥ VCC – 0.2 V, CE2s ≥ VCC – 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled), CIOs = VSS or VCC.
Figure 33. CE1#s Controlled Data Retention Mode
Figure 34. CE2s Controlled Data Retention Mode
Parameter
Symbol Parameter Description Test Setup Min Typ Max Unit
VDR VCC for Data Retention CS1#s ≥ VCC – 0.2 V (See Note) 1.5 3.3 V
VDH Data Retention Current VCC = 1. 5 V, CE1#s ≥ VCC – 0.2 V
(See Note) 0.5 5 µA
tSDR Data Retention Set-Up Ti me See data retention waveforms 0ns
tRDR Recove ry Time tRC ns
V
DR
V
CC
2.7V
2.2V
CE1#s
GND
Data Retention Mode
CE1#s
≥
V
CC
-
0.2 V
t
SDR
t
RDR
V
CC
2.7 V
0.4 V
V
DR
CE2s
GND
Data Retention Mode
t
SDR
t
RDR
CE2s £ 0.2 V
57 DS42553
PHYSICAL DIMENSIONS
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11 mm
DS42553 58
REVISION SUMMARY
Revision A (October 9, 2000)
Initial release as Preliminary Draft.
Revision B (March 8, 2001)
Global
Deleted Preliminary status from document. Added
table of contents.
Flash Memory Block Diagram
Added OE# and BYTE# inp uts to low er bank sec ti on.
Table 7, Top Boot Sector/Sector Block Addresses
for Protection/Unprotection
Corrected SA3 addess range to 000011XXX.
Sector/Sector Block Protection/Unprotection
Adde d to seco nd para grap h: “No te th at t he s ecto r un-
protect algorithm unprotects all sectors in parallel. All
previously protected sectors must be individually
re-protected. To change data in protected sectors effi-
ciently, the temporary sector unprotect function is
available. See “Temporary Sector/Sector Block
Unprotect”.”
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
Added to en d of f irst parag raph: “Note that the acceler-
ated programming (ACC) and unlock byp ass functions
are n ot ava ilab le wh en pro gram ming t he SecS i Se ctor.”
Common Flash Memory Interface (CFI)
Added to second paragraph: “T he CFI Q uery mo de is
not accessible when the device is executing an Em-
bedded Program or embedded erase algorithm.”
Command Definitions
Table 12 , Comman d Definiti ons: The SecSi Sector In-
dicator Bit values have changed from 80h and 00h to
81h and 01h, respectively.
Revision B+1 (March 15, 2001)
Added “Am29DL323D Top Boot” to the product de-
scription on the top portion of the first page.
‘
Trademarks
Copyright © 2001 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Device s, Inc.
ExpressFlash is a trademark of Advan ced Micro Devices , Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
