74HC/HCTO2 ssi QUAD 2-INPUT NOR GATE FEATURES TYPICAL @ Output capability: standard SYMBOL PARAMETER CONDITIONS UNIT Icc category: SSI HC HCT tpHL/ propagation delay Cy = 15 pF : GENERAL DESCRIPTION tPLH nA, nB tonY Veo=5V 7 9 ns The 74HC/HCTQ2 are high-speed Si-gate CMOS devices and are pin cy input capacitance 3.5 3.5 pF compatible with low power Schottky TTL (LSTTL). They are specified in Cpp power dissipation notes 1 and 2 22 24 pF compliance with JEDEC standard no. 7A. capacitance per gate The 74HC/HCTO2 provide the 2-input NOR function. GND = 0 V; Tamb = 25 C: ty = tf = 6 ns Notes 1, CPp is used to determine the dynamic power dissipation (Po in wW): Pp = Cpp x Vcc? x fi + = (CL x Vcc? x fo) where: f; = input frequency in MHz CL = output load capacitance in pF fo = output frequency in MHz Vcc = supply voltage in V LICL x Voc? x fg) = sum of outputs 2. For HC the condition is Vj = GND to Vcc For HCT the condition is V] = GND to Vcc 1.5 V PACKAGE OUTLINES SEE PACKAGE INFORMATION SECTION PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 4, 10, 13 TY to 4 data outputs 2,5, 8, 11 1Ato 4A data inputs 3, 6,9, 12 1B to 48 data inputs 7 GND ground (0 V) 14 Vee positive supply voltage wr] U [14] Yeo raz] [13] av r8 [3 | 12] 4B avfe] o2 [ules 2a fe] ia] a 2a fe] [9] 38 eno [7 | [a] 34 7287402.1 Fig. 1 Pin configuration. 2 a] 7 4] Bt 4 3 a & a 10 9 B10 St 2 KI 7287403.1 7z909771 Fig. 2. Logic symbol. Fig. 3 IEC logic symbol. December 1990PC74HC/HCT02 SSI 92874031 Fig. 4 Functional diagram. Y 7z90087 Fig. 5 Logic diagram (one gate). DC CHARACTERISTICS FOR 74HC FUNCTION TABLE INPUTS OUTPUT nA nB ny L L H L H L H L L H H L H = HIGH voltage jevel L = LOW voitage level For the DC characteristics see chapter HCMOS family characteristics, section Family specifications, Output capability: standard icc category: SSI AC CHARACTERISTICS FOR 74HC GND =O V: tp =t =6ns; Cy = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Voc | WAVEFORMS +25 -40 to +85 | 40 to +125 Vv min.) typ. | max. | min. | max. | min. | max. . 0 1 135 2.0 PHL! propagation delay e 8 a 27 | ns 45 | Fig 6 PLH nA, nB tony 7 | 15 20 23 6.0 wy! 19 | 75 95 110 2.0 THL output transition time 7 15 19 22 ns 4.5 Fig. 6 TLH 6 | 13 16 19 6.0 112 January 1986Quad 2-input NOR gate 74HC/HCTO2 Ss DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics, section Family specifications, Output capability: standard lec category: SSI Note to HCT types The value of additional quiescent supply current (Alec) for a unit load of 1 is given in the family specifications. To determine Alcc per input, multiply this value by the unit ioad coefficient shown in the table below. UNIT LOAD INPUT | COEFFICIENT nA, 18 1.50 AC CHARACTERISTICS FOR 74HCT GNO = 0 V; ty = ty = 6 a8; CL = 50 pF Tamb (C) | TEST CONDITIONS 74HCT | UNIT! Voc] WAVEFORMS +25 -40 to +85 | 40 to +125 v | SYMBOL | PARAMETER min. wy. max.} min.| max. | min. | max. i tPHL/ propagation delay 1 24 | 45 Fig, (LH nA, nB to n 19 29 | ns 5 Fig. 6 TH L/ output transition time 7 15 19 22 ns 4.5 Fig. 6 TLH January 1986 11374HC/HCTO2 SSI AC WAVEFORMS 48,98 INPUT ny OUTPUT F2asags Fig, 6 Waveforms showing the input (nA, n@) to output (nV) propagation delays and the output Note to AC waveforms transition times. (1} HC: Vay = 50%; Vj = GND to Vcc. HCT: Vy 2 1.3V: V1, =GNDito3V. 114 January 1986