LTC3703
1
3703fc
Typical applicaTion
FeaTures
applicaTions
DescripTion
100V Synchronous
Switching Regulator
Controller
The LT C
®
3703 is a synchronous step-down switching
regulator controller that can directly step down voltages
from up to 100V, making it ideal for telecom and automo-
tive applications. The LTC3703 drives external N-channel
MOSFETs using a constant frequency (up to 600kHz),
voltage mode architecture.
A precise internal reference provides 1% DC accuracy.
A high bandwidth error amplifier and patented line feed-
forward compensation provide very fast line and load
transient response. Strong 1Ω gate drivers allow the
LTC3703 to drive multiple MOSFETs for higher current ap-
plications. The operating frequency is user programmable
from 100kHz to 600kHz and can also be synchronized to
an external clock for noise-sensitive applications. Cur-
rent limit is programmable with an external resistor and
utilizes the voltage drop across the synchronous MOSFET
to eliminate the need for a current sense resistor. For ap-
plications requiring up to 60V operation with logic-level
MOSFETS, refer to the LTC3703-5 data sheet.
n High Voltage Operation: Up to 100V
n Large 1Ω Gate Drivers
n No Current Sense Resistor Required
n Step-Up or Step-Down DC/DC Converter
n Dual N-Channel MOSFET Synchronous Drive
n Excellent Line and Load Transient Response
n Programmable Constant Frequency: 100kHz to
600kHz
n ±1% Reference Accuracy
n Synchronizable up to 600kHz
n Selectable Pulse-Skip Mode Operation
n Low Shutdown Current: 50µA Typ
n Programmable Current Limit
n Undervoltage Lockout
n Programmable Soft-Start
n 16-Pin Narrow SSOP and 28-Pin SSOP Packages
n 48V Telecom and Base Station Power Supplies
n Networking Equipment, Servers
n Automotive and Industrial Control PARAMETER LTC3703-5 LTC3703
Maximum VIN 60V 100V
MOSFET Gate Drive 4.5V to 15V 9.3V to 15V
VCC UV+3.7V 8.7V
VCC UV–3.1V 6.2V
LTC3703
MODE/SYNC
fSET
COMP
FB
IMAX
INV
RUN/SS
GND
VIN
BOOST
TG
SW
VCC
DRVCC
BG
BGRTN
68µF
1000pF
2200pF
10k
100Ω 113k
1%
8.06k
1% 10Ω
15k
30k
0.1µF
VIN
15V TO 100V
Si7456DP
8µH
MBR1100
VOUT
12V
5A
270µF
16V
BAS19
VCC
9.3V TO 15V
0.1µF
3703 F01
10µF
1µF
+
+
+
Si7456DP
22µF
25V
470pF
LOAD (A)
0
EFFICIENCY (%)
100
95
90
85
80 4
3703 F01b
1235
VIN = 25V
VIN = 50V
VIN = 75V
Figure 1. High Efficiency High Voltage Step-Down Converter
Efficiency vs Load Current
L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and
ThinSOT and No RSENSE are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents, including 5408150,
5055767, 6677210, 5847554, 5481178, 6304066, 6580258.
LTC3703
2
3703fc
absoluTe MaxiMuM raTings
Supply Voltages
VCC, DRVCC .......................................... –0.3V to 15V
(DRVCC – BGRTN), (BOOST – SW) ....... –0.3V to 15V
BOOST ................................................. –0.3V to 115V
BGRTN ....................................................... –5V to 0V
VIN Voltage .............................................. –0.3V to 100V
SW Voltage (Note 10).................................. –1V to 100V
RUN/SS Voltage .......................................... –0.3V to 5V
MODE/SYNC, INV Voltages ....................... –0.3V to 15V
fSET, FB, IMAX Voltages................................ –0.3V to 3V
(Note 1)
TOP VIEW
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE/SYNC
fSET
COMP
FB
IMAX
INV
RUN/SS
GND
VIN
B00ST
TG
SW
VCC
DRVCC
BG
BGRTN
TJMAX = 150°C, θJA = 110°C/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BOOST
TG
SW
NC
NC
NC
NC
VCC
DRVCC
BG
NC
NC
NC
BGRTN
VIN
NC
NC
NC
NC
MODE/SYNC
fSET
COMP
FB
IMAX
INV
NC
RUN/SS
GND
TJMAX = 125°C, θJA = 100°C/W
pin conFiguraTion
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3703EGN#PBF LTC3703EGN#TRPBF 3703 16-Lead Narrow Plastic SSOP –40°C to 85°C
LTC3703IGN#PBF LTC3703IGN#TRPBF 3703I 16-Lead Narrow Plastic SSOP –40°C to 125°C
LTC3703HGN#PBF LTC3703HGN#TRPBF 3703H 16-Lead Narrow Plastic SSOP –40°C to 150°C
LTC3703EG#PBF LTC3703EG#TRPBF LTC3703EG 28-Lead Plastic SSOP –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3703EGN LTC3703EGN#TR 3703 16-Lead Narrow Plastic SSOP –40°C to 85°C
LTC3703IGN LTC3703IGN#TR 3703I 16-Lead Narrow Plastic SSOP –40°C to 125°C
LTC3703HGN LTC3703HGN#TR 3703H 16-Lead Narrow Plastic SSOP –40°C to 150°C
LTC3703EG LTC3703EG#TR LTC3703EG 28-Lead Plastic SSOP –40°C to 85°C
Consult LT C Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Peak Output Current <10µs BG,TG ..............................5A
Operating Temperature Range (Note 2)
LTC3703E ............................................–40°C to 85°C
LTC3703I ........................................... –40°C to 125°C
LTC3703H (Note 9) ............................ –40°C to 150°C
Junction Temperature (Notes 3, 7)
LTC3703E, LTC3703I ........................................ 125°C
LTC3703H (Note 9) ........................................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.) ..................300°C
LTC3703
3
3703fc
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = VBOOST = VIN = 10V, VMODE/SYNC = VINV = VSW =
BGRTN = 0V, RUN/SS = IMAX = open, RSET = 25k, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC, DRVCC VCC, DRVCC Supply Voltage l9.3 15 V
VIN VIN Pin Voltage l100 V
ICC VCC Supply Current VFB = 0V
RUN/SS = 0V
l1.7
50
2.5 mA
µA
IDRVCC DRVCC Supply Current (Note 5)
RUN/SS = 0V
0
0
5
5
µA
µA
IBOOST BOOST Supply Current (Note 5) TJ ≤ 125°C
TJ > 125°C
RUN/SS = 0V
l
l
360
360
0
500
800
5
µA
µA
µA
Main Control Loop
VFB Feedback Voltage (Note 4)
l
0.792
0.788
0.800 0.808
0.812
V
V
∆VFB(LINE) Feedback Voltage Line Regulation 9V < VCC < 15V (Note 4) l 0.007 0.05 %/V
∆VFB(LOAD) Feedback Voltage Load Regulation 1V < VCOMP < 2V (Note 4) l0.01 0.1 %
VMODE/SYNC MODE/SYNC Threshold MODE/SYNC Rising 0.75 0.81 0.87 V
∆VMODE/SYNC MODE/SYNC Hysteresis 20 mV
IMODE/SYNC MODE/SYNC Current 0 ≤ VMODE/SYNC ≤ 15V 0 1 µA
VINV Invert Threshold 1 1.5 2 V
IINV Invert Current 0 ≤ VINV ≤ 15V 0 1 µA
IVIN VIN Sense Input Current VIN = 100V
RUN/SS = 0V, VIN = 10V
100
0
140
1
µA
µA
IMAX IMAX Source Current VIMAX = 0V 10.5 12 13.5 µA
VOS(IMAX) VIMAX Offset Voltage |VSW| – VIMAX at IRUN/SS = 0µA
H Grade
–25
–25
10
10
55
65
mV
mV
VRUN/SS Shutdown Threshold 0.7 0.9 1.2 V
IRUN/SS RUN/SS Source Current RUN/SS = 0V 2.5 4 5.5 µA
Maximum RUN/SS Sink Current |VSW| – VIMAX ≥ 200mV, VRUN/SS = 3V 9 17 25 µA
VUV Undervoltage Lockout VCC Rising
VCC Falling
l
l
8.0
5.7
8.7
6.2
9.3
6.8
V
V
Oscillator
fOSC Oscillator Frequency RSET = 25k 270 300 330 kHz
fSYNC External Sync Frequency Range 100 600 kHz
tON(MIN) Minimum On-Time 200 ns
DCMAX Maximum Duty Cycle f < 200kHz 89 93 96 %
Driver
IBG(PEAK) BG Driver Peak Source Current 1.5 2 A
RBG(SINK) BG Driver Pull-Down RDS(ON) (Note 8) 1 1.5 Ω
ITG(PEAK) TG Driver Peak Source Current 1.5 2 A
RTG(SINK) TG Driver Pull-Down RDS(ON) (Note 8) 1 1.5 Ω
Feedback Amplifier
AVOL Op Amp DC Open Loop Gain (Note 4) 74 85 dB
fUOp Amp Unity Gain Crossover Frequency (Note 6) 25 MHz
IFB FB Input Current 0 ≤ VFB ≤ 3V 0 1 µA
ICOMP COMP Sink/Source Current ±5 ±10 mA
LTC3703
4
3703fc
Typical perForMance characTerisTics
Efficiency vs Input Voltage Efficiency vs Load Current Load Transient Response
VCC Current vs VCC Voltage VCC Current vs Temperature
VCC Shutdown Current vs
VCC Voltage
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3703E is guaranteed to meet performance specifications from
0°C to 85°C. Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with statistical
process controls. The LTC3703I is guaranteed over the full –40°C to 125°C
operating junction temperature range. The LTC3703H is guaranteed over the
full –40°C to 150°C operating junction temperature range.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LTC3703: TJ = TA + (PD • 100 °C/W) G Package
Note 4: The LTC3703 is tested in a feedback loop that servos VFB to the
reference voltage with the COMP pin forced to a voltage between 1V and 2V.
Note 5: The dynamic input supply current is higher due to the power
MOSFET gate charge being delivered at the switching frequency (QG • fOSC).
Note 6: Guaranteed by design. Not subject to test.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 8: RDS(ON) guaranteed by correlation to wafer level measurement.
Note 9: High junction temperatures degrade operating lifetimes. Operating
lifetime at junction temperatures greater than 125°C is derated to 1000 hours.
Note 10: Transient voltages (such as due to inductive ringing) are allowed
beyond this range provided that the voltage does not exceed 10V below
ground and duration does not exceed 20ns per switching cycle.
TA = 25°C unless otherwise noted.
INPUT VOLTAGE (V)
EFFICIENCY (%)
3703 G01
100
95
90
85
80
75
70 020 40 50
10 30 60 70 80
VOUT = 12V
f = 300kHz
PULSE SKIP DISABLED
IOUT = 0.5A
IOUT = 5A
LOAD CURRENT (A)
0 0.5 1.5 2.5 3.5 4.5
EFFICIENCY (%)
100
95
90
85
80
75
70 1.0 2.0 3.0 4.0
3703 G02
5.0
VOUT = 5V
f = 250kHz
PULSE SKIP ENABLED
VIN = 75V
VIN = 45V
VIN = 15V
3703 G03
VOUT
50mV/DIV
IOUT
2A/DIV
VIN = 50V
VOUT = 12V
1A TO 5A LOAD STEP
50µs/DIV
VCC VOLTAGE (V)
6
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12
3703 G04
8 10 14 16
VCC CURRENT (mA)
VFB = 0V
COMP = 1.5V
3703 G05
TEMPERATURE (°C)
–50 –25 0 25
VCC CURRENT (mA)
100 150
50 75 125
4
3
2
1
0
VFB = 0V
COMP = 1.5V
VCC VOLTAGE (V)
6
VCC CURRENT (µA)
100
90
80
70
60
50
40
30
20
10
014
3703 G06
810 12 16
LTC3703
5
3703fc
Typical perForMance characTerisTics
VCC Shutdown Current vs
Temperature
Reference Voltage vs
Temperature
Normalized Frequency vs
Temperature
Driver Peak Source Current vs
Temperature
Driver Pull-Down RDS(ON) vs
Temperature
Driver Peak Source Current vs
Supply Voltage
Driver Pull-Down RDS(ON) vs
Supply Voltage
Rise/Fall Time vs Gate
Capacitance
RUN/SS Pull-Up Current vs
Temperature
TEMPERATURE (°C)
–50 –25 0 25 100 150
50 75 125
VCC CURRENT (µA)
3703 G07
70
65
60
55
50
45
40
35
30
3703 G08
TEMPERATURE (°C)
–50 –25 0 25 100 150
50 75 125
REFERENCE VOLTAGE (V)
0.803
0.802
0.801
0.800
0.799
0.798
3703 G09
–50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
NORMALIZED FREQUENCY
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
PEAK SOURCE CURRENT (A)
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
3703 G10
TEMPERATURE (°C)
–50 –25 0 25 100 150
50 75 125
VCC = 10V
TEMPERATURE (°C)
RDS(ON) (Ω)
3703 G11
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–50 –25 0 25 100 150
50 75 125
VCC = 10V
DRVCC/BOOST VOLTAGE (V)
5 6 8 10 12 14
PEAK SOURCE CURRENT (A)
3.0
2.5
2.0
1.5
1.0
0.5
07 9 11 13
3703 G12
15
DRVCC/BOOST VOLTAGE (V)
6
RDS(ON) (Ω)
0.6
0.8
0.9
1.0
1.1
810 11 15
3703 G13
0.7
7 9 12 13 14
GATE CAPACITANCE (pF)
0
70
60
50
40
30
20
10
0
6000
3703 G14
2000 4000 8000 10000
RISE/FALL TIME (ns)
DRVCC, BOOST = 10V
RISE
FALL
TEMPERATURE (°C)
RUN/SS CURRENT (µA)
1573 G15
8
7
6
5
4
3
2
1
0
–50 –25 0 25 100 150
50 75 125
LTC3703
6
3703fc
Typical perForMance characTerisTics
RUN/SS Pull-Up Current vs
VCC Voltage
RUN/SS Sink Current vs
SW Voltage Max % DC vs RUN/SS Voltage
IMAX Current vs Temperature % Duty Cycle vs COMP Voltage
Max % DC vs Frequency and
Temperature
Shutdown Threshold vs
Temperature tON(MIN) vs Temperature
VCC VOLTAGE (V)
6
RUN/SS PULLUP CURRENT (µA)
6
5
4
3
2
1
08 10 12 14
3703 G16
16
|SW| VOLTAGE (V)
0
25
20
15
10
5
0
–5
–10
0.3 0.5
3703 G17
0.1 0.2 0.4 0.6 0.7
RUN/SS SINK CURRENT (µA)
IMAX = 0.3V
RUN VOLTAGE (V)
0.5
MAX DUTY CYCLE (%)
100
90
80
70
60
50
40
30
20
10
0
–10 2.5
3703 G18
1.0 1.5 2.0 3.0
3703 G19
IMAX SOURCE CURRENT (µA)
13
12
11
–50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) COMP (V)
0.5
DUTY CYCLE (%)
100
80
60
40
20
00.75 1.00 1.25 1.50
3703 G20
1.75 2.00
VIN = 10V
VIN = 75V
VIN = 50V
VIN = 25V
3703 G21
FREQUENCY (kHz)
MAX DUTY CYCLE (%)
100
95
90
85
80
75
70 0 200 400 500100 300 600 700
25°C
–45°C
90°C
150°C 125°C
TEMPERATURE (°C)
SHUTDOWN THRESHOLD (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3703 G22
–50 –25 0 25 50 75 100 125 150
3703 G23
tON(MIN) (ns)
200
180
160
140
120
100
80
60
40
–50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
LTC3703
7
3703fc
pin FuncTions
(GN16/G28)
MODE/SYNC (Pin 1/Pin 6): Pulse-Skip Mode Enable/Sync
Pin. This multifunction pin provides pulse-skip mode
enable/disable control and an external clock input for
synchronization of the internal oscillator. Pulling this pin
below 0.8V or to an external logic-level synchronization
signal disables pulse-skip mode operation and forces
continuous operation. Pulling the pin above 0.8V enables
pulse-skip mode operation. This pin can also be connected
to a feedback resistor divider from a secondary winding
on the inductor to regulate a second output voltage.
fSET (Pin 2/Pin 7): Frequency Set. A resistor connected
to this pin sets the free running frequency of the internal
oscillator. See Applications Information section for resistor
value selection details.
COMP (Pin 3/Pin 8): Loop Compensation. This pin is con-
nected directly to the output of the internal error amplifier.
An RC network is used at the COMP pin to compensate
the feedback loop for optimal transient response.
FB (Pin 4/Pin 9): Feedback Input. Connect FB through a
resistor divider network to VOUT to set the output volt-
age. Also connect the loop compensation network from
COMP to FB.
IMAX (Pin 5/Pin 10): Current Limit Set. The IMAX pin sets
the current limit comparator threshold. If the voltage drop
across the bottom MOSFET exceeds the magnitude of the
voltage at IMAX, the controller goes into current limit. The
IMAX pin has an internal 12µA current source, allowing the
current threshold to be set with a single external resistor
to ground. See the Current Limit Programming section
for more information on choosing RIMAX.
INV (Pin 6/Pin 11): Top/Bottom Gate Invert. Pulling this
pin above 2V sets the controller to operate in step-up
(boost) mode with the TG output driving the synchronous
MOSFET and the BG output driving the main switch. Below
1V, the controller will operate in step-down (buck) mode.
RUN/SS (Pin 7/Pin 13): Run/Soft-Start. Pulling RUN/SS
below 0.9V will shut down the LTC3703, turn off both of
the external MOSFET switches and reduce the quiescent
supply current to 50µA. A capacitor from RUN/SS to
ground will control the turn-on time and rate of rise of
the output voltage at power-up. An internal 4µA current
source pull-up at the RUN/SS pin sets the turn-on time
at approximately 750ms/µF.
GND (Pin 8/Pin 14): Ground Pin.
BGRTN (Pin 9/Pin 15): Bottom Gate Return. This pin
connects to the source of the pull-down MOSFET in the
BG driver and is normally connected to ground. Connect-
ing a negative supply to this pin allows the synchronous
MOSFET’s gate to be pulled below ground to help prevent
false turn-on during high dV/dt transitions on the SW node.
See the Applications Information section for more details.
BG (Pin 10/Pin 19): Bottom Gate Drive. The BG pin drives
the gate of the bottom N-channel synchronous switch
MOSFET. This pin swings from BGRTN to DRVCC.
DRVCC (Pin 11/Pin 20): Driver Power Supply Pin. DRVCC
provides power to the BG output driver. This pin should
be connected to a voltage high enough to fully turn on
the external MOSFETs, normally 10V to 15V for standard
threshold MOSFETs. DRVCC should be bypassed to BGRTN
with a 10µF, low ESR (X5R or better) ceramic capacitor.
VCC (Pin 12/Pin 21): Main Supply Pin. All internal circuits
except the output drivers are powered from this pin. VCC
should be connected to a low noise power supply voltage
between 9V and 15V and should be bypassed to GND
(Pin 8) with at least a 0.1µF capacitor in close proximity
to the LTC3703.
SW (Pin 13/Pin 26): Switch Node Connection to Inductor
and Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground to VIN.
TG (Pin 14/Pin 27): Top Gate Drive. The TG pin drives the
gate of the top N-channel synchronous switch MOSFET.
The TG driver draws power from the BOOST pin and
returns to the SW pin, providing true floating drive to the
top MOSFET.
BOOST (Pin 15/Pin 28): Top Gate Driver Supply. The
BOOST pin supplies power to the floating TG driver. The
BOOST pin should be bypassed to SW with a low ESR
(X5R or better) 0.1µF ceramic capacitor. An additional fast
recovery Schottky diode from DRVCC to BOOST will create
a complete floating charge-pumped supply at BOOST.
VIN (Pin 16/Pin 1): Input Voltage Sense Pin. This pin is
connected to the high voltage input of the regulator and is
used by the internal feedforward compensation circuitry
to improve line regulation. This is not a supply pin.
LTC3703
8
3703fc
FuncTional DiagraM
5
1
UVSD OTSD
CHIP
SD
0.9V
3.2V
4µA
RUN/SS
BANDGAP
SYNC
DETECT
OVER
TEMP VCC UVLO
OSC
% DC
LIMIT
DRIVE
LOGIC
+
–
+
–
+
–
+
–
EXT SYNC
FORCED CONTINUOUS
÷
+
+
–
+–+–
+
–
0.8V
MODE/SYNC
3COMP
4FB
16
15
14
13
11
10
9
6
12
VIN
VCC
(<15V)
INV
PWM
MIN MAX
0.76V 0.84V
±
OVERCURRENT
12µA
50mV
IMAX
RMAX
BOOST
TG
SW
DRVCC
BG
BGRTN
INV
8
GND
GN16
OT SD 0.8V
REFERENCE
INTERNAL
3.2V VCC
UV SD
2
fSET
3703 FD
REVERSE
CURRENT
FB
RSET
5
CSS
R2 R1
VCC
CVCC
DB
CB
VCC
VIN
M1
M2
COUT
VOUT
L1
INV
±
operaTion
(Refer to Functional Diagram)
The LTC3703 is a constant frequency, voltage mode con-
troller for DC/DC step-down converters. It is designed to
be used in a synchronous switching architecture with two
external N-channel MOSFETs. Its high operating voltage
capability allows it to directly step down input voltages up
to 100V without the need for a step-down transformer. For
circuit operation, please refer to the Functional Diagram
of the IC and Figure 1. The LTC3703 uses voltage mode
control in which the duty ratio is controlled directly by
the error amplifier output and thus requires no current
sense resistor. The VFB pin receives the output voltage
feedback and is compared to the internal 0.8V reference
by the error amplifier, which outputs an error signal at the
COMP pin. When the load current increases, it causes a
LTC3703
9
3703fc
operaTion
drop in the feedback voltage relative to the reference. The
COMP voltage then rises, increasing the duty ratio until
the output feedback voltage again matches the reference
voltage. In normal operation, the top MOSFET is turned
on when the RS latch is set by the on-chip oscillator and
is turned off when the PWM comparator trips and resets
the latch. The PWM comparator trips at the proper duty
ratio by comparing the error amplifier output (after being
“compensated” by the line feedforward multiplier) to a
sawtooth waveform generated by the oscillator. When the
top MOSFET is turned off, the bottom MOSFET is turned
on until the next cycle begins or, if pulse-skip mode op-
eration is enabled, until the inductor current reverses as
determined by the reverse current comparator. MAX and
MIN comparators ensure that the output never exceed
±5% of nominal value by monitoring VFB and forcing the
output back into regulation quickly by either keeping the top
MOSFET off or forcing maximum duty cycle. The operation
of its other features—fast transient response, outstanding
line regulation, strong gate drivers, short-circuit protection
and shutdown/soft-start—are described below.
Fast Transient Response
The LTC3703 uses a fast 25MHz op amp as an error ampli-
fier. This allows the compensation network to be optimized
for better load transient response. The high bandwidth of
the amplifier, along with high switching frequencies and
low value inductors, allow very high loop crossover fre-
quencies. The 800mV internal reference allows regulated
output voltages as low as 800mV without external level
shifting amplifiers.
Line Feedforward Compensation
The LTC3703 achieves outstanding line transient response
using a patented feedforward correction scheme. With
this circuit the duty cycle is adjusted instantaneously to
changes in input voltage, thereby avoiding unacceptable
overshoot or undershoot. It has the added advantage of
making the DC loop gain independent of input voltage.
Figure 2 shows how large transient steps at the input have
little effect on the output voltage.
Strong Gate Drivers
The LTC3703 contains very low impedance drivers capable
of supplying amps of current to slew large MOSFET gates
quickly. This minimizes transition losses and allows paral-
leling MOSFETs for higher current applications. A 100V
floating high side driver drives the topside MOSFET and
a low side driver drives the bottom side MOSFET (see
Figure 3). They can be powered from either a separate
DC supply or a voltage derived from the input or output
voltage (see MOSFET Driver Supplies section). The bottom
side driver is supplied directly from the DRVCC pin. The
top MOSFET drivers are biased from floating bootstrap
capacitor, CB, which normally is recharged during each off
cycle through an external diode from DRVCC when the top
MOSFET turns off. In pulse-skip mode operation, where
it is possible that the bottom MOSFET will be off for an
extended period of time, an internal counter guarantees
that the bottom MOSFET is turned on at least once every
10 cycles for 10% of the period to refresh the bootstrap
capacitor. An undervoltage lockout keeps the LTC3703
shut down unless this voltage is above 8.7V.
The bottom driver has an additional feature that helps
minimize the possibility of external MOSFET shoot-through.
When the top MOSFET turns on, the switch node dV/dt
pulls up the bottom MOSFET’s internal gate through the
Miller capacitance, even when the bottom driver is holding
the gate terminal at ground. If the gate is pulled up high
enough, shoot-through between the topside and bottom
VOUT
50mV/DIV
VIN
20V/DIV
IL
2A/DIV
20µs/DIV 3703 F02
VOUT = 12V
ILOAD = 1A
25V TO 60V VIN STEP
Figure 2. Line Transient Performance
(Refer to Functional Diagram)
LTC3703
10
3703fc
side MOSFETs can occur. To prevent this from occurring,
the bottom driver return is brought out as a separate pin
(BGRTN) so that a negative supply can be used to reduce
the effect of the Miller pull-up. For example, if a –2V sup-
ply is used on BGRTN, the switch node dV/dt could pull
the gate up 2V before the VGS of the bottom MOSFET has
more than 0V across it.
duty cycle control set to 0%. As CSS continues to charge,
the duty cycle is gradually increased, allowing the output
voltage to rise. This soft-start scheme smoothly ramps the
output voltage to its regulated value with no overshoot.
The RUN/SS voltage will continue ramping until it reaches
an internal 4V clamp. Then the MIN feedback comparator
is enabled and the LTC3703 is in full operation. When the
RUN/SS is low, the supply current is reduced to 50µA.
BOOST
TG
SW
BG
BGRTN
DRVCC
DRVCC
LTC3703
MT
MB
+
+
VIN
CIN
VOUT
COUT
DB
CB
L
3703 F03
0V TO –5V
Figure 3. Floating TG Driver Supply and Negative BG Return
Constant Frequency
The internal oscillator can be programmed with an external
resistor connected from fSET to ground to run between
100kHz and 600kHz, thereby optimizing component size,
efficiency, and noise for the specific application. The internal
oscillator can also be synchronized to an external clock
applied to the MODE/SYNC pin and can lock to a frequency
in the 100kHz to 600kHz range. When locked to an external
clock, pulse-skip mode operation is automatically disabled.
Constant frequency operation brings with it a number of
benefits: inductor and capacitor values can be chosen for
a precise operating frequency and the feedback loop can
be similarly tightly specified. Noise generated by the circuit
will always be at known frequencies. Subharmonic oscil-
lation and slope compensation, common headaches with
constant frequency current mode switchers, are absent in
voltage mode designs like the LTC3703.
Shutdown/Soft-Start
The main control loop is shut down by pulling RUN/SS
pin low. Releasing RUN/SS allows an internal 4µA current
source to charge the soft-start capacitor, CSS. When CSS
reaches 0.9V, the main control loop is enabled with the
CURRENT
LIMIT
NORMAL OPERATION
START-UP
0V
4V
3V
1.4V
0.9V
0V
POWER
DOWN MODE
MINIMUM
DUTY CYCLE
OUTPUT VOLTAGE
IN REGULATION
LTC3703
ENABLE
MIN COMPARATOR ENABLED
3703 F04
RUN/SS SOFT-STARTS
OUTPUT VOLTAGE AND
INDUCTOR CURRENT
SHUTDOWN
VOUT
VRUN/SS
Figure 4. Soft-Start Operation in Start-Up and Current Limit
Current Limit
The LTC3703 includes an onboard current limit circuit that
limits the maximum output current to a user-programmed
level. It works by sensing the voltage drop across the
bottom MOSFET and comparing that voltage to a user-
programmed voltage at the IMAX pin. Since the bottom
MOSFET looks like a low value resistor during its on-time,
the voltage drop across it is proportional to the current
flowing in it. In a buck converter, the average current in
the inductor is equal to the output current. This current
also flows through the bottom MOSFET during its on-time.
Thus by watching the drain-to-source voltage when the
bottom MOSFET is on, the LTC3703 can monitor the output
current. The LTC3703 senses this voltage and inverts it to
allow it to compare the sensed voltage (which becomes
more negative as peak current increases) with a positive
voltage at the IMAX pin. The IMAX pin includes a 12µA
pull-up, enabling the user to set the voltage at IMAX with
a single resistor (RIMAX) to ground. See the Current Limit
Programming section for RIMAX selection.
operaTion
(Refer to Functional Diagram)
LTC3703
11
3703fc
For maximum protection, the LTC3703 current limit con-
sists of a steady-state limit circuit and an instantaneous
limit circuit. The steady-state limit circuit is a gm amplifier
that pulls a current from the RUN/SS pin proportional
to the difference between the SW and IMAX voltages.
This current begins to discharge the capacitor at RUN/
SS, reducing the duty cycle and controlling the output
voltage until the current regulates at the limit. Depending
on the size of the capacitor, it may take many cycles to
discharge the RUN/SS voltage enough to properly regulate
the output current. This is where the instantaneous limit
circuit comes into play. The instantaneous limit circuit is
a cycle-by-cycle comparator which monitors the bottom
MOSFET’s drain voltage and keeps the top MOSFET from
turning on whenever the drain voltage is 50mV above the
programmed max drain voltage. Thus the cycle-by-cycle
comparator will keep the inductor current under control
until the gm amplifier gains control.
Pulse-Skip Mode
The LTC3703 can operate in one of two modes selectable
with the MODE/SYNC pin—pulse-skip mode or forced
continuous mode. Pulse-skip mode is selected when in-
creased efficiency at light loads is desired. In this mode,
the bottom MOSFET is turned off when inductor current
reverses to minimize the efficiency loss due to reverse cur-
rent flow. As the load is decreased (see Figure 5), the duty
cycle is reduced to maintain regulation until its minimum
on-time (~200ns) is reached. When the load decreases
below this point, the LTC3703 begins to skip cycles to
maintain regulation. The frequency drops but this further
improves efficiency by minimizing gate charge losses. In
forced continuous mode, the bottom MOSFET is always
on when the top MOSFET is off, allowing the inductor cur-
rent to reverse at low currents. This mode is less efficient
due to resistive losses, but has the advantage of better
transient response at low currents, constant frequency
operation, and the ability to maintain regulation when
sinking current. See Figure 6 for a comparison of the ef-
fect on efficiency at light loads for each mode. The MODE/
SYNC threshold is 0.8V ±7.5%, allowing the MODE/SYNC
to act as a feedback pin for regulating a second winding.
If the feedback voltage drops below 0.8V, the LTC3703
reverts to continuous operation to maintain regulation in
the secondary supply.
PULSE-SKIP MODE FORCED CONTINUOUS
DECREASING
LOAD
CURRENT
3703 F05
LOAD (mA)
10
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0100 1000 10000
3703 F06
FORCED CONTINUOUS
PULSE SKIP MODE
VIN = 75V
VIN = 25V
VIN = 25V
VIN = 75V
Figure 5. Comparison of Inductor Current Waveforms for Pulse-Skip Mode and Forced Continuous Operation
Figure 6. Efficiency in Pulse-Skip/Forced Continuous Modes
operaTion
(Refer to Functional Diagram)
LTC3703
12
3703fc
Buck or Boost Mode Operation
The LTC3703 has the capability of operating both as a
step-down (buck) and step-up (boost) controller. In boost
mode, output voltages as high as 80V can be tightly regu-
lated. With the INV pin grounded, the LTC3703 operates
in buck mode with TG driving the main (topside) switch
and BG driving the synchronous (bottom side) switch.
If the INV pin is pulled above 2V, the LTC3703 operates
in boost mode with BG driving the main (bottom side)
switch and TG driving the synchronous (topside) switch.
Internal circuit operation is very similar regardless of the
operating mode with the following exceptions: in boost
mode, pulse-skip mode operation is always disabled
regardless of the level of the MODE/SYNC pin and the
line feedforward compensation is also disabled. The
overcurrent circuitry continues to monitor the load cur-
rent by looking at the drain voltage of the main (bottom
side) MOSFET. In boost mode, however, the peak MOS-
FET current does not equal the load current but instead
ID = ILOAD/(1 – D). This factor needs to be taken into ac-
count when programming the IMAX voltage.
applicaTions inForMaTion
The basic LTC3703 application circuit is shown in Figure 1.
External component selection is determined by the input
voltage and load requirements as explained in the following
sections. After the operating frequency is selected, RSET
and L can be chosen. The operating frequency and the
inductor are chosen for a desired amount of ripple current
and also to optimize efficiency and component size. Next,
the power MOSFETs and D1 are selected based on voltage,
load and efficiency requirements. CIN is selected for its
ability to handle the large RMS currents in the converter
and COUT is chosen with low enough ESR to meet the
output voltage ripple and transient specifications. Finally,
the loop compensation components are chosen to meet
the desired transient specifications.
Operating Frequency
The choice of operating frequency and inductor value is
a trade-off between efficiency and component size. Low
frequency operation improves efficiency by reducing MOS-
FET switching losses and gate charge losses. However,
lower frequency operation requires more inductance for a
given amount of ripple current, resulting in a larger induc-
tor size and higher cost. If the ripple current is allowed
to increase, larger output capacitors may be required to
maintain the same output ripple. For converters with high
step-down VIN to VOUT ratios, another consideration is
the minimum on-time of the LTC3703 (see the Minimum
On-Time Considerations section). A final consideration for
operating frequency is that in noise-sensitive communica-
tions systems, it is often desirable to keep the switching
noise out of a sensitive frequency band.
The LTC3703 uses a constant frequency architecture that
can be programmed over a 100kHz to 600kHz range with
a single resistor from the fSET pin to ground, as shown
in Figure 1. The nominal voltage on the fSET pin is 1.2V,
and the current that flows from this pin is used to charge
and discharge an internal oscillator capacitor. The value
of RSET for a given operating frequency can be chosen
from Figure 7 or from the following equation:
RSET(kΩ)=
7100
f(kHz)– 25
FREQUENCY (kHz)
RSET (kΩ)
1000
3703 F07
10
1
100
200 1000800600400
0
Figure 7. Timing Resistor (RSET) Value
operaTion
(Refer to Functional Diagram)
LTC3703
13
3703fc
applicaTions inForMaTion
The oscillator can also be synchronized to an external
clock applied to the MODE/SYNC pin with a frequency in
the range of 100kHz to 600kHz (refer to the MODE/SYNC
Pin section for more details). In this synchronized mode,
pulse-skip mode operation is disabled. The clock high level
must exceed 2V for at least 25ns. As shown in Figure 8,
the top MOSFET turn-on will follow the rising edge of the
external clock by a constant delay equal to one-tenth of
the cycle period.
3703 F08
2V TO 10V
MODE/
SYNC
TG
IL
tMIN = 25ns
0.8T
0.1T
D = 40%
T T = 1/fO
Figure 8. MODE/SYNC Clock Input and Switching
Waveforms for Synchronous Operation
Inductor
The inductor in a typical LTC3703 circuit is chosen for a
specific ripple current and saturation current. Given an
input voltage range and an output voltage, the inductor
value and operating frequency directly determine the ripple
current. The inductor ripple current in the buck mode is:
∆IL=VOUT
(f)(L) 1– VOUT
VIN
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus highest efficiency operation is obtained at
low frequency with small ripple current. To achieve this
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
between 20% and 40% of IO(MAX). Note that the largest
ripple current occurs at the highest VIN. To guarantee that
ripple current does not exceed a specified maximum, the
inductor in buck mode should be chosen according to:
L≥VOUT
f∆IL(MAX)
1– VOUT
VIN(MAX)
The inductor also has an affect on low current operation
when pulse-skip mode operation is enabled. The frequency
begins to decrease when the output current drops below
the average inductor current at which the LTC3703 is
operating at its tON(MIN) in discontinuous mode (see
Figure 6). Lower inductance increases the peak inductor
current that occurs in each minimum on-time pulse and
thus increases the output current at which the frequency
starts decreasing.
Power MOSFET Selection
The LTC3703 requires at least two external N-channel
power MOSFETs, one for the top (main) switch and one or
more for the bottom (synchronous) switch. The number,
type and “on” resistance of all MOSFETs selected take into
account the voltage step-down ratio as well as the actual
position (main or synchronous) in which the MOSFET will
be used. A much smaller and much lower input capacitance
MOSFET should be used for the top MOSFET in applica-
tions that have an output voltage that is less than 1/3 of
the input voltage. In applications where VIN >> VOUT, the
top MOSFETs’ “on” resistance is normally less important
for overall efficiency than its input capacitance at operating
frequencies above 300kHz. MOSFET manufacturers have
designed special purpose devices that provide reason-
ably low “on” resistance with significantly reduced input
capacitance for the main switch application in switching
regulators.
Selection criteria for the power MOSFETs include the “on”
resistance RDS(ON), input capacitance, breakdown voltage
and maximum output current.
The most important parameter in high voltage applications
is breakdown voltage BVDSS. Both the top and bottom
MOSFETs will see full input voltage plus any additional
ringing on the switch node across its drain-to-source dur-
ing its off-time and must be chosen with the appropriate
LTC3703
14
3703fc
applicaTions inForMaTion
breakdown specification. Since many high voltage MOS-
FETs have higher threshold voltages (typically, VGS(MIN)
≥ 6V), the LTC3703 is designed to be used with a 9V to
15V gate drive supply (DRVCC pin).
For maximum efficiency, on-resistance RDS(ON) and input
capacitance should be minimized. Low RDS(ON) minimizes
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 9).
+
–VDS
VIN
VGS
MILLER EFFECT
QIN
a b
CMILLER = (QB – QA)/VDS
VGS V
+
–
3703 F09
Figure 9. Gate Charge Characteristic
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given VDS drain
voltage, but can be adjusted for different VDS voltages by
multiplying by the ratio of the application VDS to the curve
specified VDS values. A way to estimate the CMILLER term
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
VDS voltage specified. CMILLER is the most important se-
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. CRSS and COS are specified sometimes but
definitions of these parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =
V
OUT
VIN
Synchronous Switch Duty Cycle =VIN – VOUT
VIN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
MAIN =VOUT
VIN
IMAX
( )
2(1+δ)RDS(ON) +
VIN
2IMAX
2(RDR )(CMILLER )•
1
VCC – VTH(IL)
+1
VTH(IL)
(f)
PSYNC =VIN −VOUT
V
IN
(IMAX)2(1+δ)RDS(0N)
where δ is the temperature dependency of RDS(ON), RDR
is the effective top driver resistance (approximately 2Ω at
VGS = VMILLER), VIN is the drain potential and the change
in drain potential in the particular application. VTH(IL) is
the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet at the specified
drain current. CMILLER is the calculated capacitance using
the gate charge curve from the MOSFET data sheet and
the technique described above.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 25V,
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 25V, the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short circuit when the synchronous switch is on close
to 100% of the period.
LTC3703
15
3703fc
applicaTions inForMaTion
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, and
typically varies from 0.005/°C to 0.01/°C depending on
the particular MOSFET used.
Multiple MOSFETs can be used in parallel to lower RDS(ON)
and meet the current and thermal requirements if desired.
The LTC3703 contains large low impedance drivers capable
of driving large gate capacitances without significantly
slowing transition times. In fact, when driving MOSFETs
with very low gate charge, it is sometimes helpful to slow
down the drivers by adding small gate resistors (5Ω or less)
to reduce noise and EMI caused by the fast transitions.
Schottky Diode Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power MOS-
FETs. This prevents the body diode of the bottom MOSFET
from turning on and storing charge during the dead time
and requiring a reverse recovery period that could cost
as much as 1% to 2% in efficiency. A 1A Schottky diode
is generally a good size for 3A to 5A regulators. Larger
diodes result in additional losses due to their larger junc-
tion capacitance. The diode can be omitted if the efficiency
loss can be tolerated.
Input Capacitor Selection
In continuous mode, the drain current of the top MOSFET
is approximately a square wave of duty cycle VOUT/VIN
which must be supplied by the input capacitor. To prevent
large input transients, a low ESR input capacitor sized for
the maximum RMS current is given by:
ICIN(RMS) ≅IO(MAX)
VOUT
VIN
VIN
VOUT
–1
1/2
This formula has a maximum at VIN = 2VOUT, where IRMS =
IO(MAX)/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that the ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life. This makes it advisable to further derate the
capacitor or to choose a capacitor rated at a higher tempera-
ture than required. Several capacitors may also be placed in
parallel to meet size or height requirements in the design.
Because tantalum and OS-CON capacitors are not available
in voltages above 30V, for regulators with input supplies
above 30V, choice of input capacitor type is limited to
ceramics or aluminum electrolytics. Ceramic capacitors
have the advantage of very low ESR and can handle high
RMS current, however ceramics with high voltage ratings
(>50V) are not available with more than a few microfarads
of capacitance. Furthermore, ceramics have high voltage
coefficients which means that the capacitance values
decrease even more when used at the rated voltage. X5R
and X7R type ceramics are recommended for their lower
voltage and temperature coefficients. Another consider-
ation when using ceramics is their high Q which if not
properly damped, may result in excessive voltage stress
on the power MOSFETs. Aluminum electrolytics have much
higher bulk capacitance, however, they have higher ESR
and lower RMS current ratings.
A good approach is to use a combination of aluminum
electrolytics for bulk capacitance and ceramics for low ESR
and RMS current. If the RMS current cannot be handled
by the aluminum capacitors alone, when used together,
the percentage of RMS current that will be supplied by the
aluminum capacitor is reduced to approximately:
%IRMS,ALUM ≈
1
1+(8fCRESR )2
•100%
where RESR is the ESR of the aluminum capacitor and C
is the overall capacitance of the ceramic capacitors. Using
an aluminum electrolytic with a ceramic also helps damp
the high Q of the ceramic, minimizing ringing.
Output Capacitor Selection
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple. The output ripple
(∆VOUT) is approximately equal to:
∆VOUT ≤ ∆ILESR+1
8fCOUT
LTC3703
16
3703fc
applicaTions inForMaTion
Since ∆IL increases with input voltage, the output ripple
is highest at maximum input voltage. ESR also has a sig-
nificant effect on the load transient response. Fast load
transitions at the output will appear as voltage across the
ESR of COUT until the feedback loop in the LTC3703 can
change the inductor current to match the new load current
value. Typically, once the ESR requirement is satisfied the
capacitance is adequate for filtering and has the required
RMS current rating.
Manufacturers such as Nichicon, Nippon Chemi-Con and
Sanyo should be considered for high performance through-
hole capacitors. The OS-CON (organic semiconductor
dielectric) capacitor available from Sanyo has the lowest
product of ESR and size of any aluminum electrolytic at
a somewhat higher price. An additional ceramic capacitor
in parallel with OS-CON capacitors is recommended to
reduce the effect of their lead inductance.
In surface mount applications, multiple capacitors placed
in parallel may be required to meet the ESR, RMS current
handling and load step requirements. Dry tantalum, special
polymer and aluminum electrolytic capacitors are available
in surface mount packages. Special polymer capacitors
offer very low ESR but have lower capacitance density
than other types. Tantalum capacitors have the highest
capacitance density but it is important to only use types
that have been surge tested for use in switching power
supplies. Several excellent surge-tested choices are the
AVX TPS and TPSV or the KEMET T510 series. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-driven applications providing that
consideration is given to ripple current ratings and long
term reliability. Other capacitor types include Panasonic
SP and Sanyo POSCAPs.
Output Voltage
The LTC3703 output voltage is set by a resistor divider
according to the following formula:
VOUT =0.8V 1+R1
R2
The external resistor divider is connected to the output as
shown in the Functional Diagram, allowing remote voltage
sensing. The resultant feedback signal is compared with
the internal precision 800mV voltage reference by the
error amplifier. The internal reference has a guaranteed
tolerance of ±1%. Tolerance of the feedback resistors will
add additional error to the output voltage. 0.1% to 1%
resistors are recommended.
MOSFET Driver Supplies (DRVCC and BOOST)
The LTC3703 drivers are supplied from the DRVCC and
BOOST pins (see Figure 3), which have an absolute
maximum voltage of 15V. If the main supply voltage,
VIN, is higher than 15V a separate supply with a voltage
between 9V and 15V must be used to power the drivers.
If a separate supply is not available, one can easily be
generated from the main supply using one of the circuits
shown in Figure 10. If the output voltage is between 10V
and 15V, the output can be used to directly power the
drivers as shown in Figure 10a. If the output is below
10V, Figure 10b shows an easy way to boost the supply
voltage to a sufficient level. This boost circuit uses the
LT1613 in a ThinSOT™ package and a chip inductor for
minimal extra area (<0.2in2). Tw o other possible schemes
are an extra winding on the inductor (Figure 10c) or a
capacitive charge pump (Figure 10d). All the circuits
shown in Figure 10 require a start-up circuit (Q1, D1 and
R1) to provide driver power at initial start-up or following
a short-circuit. The resistor R1 must be sized so that it
supplies sufficient base current and zener bias current at
the lowest expected value of VIN. When using an exist-
ing supply, the supply must be capable of supplying the
required gate driver current which can be estimated from:
IDRVCC = (f)(QG(TOP) + QG(BOTTOM))
This equation for IDRVCC is also useful for properly sizing
the circuit components shown in Figure 10.
An external bootstrap capacitor, CB, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFETs. Capacitor CB is charged through external diode,
DB, from the DRVCC supply when SW is low. When the
topside MOSFET is turned on, the driver places the CB
voltage across the gate source of the top MOSFET. The
switch node voltage, SW, rises to VIN and the BOOST pin
follows. With the topside MOSFET on, the boost voltage is
LTC3703
17
3703fc
applicaTions inForMaTion
above the input supply: VBOOST = VIN + VDRVCC. The value
of the boost capacitor, CB, needs to be 100 times that
of the total input capacitance of the topside MOSFET(s).
The reverse breakdown of the external diode, DB, must be
greater than VIN(MAX). Another important consideration
for the external diode is the reverse recovery and reverse
leakage, either of which may cause excessive reverse cur-
rent to flow at full reverse voltage. If the reverse current
times reverse voltage exceeds the maximum allowable
power dissipation, the diode may be damaged. For best
results, use an ultrafast recovery silicon diode such as
the BAS19.
An internal undervoltage lockout (UVLO) monitors the volt-
age on DRVCC to ensure that the LTC3703 has sufficient
gate drive voltage. If the DRVCC voltage falls below the
UVLO threshold, the LTC3703 shuts down and the gate
drive outputs remain low.
VCC
DRVCC
VIN
TG
SW
BG
BGRTN
LTC3703
VOUT
10V TO
15V
+COUT
3703 F10a
+CIN
+1µF
VIN
L1
12V
VCC
DRVCC
VIN
TG
SW
BG
BGRTN
LTC3703
VOUT
<10V
+COUT
3703 F10b
+
CIN
C9
4.7µF
6.3V
VIN
L1
12V
C10
1µF
16V VIN
SW
GND
SHDN
FB
R17
1M
1%
R17
110k
1%
LT1613
D2
ZHCS400 L2
10µH
VCC
DRVCC
FCB
GND
VIN
TG1
SW
BG1
BGRTN
LTC3703
VOUT
VSEC
+COUT
+1µF
3703 F10c
R1
VIN
T1
OPTIONAL VCC
CONNECTION
10V < VSEC < 15V
R2
+CIN
12V
N
1VCC
DRVCC
VIN
TG
SW
BG
BGRTN
LTC3703
VOUT
+COUT
3703 F10d
+
+
CIN
VIN (<40V)
L1
1µF
12V
BAT85
BAT85 BAT85
VN2222LL
0.22µF
Figure 10a. VCC Generated from 10V < VOUT < 15V Figure 10b. VCC Generated from VOUT < 10V
Figure 10c. Secondary Output Loop and VCC Connection Figure 10d. Capacitive Charge Pump for VCC (VIN < 40V)
LTC3703
18
3703fc
Bottom MOSFET Source Supply (BGRTN)
The bottom gate driver, BG, switches from DRVCC to
BGRTN where BGRTN can be a voltage between ground
and –5V. Why not just keep it simple and always connect
BGRTN to ground? In high voltage switching converters,
the switch node dV/dt can be many volts/ns, which will
pull up on the gate of the bottom MOSFET through its
Miller capacitance. If this Miller current, times the internal
gate resistance of the MOSFET plus the driver resistance,
exceeds the threshold of the FET, shoot-through will oc-
cur. By using a negative supply on BGRTN, the BG can be
pulled below ground when turning the bottom MOSFET off.
This provides a few extra volts of margin before the gate
reaches the turn-on threshold of the MOSFET. Be aware
that the maximum voltage difference between DRVCC and
BGRTN is 15V. If, for example, VBGRTN = –2V, the maximum
voltage on DRVCC pin is now 13V instead of 15V.
Current Limit Programming
Programming current limit on the LTC3703 is straight
forward. The IMAX pin sets the current limit by setting
the maximum allowable voltage drop across the bottom
MOSFET. The voltage across the MOSFET is set by its on-
resistance and the current flowing in the inductor, which
is the same as the output current. The LTC3703 current
limit circuit inverts the negative voltage across the MOSFET
before comparing it to the voltage at IMAX, allowing the
current limit to be set with a positive voltage.
To set the current limit, calculate the expected voltage
drop across the bottom MOSFET at the maximum desired
current and maximum junction temperature:
VPROG = (ILIMIT)(RDS(ON))(1 + δ)
where δ is explained in the MOSFET Selection section.
VPROG is then programmed at the IMAX pin using the
internal 12µA pull-up and an external resistor:
RIMAX = VPROG/12µA
The current limit value should be checked to ensure
that ILIMIT(MIN) > IOUT(MAX) and also that ILIMIT(MAX) is
less than the maximum rated current of the inductor
and bottom MOSFET. The minimum value of current
limit generally occurs with the largest VIN at the highest
ambient temperature, conditions that cause the largest
power loss in the converter. Note that it is important to
check for self-consistency between the assumed MOSFET
junction temperature and the resulting value of ILIMIT which
heats the MOSFET switches.
Caution should be used when setting the current limit based
upon the RDS(ON) of the MOSFETs. The maximum current
limit is determined by the minimum MOSFET on-resistance.
Data sheets typically specify nominal and maximum values
for RDS(ON), but not a minimum. A reasonable assumption
is that the minimum RDS(ON) lies the same amount below
the typical value as the maximum lies above it. Consult the
MOSFET manufacturer for further guidelines.
For best results, use a VPROG voltage between 100mV and
500mV. Values outside of this range may give less accu-
rate current limit. The current limit can also be disabled
by floating the IMAX pin.
FEEDBACK LOOP/COMPENSATION
Feedback Loop Types
In a typical LTC3703 circuit, the feedback loop consists of
the modulator, the external inductor, the output capacitor
and the feedback amplifier with its compensation network.
All of these components affect loop behavior and must be
accounted for in the loop compensation. The modulator
consists of the internal PWM generator, the output MOS-
FET drivers and the external MOSFETs themselves. From
a feedback loop point of view, it looks like a linear voltage
transfer function from COMP to SW and has a gain roughly
equal to the input voltage. It has fairly benign AC behavior
at typical loop compensation frequencies with significant
phase shift appearing at half the switching frequency.
The external inductor/output capacitor combination
makes a more significant contribution to loop behavior.
These components cause a second order LC roll off at the
output, with the attendant 180° phase shift. This rolloff is
what filters the PWM waveform, resulting in the desired
DC output voltage, but the phase shift complicates the
loop compensation if the gain is still higher than unity at
the pole frequency. Eventually (usually well above the LC
pole frequency), the reactance of the output capacitor will
applicaTions inForMaTion
LTC3703
19
3703fc
approach its ESR and the rolloff due to the capacitor will
stop, leaving 6dB/octave and 90° of phase shift (Figure 11).
Type 2 loops work well in systems where the ESR zero
in the LC roll-off happens close to the LC pole, limiting
the total phase shift due to the LC. The additional phase
compensation in the feedback amplifier allows the 0dB
point to be at or above the LC pole frequency, improving
loop bandwidth substantially over a simple Type 1 loop.
It has limited ability to compensate for LC combinations
where low capacitor ESR keeps the phase shift near 180°
for an extended frequency range. LTC3703 circuits using
conventional switching grade electrolytic output capaci-
tors can often get acceptable phase margin with Type 2
compensation.
“Type 3” loops (Figure 14) use two poles and two zeros to
obtain a 180° phase boost in the middle of the frequency
band. A properly designed Type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180° phase shift
well above the initial LC roll-off. As with a Type 2 circuit,
the loop should cross through 0dB in the middle of the
phase bump to maximize phase margin. Many LTC3703
circuits using low ESR tantalum or OS-CON output capaci-
tors need Type 3 compensation to obtain acceptable phase
margin with a high bandwidth feedback loop.
applicaTions inForMaTion
GAIN (dB)
3703 F11
AV
0
PHASE
–6dB/OCT
–12dB/OCT
GAIN
PHASE (DEG)
FREQ
–90
–180
–270
–360
Figure 11. Transfer Function of Buck Modulator
So far, the AC response of the loop is pretty well out
of the user’s control. The modulator is a fundamental
piece of the LTC3703 design and the external L and C are
usually chosen based on the regulation and load current
requirements without considering the AC loop response.
The feedback amplifier, on the other hand, gives us a
handle with which to adjust the AC response. The goal is
to have 180° phase shift at DC (so the loop regulates) and
something less than 360° phase shift at the point that the
loop gain falls to 0dB. The simplest strategy is to set up
the feedback amplifier as an inverting integrator, with the
0dB frequency lower than the LC pole (Figure 12). This
“Type 1” configuration is stable but transient response is
less than exceptional if the LC pole is at a low frequency.
GAIN (dB)
3703 F12
0
PHASE
–6dB/OCT
GAIN
PHASE (DEG)
FREQ
–90
–180
–270
–360
RB
R1
FB
C1
IN
OUT
+
–
VREF
Figure 12. Type 1 Schematic and Transfer Function
Figure 13 shows an improved “Type 2” circuit that uses
an additional pole-zero pair to temporarily remove 90°
of phase shift. This allows the loop to remain stable with
90° more phase shift in the LC section, provided the loop
reaches 0dB gain near the center of the phase “bump.”
GAIN (dB)
3703 F13
0
PHASE
–6dB/OCT
–6dB/OCT
GAIN
PHASE (DEG)
FREQ
–90
–180
–270
–360
RB
VREF
R1
R2
FB
C2
IN
OUT
+
–
C1
Figure 13. Type 2 Schematic and Transfer Function
GAIN (dB)
3703 F14
0
PHASE
–6dB/OCT
+6dB/OCT –6dB/OCT
GAIN
PHASE (DEG)
FREQ
–90
–180
–270
–360
RB
VREF
R1
R2
FB
C2
IN
OUT
+
–
C1
C3
R3
Figure 14. Type 3 Schematic and Transfer Function
LTC3703
20
3703fc
Feedback Component Selection
Selecting the R and C values for a typical Type 2 or
Type 3 loop is a nontrivial task. The applications shown
in this data sheet show typical values, optimized for the
power components shown. They should give acceptable
performance with similar power components, but can be
way off if even one major power component is changed
significantly. Applications that require optimized transient
response will require recalculation of the compensation
values specifically for the circuit in question. The underlying
mathematics are complex, but the component values can
be calculated in a straightforward manner if we know the
gain and phase of the modulator at the crossover frequency.
Modulator gain and phase can be measured directly from a
breadboard or can be simulated if the appropriate parasitic
values are known. Measurement will give more accurate
results, but simulation can often get close enough to give
a working system. To measure the modulator gain and
phase directly, wire up a breadboard with an LTC3703
and the actual MOSFETs, inductor and input and output
capacitors that the final design will use. This breadboard
should use appropriate construction techniques for high
speed analog circuitry: bypass capacitors located close
to the LTC3703, no long wires connecting components,
appropriately sized ground returns, etc. Wire the feedback
amplifier as a simple Type 1 loop, with a 10k resistor from
VOUT to FB and a 0.1µF feedback capacitor from COMP
to FB. Choose the bias resistor, RB, as required to set the
desired output voltage. Disconnect RB from ground and
connect it to a signal generator or to the source output
of a network analyzer to inject a test signal into the loop.
Measure the gain and phase from the COMP pin to the
output node at the positive terminal of the output capacitor.
Make sure the analyzer’s input is AC coupled so that the
DC voltages present at both the COMP and VOUT nodes
don’t corrupt the measurements or damage the analyzer.
If breadboard measurement is not practical, a SPICE
simulation can be used to generate approximate gain/
phase curves. Plug the expected capacitor, inductor and
MOSFET values into the following SPICE deck and gener-
ate an AC plot of V(VOUT )/V(COMP) in dB and phase of
VOUT in degrees. Refer to your SPICE manual for details
of how to generate this plot.
*3703 modulator gain/phase
*2003 Linear Technology
*this file written to run with PSpice 8.0
*may require modifications for other
SPICE simulators
*MOSFETs
rfet mod sw 0.02 ;MOSFET rdson
*inductor
lext sw out1 10u ;inductor value
rl out1 out 0.015 ;inductor series R
*output cap
cout out out2 540u ;capacitor value
resr out2 0 0.01 ;capacitor ESR
*3703 internals
emod mod 0 value = {57*v(comp)}
;3703multiplier
vstim comp 0 0 ac 1 ;ac stimulus
.ac dec 100 1k 1meg
.probe
.end
With the gain/phase plot in hand, a loop crossover fre-
quency can be chosen. Usually the curves look something
like Figure 11. Choose the crossover frequency in the ris-
ing or flat parts of the phase curve, beyond the external
LC poles. Frequencies between 10kHz and 50kHz usually
work well. Note the gain (GAIN, in dB) and phase (PHASE,
in degrees) at this point. The desired feedback amplifier
gain will be –GAIN to make the loop gain at 0dB at this
frequency. Now calculate the needed phase boost, assum-
ing 60° as a target phase margin:
BOOST = –(PHASE + 30°)
If the required BOOST is less than 60°, a Type 2 loop can
be used successfully, saving two external components.
BOOST values greater than 60° usually require Type 3
loops for satisfactory performance.
applicaTions inForMaTion
LTC3703
21
3703fc
Finally, choose a convenient resistor value for R1 (10k is
usually a good value). Now calculate the remaining values:
(K is a constant used in the calculations)
f = chosen crossover frequency
G = 10(GAIN/20) (this converts GAIN in dB to G in
absolute gain)
TYPE 2 Loop:
K=tan BOOST
2+45°
C2 =1
2π•f•G•K•R1
C1=C2 K2−1
( )
R2 =K
2π•f•C1
RB=VREF(R1)
VOUT −VREF
TYPE 3 Loop:
K=tan2BOOST
4+45°
C2 =1
2π•f•G•R1
C1=C2 K −1
( )
R2 =K
2π•f•C1
R3 =R1
K−1
C3 =1
2πf K •R3
RB=VREF(R1)
VOUT −VREF
Boost Converter Design
The following sections discuss the use of the LTC3703
as a step-up (boost) converter. In boost mode, the
LTC3703 can step-up output voltages as high as 80V.
These sections discuss only the design steps specific to
a boost converter. For the design steps common to both
a buck and a boost, see the applicable section in the buck
mode section. An example of a boost converter circuit
is shown in the Typical Applications section. To operate
the LTC3703 in boost mode, the INV pin should be tied
to the VCC voltage (or a voltage above 2V). Note that in
boost mode, pulse-skip operation and the line feedforward
compensation are disabled.
For a boost converter, the duty cycle of the main switch is:
D=
V
OUT
– V
IN
VOUT
For high VOUT to VIN ratios, the maximum VOUT is limited
by the LTC3703’s maximum duty cycle which is typically
93%. The maximum output voltage is therefore:
VOUT(MAX) =VIN(MIN)
1–DMAX
≅14VIN(MIN)
Boost Converter: Inductor Selection
In a boost converter, the average inductor current equals
the average input current. Thus, the maximum average
inductor current can be calculated from:
IL(MAX) =IO(MAX)
1−DMAX
=IO(MAX) •VO
VIN(MIN)
Similar to a buck converter, choose the ripple current to
be 20% to 40% of IL(MAX). The ripple current amplitude
then determines the inductor value as follows:
L=
V
IN(MIN)
∆IL•f•DMAX
The minimum required saturation current for the inductor is:
IL(SAT) > IL(MAX) + ∆IL/2
Boost Converter: Power MOSFET Selection
For information about choosing power MOSFETs for a
boost converter, see the Power MOSFET Selection section
for the buck converter, since MOSFET selection is similar.
applicaTions inForMaTion
LTC3703
22
3703fc
However, note that the power dissipation equations for
the MOSFETs at maximum output current in a boost
converter are:
P
MAIN =DMAX
IMAX
1–DMAX
2
1+δ
( )
RDS(ON) +
1
2VOUT
2IMAX
1–DMAX
RDR
( )
CMILLER
( )
•
1
VCC – VTH(IL)
+1
VTH(IL)
f
( )
PSYNC =–1
1–DMAX
IMAX
( )
21+δ
( )
RDS(ON)
Boost Converter: Output Capacitor Selection
In boost mode, the output capacitor requirements are
more demanding due to the fact that the current waveform
is pulsed instead of continuous as in a buck converter.
The choice of component(s) is driven by the acceptable
ripple voltage which is affected by the ESR, ESL and bulk
capacitance as shown in Figure 15. The total output ripple
voltage is:
∆VOUT =IO(MAX)
1
f•COUT
+ESR
1–DMAX
where the first term is due to the bulk capacitance and
second term due to the ESR.
At lower output voltages (less than 30V), it may be pos-
sible to satisfy both the output ripple voltage and RMS
ripple current requirements with one or more capacitors
of a single capacitor type. However, at output voltages
above 30V where capacitors with both low ESR and high
bulk capacitance are hard to find, the best approach is to
use a combination of aluminum and ceramic capacitors
(see discussion in Input Capacitor section for the buck
converter). With this combination, the ripple voltage can
be improved significantly. The low ESR ceramic capaci-
tor will minimize the ESR step, while the electrolytic will
supply the required bulk capacitance.
Boost Converter: Input Capacitor Selection
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input and the input current waveform
is continuous. The input voltage source impedance deter-
mines the size of the input capacitor, which is typically in
the range of 10µF to 100µF. A low ESR capacitor is recom-
mended though not as critical as for the output capacitor.
The RMS input capacitor ripple current for a boost con-
verter is:
IRMS(CIN) =0.3•
V
IN(MIN)
L•f
•DMAX
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to
the input of the converter and solid tantalum capacitors
can fail catastrophically under these conditions. Be sure
to specify surge-tested capacitors!
Boost Converter: Current Limit Programming
The LTC3703 provides current limiting in boost mode by
monitoring the VDS of the main switch during its on-time
and comparing it to the voltage at IMAX. To set the cur-
rent limit, calculate the expected voltage drop across the
MOSFET at the maximum desired inductor current and
maximum junction temperature. The maximum inductor
current is a function of both duty cycle and maximum
load current, so the limit must be set for the maximum
applicaTions inForMaTion
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
∆VESR
∆VCOUT
VOUT
(AC)
Figure 15. Output Voltage Ripple Waveform for a Boost Converter
The choice of output capacitor is driven also by the RMS
ripple current requirement. The RMS ripple current is:
IRMS(COUT) ≈IO(MAX) •VO– VIN(MIN)
VIN(MIN)
LTC3703
23
3703fc
expected duty cycle (minimum VIN) in order to ensure
that the current limit does not kick in at loads < IO(MAX):
VPROG =IO(MAX)
1–DMAX
RDS(ON)(1+δ)
=VOUT
VIN(MIN)
IO(MAX) •RDS(ON)(1+δ)
Once VPROG is determined, RIMAX is chosen as follows:
RIMAX = VPROG/12µA
Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where VOUT > VIN.
For hard shorts, the inductor current is limited only by the
input supply capability. Refer to Current Limit Program-
ming for buck mode for further considerations for current
limit programming.
Boost Converter: Feedback Loop/Compensation
Compensating a voltage mode boost converter is unfor-
tunately more difficult than for a buck converter. This is
due to an additional right-half plane (RHP) zero that is
present in the boost converter but not in a buck. The ad-
ditional phase lag resulting from the RHP zero is difficult
if not impossible to compensate even with a Type 3 loop,
so the best approach is usually to roll off the loop gain at
a lower frequency than what could be achievable in buck
converter.
A typical gain/phase plot of a voltage mode boost converter
is shown in Figure 16. The modulator gain and phase can
be measured as described for a buck converter or can be
estimated as follows:
GAIN (COMP-to-VOUT DC gain) = 20Log(VOUT2/VIN)
Dominant Pole: fP =
V
IN
VOUT
•
1
2πLC
Since significant phase shift begins at frequencies above
the dominant LC pole, choose a crossover frequency no
greater than about half this pole frequency. The gain of
the compensation network should equal –GAIN at this
frequency so that the overall loop gain is 0dB here. The
compensation component to achieve this, using a Type 1
amplifier (see Figure 12), is:
G = 10–GAIN/20
C1 = 1/(2π • f • G • R1)
Run/Soft-Start Function
The RUN/SS pin is a multipurpose pin that provide a soft-
start function and a means to shut down the LTC3703.
Soft-start reduces the input supply’s surge current by
gradually increasing the duty cycle and can also be used
for power supply sequencing.
Pulling RUN/SS below 0.9V puts the LTC3703 into a low
quiescent current shutdown (IQ ≅ 50µA). This pin can be
driven directly from logic as shown in Figure 17. Releasing
the RUN/SS pin allows an internal 4µA current source to
applicaTions inForMaTion
GAIN
(dB)
PHASE
(DEG)
3703 F16
AV
0 0
–90
–180
PHASE
GAIN
–12dB/OCT
Figure 16. Transfer Function of Boost Modulator
2ms/DIV
VOUT
5V/DIV
VIN = 50V
ILOAD = 2A
CSS = 0.01µF
RUN/SS
2V/DIV
IL
2A/DIV
3703 F17
Figure 17. LTC3703 Start-Up Operation
LTC3703
24
3703fc
charge up the soft-start capacitor CSS. When the voltage
on RUN/SS reaches 0.9V, the LTC3703 begins operating
at its minimum on-time. As the RUN/SS voltage increases
from 1.4V to 3V, the duty cycle is allowed to increase from
0% to 100%. The duty cycle control minimizes input supply
inrush current and eliminates output voltage overshoot at
start-up and ensures current limit protection even with a
hard short. The RUN/SS voltage is internally clamped at 4V.
If RUN/SS starts at 0V, the delay before starting is
approximately:
tDELAY,START =
1V
4µA CSS =(0.25s/µF)CSS
plus an additional delay, before the output will reach its
regulated value, of:
tDELAY,REG ≥
3V – 1V
4µA CSS =(0.5s/µF)CSS
The start delay can be reduced by using diode D1 in
Figure 18.
the main output voltage and the turns ratio of the extra
winding to the primary winding as follows:
VSEC ≈ (N + 1)VOUT
Since the secondary winding only draws current when the
synchronous switch is on, load regulation at the auxiliary
output will be relatively good as long as the main output
is running in continuous mode. As the load on the primary
output drops and the LTC3703 switches to pulse-skip
mode operation, the auxiliary output may not be able to
maintain regulation, especially if the load on the auxiliary
output remains heavy. To avoid this, the auxiliary output
voltage can be divided down with a conventional feedback
resistor string with the divided auxiliary output voltage fed
back to the MODE/SYNC pin. The MODE/SYNC threshold
is trimmed to 800mV with 20mV of hysteresis, allowing
precise control of the auxiliary voltage and is set as follows:
VSEC(MIN) ≈0.8V 1+R1
R2
where R1 and R2 are shown in Figure 10c.
If the LTC3703 is operating in pulse-skip mode and the
auxiliary output voltage drops below VSEC(MIN), the MODE/
SYNC pin will trip and the LTC3703 will resume continu-
ous operation regardless of the load on the main output.
Thus, the MODE/SYNC pin removes the requirement that
power must be drawn from the inductor primary in order
to extract power from the auxiliary winding. With the loop
in continuous mode (MODE/SYNC < 0.8V), the auxiliary
outputs may nominally be loaded without regard to the
primary output load.
The following table summarizes the possible states avail-
able on the MODE/SYNC pin:
Table 1
MODE/SYNC PIN CONDITION
DC Voltage: 0V to 0.75V Forced Continuous
Current Reversal Enabled
DC Voltage: ≥ 0.87V Pulse-Skip Mode Operation
No Current Reversal
Feedback Resistors Regulating a Secondary Winding
Ext. Clock: 0V to ≥ 2V Forced Continuous
Current Reversal Enabled
applicaTions inForMaTion
3.3V
OR 5V RUN/SS
D1
CSS
3703 F18
RUN/SS
CSS
Figure 18. RUN/SS Pin Interfacing
MODE/SYNC Pin (Operating Mode and Secondary
Winding Control)
The MODE/SYNC pin is a dual function pin that can be
used for enabling or disabling pulse-skip mode operation
and also as an external clock input for synchronizing the
internal oscillator (see next section). Pulse-skip mode is
enabled when the MODE/SYNC pin is above 0.8V and is
disabled, i.e., forced continuous, when the pin is below 0.8V.
In addition to providing a logic input to force continuous
operation and external synchronization, the MODE/SYNC
pin provides a means to regulate a flyback winding output
as shown in Figure 10c. The auxiliary output is taken from
a second winding on the core of the inductor, converting
it to a transformer. The auxiliary output voltage is set by
LTC3703
25
3703fc
MODE/SYNC Pin (External Synchronization)
The internal LTC3703 oscillator can be synchronized to
an external oscillator by applying and clocking the MODE/
SYNC pin with a signal above 2VP-P
. The internal oscillator
locks to the external clock after the second clock transition
is received. When external synchronization is detected,
LTC3703 will operate in forced continuous mode. If an
external clock transition is not detected for three suc-
cessive periods, the internal oscillator will revert to the
frequency programmed by the RSET resistor. The internal
oscillator can synchronize to frequencies between 100kHz
and 600kHz, independent of the frequency programmed by
the RSET resistor. However, it is recommended that an RSET
resistor be chosen such that the frequency programmed
by the RSET resistor is close to the expected frequency of
the external clock. In this way, the best converter operation
(ripple, component stress, etc) is achieved if the external
clock signal is lost.
Fault Conditions: Output Overvoltage Protection
(Crowbar)
The output overvoltage crowbar is designed to blow a
system fuse in the input lead when the output of the regula-
tor rises much higher than nominal levels. This condition
causes huge currents to flow, much greater than in normal
operation. This feature is designed to protect against a
shorted top MOSFET; it does not protect against a failure
of the controller itself.
The comparator (MAX in the Functional Diagram) detects
overvoltage faults greater than 5% above the nominal
output voltage. When this condition is sensed the top
MOSFET is turned off and the bottom MOSFET is forced
on. The bottom MOSFET remains on continuously for as
long as the 0V condition persists; if VOUT returns to a safe
level, normal operation automatically resumes.
Minimum On-Time Considerations (Buck Mode)
Minimum on-time tON(MIN) is the smallest amount of time
that the LTC3703 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays
and the amount of gate charge required to turn on the
top MOSFET. Low duty cycle applications may approach
this minimum on-time limit and care should be taken to
ensure that:
tON =
V
OUT
VIN •f>tON(MIN)
where tON(MIN) is typically 200ns.
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3703 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency opera-
tion is acceptable, the on-time can be increased above
tON(MIN) for the same step-down ratio.
Pin Clearance/Creepage Considerations
The LTC3703 is available in two packages (GN16 and G28)
both with identical functionality. The GN16 package gives
the smallest size solution, however the 0.013" (minimum)
space between pins may not provide sufficient PC board
trace clearance between high and low voltage pins in higher
voltage applications. Where clearance is an issue, the G28
package should be used. The G28 package has four un-
connected pins between the all adjacent high voltage and
low voltage pins, providing 5(0.0106") = 0.053" clearance
which will be sufficient for most applications up to 100V.
For more information, refer to the printed circuit board
design standards described in IPC-2221 (www.ipc.org).
Efficiency Considerations
The efficiency of a switching regulator is equal to the out-
put power divided by the input power (x100%). Percent
efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power. It is often useful to analyze the individual
losses to determine what is limiting the efficiency and
what change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3703 circuits: 1) LTC3703 VCC current, 2)
MOSFET gate current, 3) I2R losses, 4) Topside MOSFET
transition losses.
applicaTions inForMaTion
LTC3703
26
3703fc
1. VCC supply current. The VCC current is the DC supply
current given in the Electrical Characteristics table which
powers the internal control circuitry of the LTC3703.
Total supply current is typically about 2.5mA and usually
results in a small (<1%) loss which is proportional to
VCC.
2. DRVCC current is MOSFET driver current. This current
results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched on
and then off, a packet of gate charge QG moves from
DRVCC to ground. The resulting dQ/dt is a current out
of the DRVCC supply. In continuous mode, IDRVCC =
f(QG(TOP) + QG(BOT)), where QG(TOP) and QG(BOT) are
the gate charges of the top and bottom MOSFETs.
3. I2R losses are predicted from the DC resistances of
MOSFETs, the inductor and input and output capacitor
ESR. In continuous mode, the average output current
flows through L but is “chopped” between the topside
MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same RDS(ON), then
the resistance of one MOSFET can simply be summed
with the DCR resistance of L to obtain I2R losses. For
example, if each RDS(ON) = 25mΩ and RL = 25mΩ, then
total resistance is 50mΩ. This results in losses ranging
from 1% to 5% as the output current increases from
1A to 5A for a 5V output.
4. Transition losses apply only to the topside MOSFET in
buck mode and they become significant when operat-
ing at higher input voltages (typically 20V or greater).
Transition losses can be estimated from the second
term of the PMAIN equation found in the Power MOSFET
Selection section.
The transition losses can become very significant at
the high end of the LTC3703 operating voltage range.
To improve efficiency, one may consider lowering the
frequency and/or using MOSFETs with lower CRSS at
the expense of higher RDS(ON).
Other losses including CIN and COUT ESR dissipative
losses, Schottky conduction losses during dead time, and
inductor core losses generally account for less than 2%
total additional loss.
Transient Response
Due to the high gain error amplifier and line feedforward
compensation of the LTC3703, the output accuracy due
to DC variations in input voltage and output load current
will be almost negligible. For the few cycles following a
load transient, however, the output deviation may be larger
while the feedback loop is responding. Consider a typical
48V input to 5V output application circuit, subjected to a 1A
to 5A load transient. Initially, the loop is in regulation and
the DC current in the output capacitor is zero. Suddenly,
an extra 4A (= 5A – 1A) flows out of the output capacitor
while the inductor is still supplying only 1A. This sudden
change will generate a (4A) • (RESR) voltage step at the
output; with a typical 0.015Ω output capacitor ESR, this
is a 60mV step at the output.
The feedback loop will respond and will move at the
bandwidth allowed by the external compensation network
towards a new duty cycle. If the unity-gain crossover
frequency is set to 50kHz, the COMP pin will get to 60%
of the way to 90% duty cycle in 3µs. Now the inductor is
seeing 43V across itself for a large portion of the cycle
and its current will increase from 1A at a rate set by di/
dt = V/L. If the inductor value is 10µH, the peak di/dt
will be 43V/10µH or 4.3A/µs. Sometime in the next few
microseconds after the switch cycle begins, the inductor
current will have risen to the 5A level of the load current
and the output voltage will stop dropping. At this point,
the inductor current will rise somewhat above the level
of the output current to replenish the charge lost from
the output capacitor during the load transient. With a
properly compensated loop, the entire recovery time will
be inside of 10µs.
Most loads care only about the maximum deviation from
ideal, which occurs somewhere in the first two cycles after
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirely controlled by the ESR of the capacitor and amounts
to most of the total voltage drop. To minimize this drop,
choose a low ESR capacitor and/or parallel multiple capaci-
tors at the output. The capacitance value accounts for the
rest of the voltage drop until the inductor current rises.
applicaTions inForMaTion
LTC3703
27
3703fc
With most output capacitors, several devices paralleled
to get the ESR down will have so much capacitance that
this drop term is negligible. Ceramic capacitors are an
exception; a small ceramic capacitor can have suitably low
ESR with relatively small values of capacitance, making
this second drop term more significant.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on transient
recovery time, the time it takes the LTC3703 to recover
after the output voltage has dropped due to a load step.
Optimizing loop compensation entails maintaining the high-
est possible loop bandwidth while ensuring loop stability.
The feedback component selection section describes in
detail the techniques used to design an optimized Type 3
feedback loop, appropriate for most LTC3703 systems.
Measurement Techniques
Measuring transient response presents a challenge in
two respects: obtaining an accurate measurement and
generating a suitable transient to test the circuit. Output
measurements should be taken with a scope probe directly
across the output capacitor. Proper high frequency probing
techniques should be used. In particular, don’t use the 6"
ground lead that comes with the probe! Use an adapter that
fits on the tip of the probe and has a short ground clip to
ensure that inductance in the ground path doesn’t cause
a bigger spike than the transient signal being measured.
Conveniently, the typical probe tip ground clip is spaced
just right to span the leads of a typical output capacitor.
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test and switch it on and off while
watching the output. If this isn’t convenient, a current
step generator is needed. This generator needs to be able
to turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC3703 and the transient generator
must be minimized.
Figure 19 shows an example of a simple transient gen-
erator. Be sure to use a noninductive resistor as the load
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution
is to take ten 1/4W film resistors and wire them in parallel
to get the desired value. This gives a noninductive resis-
tive load which can dissipate 2.5W continuously or 50W
if pulsed with a 5% duty cycle, enough for most LTC3703
circuits. Solder the MOSFET and the resistor(s) as close
to the output of the LTC3703 circuit as possible and set
up the signal generator to pulse at a 100Hz rate with a 5%
duty cycle. This pulses the LTC3703 with 500µs transients
10ms apart, adequate for viewing the entire transient
recovery time for both positive and negative transitions
while keeping the load resistor cool.
Design Example
As a design example, take a supply with the following
specifications: VIN = 36V to 72V (48V nominal), VOUT =
12V ±5%, IOUT(MAX) = 10A, f = 250kHz. First, calculate
RSET to give the 250kHz operating frequency:
RSET = 7100/(250 – 25) = 31.6k
Next, choose the inductor value for about 40% ripple
current at maximum VIN:
L=12V
(250kHz)(0.4)(10A) 1– 12
72
=10µH
With 10µH inductor, ripple current will vary from 3.2A to
4A (32% to 40%) over the input supply range.
Next, verify that the minimum on-time is not violated. The
minimum on-time occurs at maximum VIN:
tON(MIN) =
V
OUT
VIN(MIN)(f) =
12
72(250kHz) =667ns
which is above the LTC3703’s 200ns minimum on-time.
applicaTions inForMaTion
LTC3703 VOUT
IRFZ44 OR
EQUIVALENT
RLOAD
50Ω
0V TO 10V
100Hz, 5%
DUTY CYCLE
LOCATE CLOSE TO THE OUTPUT
3703 F19
PULSE
GENERATOR
Figure 19. Transient Load Generator
LTC3703
28
3703fc
applicaTions inForMaTion
Next, choose the top and bottom MOSFET switch. Since
the drain of each MOSFET will see the full supply voltage
72V (max) plus any ringing, choose a 100V MOSFET to
provide a margin of safety. Si7456DP has a 100V BVDSS,
RDS(ON) = 25mΩ (max), δ = 0.009/°C, CMILLER = (19nC
– 10nC)/50V = 180pF, VGS(MILLER) = 4.7V, θJA = 20°C/W.
The power dissipation can be estimated at maximum input
voltage, assuming a junction temperature of 100°C (30°C
above an ambient of 70°C):
P
MAIN =12
72(10)21+0.009(100 – 25)
[ ]
(0.025)
+(72)210
2
(2)(180pF)•1
10 – 4.7 +1
4.7
(250k)
=0.70W +0.94W =1.64W
And double check the assumed TJ in the MOSFET:
TJ = 70°C + (1.64W)(20°C/W) = 103°C
Since the synchronous MOSFET will be conducting over
twice as long each period (almost 100% of the period
in short circuit) as the top MOSFET, use two Si7456DP
MOSFETs on the bottom:
PSYNC =72−12
72
(10)21+0.009(100 – 25)
[ ]
•
0.025
2
=1.74W
TJ = 70°C + (1.74W)(20°C/W) = 105°C
Next, set the current limit resistor. Since IMAX = 10A, the
limit should be set such that the minimum current limit is
>10A. Minimum current limit occurs at maximum RDS(ON).
Using the above calculation for bottom MOSFET TJ, the
max RDS(ON) = (25mΩ/2) [1 + 0.009 (105-25)] = 21.5mΩ.
Therefore, IMAX pin voltage should be set to (10A)(0.0215)
= 0.215V. The RSET resistor can now be chosen to be
0.215V/12µA = 18k.
CIN is chosen for an RMS current rating of about 5A
(IMAX/2) at 85°C. For the output capacitor, two low ESR
OS-CON capacitors (18mΩ each) are used to minimize
output voltage changes due to inductor current ripple and
load steps. The ripple voltage will be:
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (4A)(0.018Ω/2)
= 36mV
However, a 0A to 10A load step will cause an output volt-
age change of up to:
∆VOUT(STEP) = ∆ILOAD(ESR) = (10A)(0.009Ω) = 90mV
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3703. These items are also illustrated graphically in the
layout diagram of Figure 18. For layout of a boost mode
converter, layout is similar with VIN and VOUT swapped.
Check the following in your layout:
1. Keep the signal and power grounds separate. The signal
ground consists of the LTC3703 GND pin, the ground
return of CVCC, and the (–) terminal of VOUT. The power
ground consists of the Schottky diode anode, the source
of the bottom side MOSFET, and the (–) terminal of the
input capacitor and DRVCC capacitor. Connect the signal
and power grounds together at the (–) terminal of the
output capacitor. Also, try to connect the (–) terminal
of the output capacitor as close as possible to the (–)
terminals of the input and DRVCC capacitor and away
from the Schottky loop described in (2).
2. The high di/dt loop formed by the top N-channel MOSFET,
the bottom MOSFET and the CIN capacitor should have
short leads and PC trace lengths to minimize high fre-
quency noise and voltage stress from inductive ringing.
3. Connect the drain of the top side MOSFET directly to the
(+) plate of CIN, and connect the source of the bottom
side MOSFET directly to the (–) terminal of CIN. This
capacitor provides the AC current to the MOSFETs.
4. Place the ceramic CDRVCC decoupling capacitor imme-
diately next to the IC, between DRVCC and BGRTN. This
capacitor carries the MOSFET drivers’ current peaks.
Likewise the CB capacitor should also be next to the IC
between BOOST and SW.
LTC3703
29
3703fc
applicaTions inForMaTion
5. Place the small-signal components away from high
frequency switching nodes (BOOST, SW, TG, and BG).
In the layout shown in Figure 20, all the small-signal
components have been placed on one side of the IC
and all of the power components have been placed on
the other. This also helps keep the signal ground and
power ground isolated.
6. A separate decoupling capacitor for the supply, VCC,
is useful with an RC filter between the DRVCC supply
and VCC pin to filter any noise injected by the drivers.
Connect this capacitor close to the IC, between the
VCC and GND pins and keep the ground side of the VCC
capacitor (signal ground) isolated from the ground side
of the DRVCC capacitor (power ground).
7. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC3703 in order
to keep the high impedance FB node short.
8. For applications with multiple switching power con-
verters connected to the same input supply, make
sure that the input filter capacitor for the LTC3703
is not shared with other converters. AC input current
from another converter could cause substantial input
voltage ripple, and this could interfere with the opera-
tion of the LTC3703. A few inches of PC trace or wire
(L ≅ 100nH) between CIN of the LTC3703 and the actual
source VIN should be sufficient to prevent input noise
interference problems.
LTC3703
MODE/SYNC
fSET
COMP
FB
IMAX
INV
RUN/SS
GND
VIN
BOOST
TG
SW
VCC
DRVCC
BG
BGRTN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
CIN
CC2
CC3
RC1
RC2 R1
R2 RF
RMAX
RSET
CB
VIN
M1
M2
L1
D1 VOUT
COUT
DB
VCC
CSS
3703 F18
CDRVCC
X5R
CVCC
X5R
+
+
+
–
Figure 20. LTC3703 Buck Converter Suggested Layout
LTC3703
30
3703fc
Typical applicaTions
36V-72V Input Voltage to 5V/10A Step-Down Converter with Pulse Skip Mode Enabled
LTC3703
MODE/SYNC
fSET
COMP
FB
IMAX
INV
RUN/SS
GND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VIN
BOOST
TG
SW
VCC
DRVCC
BG
BGRTN
CIN
68µF
100V
×2
CC2
1000pF
CC3
2200pF
RC1
10k
RMAX 20k
CC1
470pF
RC2
100Ω
R1
113k
1%
R2
21.5k
1% RF 10Ω
RSET
25k
CB
0.1µF
VIN
36V TO 72V
M2
Si7852DP
L1
4.7µH
D1
MBR1100
VOUT
5V
10A
COUT
270µF
10V
×2
DB
BAS19
VCC
9.3V TO 15V
CSS
0.1µF
3703 TA01
CDRVCC
10µF
CVCC
1µF
+
+
+
M1
Si7852DP
22µF
25V
Single Input Supply 12V/5A Output Step-Down Converter
LTC3703
MODE/SYNC
fSET
COMP
FB
IMAX
INV
RUN/SS
GND
VIN
BOOST
TG
SW
VCC
DRVCC
BG
BGRTN
CIN
68µF
100V
VIN
15V TO 80V
CC2
1000pF
CC3
2200pF
RC1
10k
RMAX 12k
CC1
470pF
RC2
100Ω
*OPTIONAL ZENER PROVIDES UNDERVOLTAGE LOCKOUT ON INPUT SUPPLY, VUVLO ≅ 10 + VZ
R1
113k
1%
R2
8.06k
1% RF 10Ω
RSET 25k
CB
0.1µF
M2
Si7852DP
L1
8µH
D1
MBR1100
VOUT
12V
5A
COUT
270µF
16V
DB
BAS19
CSS
0.1µF
3703 TA02
CDRVCC
10µF
CVCC
1µF
+
+
+
M1
Si7852DP
22µF
25V
FZT600
100Ω
10k *
12V
CMDSH-3
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
LTC3703
31
3703fc
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN16 REV B 0212
1 2 345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ±.004
(0.38 ±0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
LTC3703
32
3703fc
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
G28 SSOP 0204
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
1 2 3 4 5678 9 10 11 12 1413
9.90 – 10.50*
(.390 – .413)
2526 22 21 20 19 18 17 16 1523242728
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
LTC3703
33
3703fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
C 05/12 Note 10 Added. 4
(Revision history begins at Rev C)
LTC3703
34
3703fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
LT 0512 REV C • PRINTED IN USA
relaTeD parTs
Typical applicaTion
12V to 24V/5A Synchronous Boost Converter
PART NUMBER DESCRIPTION COMMENTS
LT
®
1074HV/LT1076HV Monolithic 5A/2A Step-Down DC/DC Converters VIN up to 60V, TO-220 and DD Packages
LT1339 High Power Synchronous DC/DC Controller VIN up to 60V, Drivers 10,000pF Gate Capacitance, IOUT ≤ 20A
LTC1702A Dual, 2-Phase Synchronous DC/DC Controller 550kHz Operation, No RSENSE, 3V ≤ VIN ≤ 7V, IOUT ≤ 20A
LTC1735 Synchronous Step-Down DC/DC Controller 3.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤6V, Current Mode, IOUT ≤ 20A
LTC1778 No RSENSE™ Synchronous DC/DC Controller 4V ≤ VIN ≤ 36V, Fast Transient Response, Current Mode, IOUT ≤ 20A
LT1956 Monolithic 1.5A, 500kHz Step-Down Regulator 5.5V ≤ VIN ≤ 60V, 2.5mA Supply Current, 16-Pin SSOP
LT3010 50mA, 3V to 80V Linear Regulator 1.275V ≤ VOUT ≤ 60V, No Protection Diode Required, 8-Lead MSOP
LT3430/LT3431 Monolithic 3A, 200kHz/500kHz Step-Down Regulator 5.5V ≤ VIN ≤ 60V, 0.1Ω Saturation Switch, 16-Pin SSOP
LT3433 Monolithic Step-Up/Step-Down DC/DC Converter 4V ≤ VIN ≤ 60V, 500mA Switch, Automatic Step-Up/Step-Down,
Single Inductor
LTC3703-5 60V Synchronous DC/DC Controller 4V ≤ VIN ≤ 60V, Voltage Mode, 1Ω Logic-Level MOSFET Drivers
LT3800 60V Synchronous DC/DC Controller 4V ≤ VIN ≤ 60V, Current Mode, 1.23V ≤ VOUT ≤ 36V
LTC3703
MODE/SYNC
fSET
COMP
FB
IMAX
INV
RUN/SS
GND
VIN
BOOST
TG
SW
VCC
DRVCC
BG
BGRTN
COUT
220µF
35V
×3
COUT2
10µF
50V
X5R
×2
RMAX 15k
CC1
100pF
0.1µF
R2
3.92k
1%
RF 10Ω
10k
R1
113k
1%
RSET 30.1k
CB
0.1µF
M2
Si7892DP
L1
3.3µH
B240A
VIN
10V TO 15V
VOUT
24V
5A
CIN
100µF
16V
DB
CMDSH-3
CSS
0.1F
3703 TA03
CDRVCC
10µF
CVCC
1µF
+
+
+
M1
Si7892DP
22µF
25V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
L1: VISHAY IHLPSOSOEZ
CIN: OSCON 20SP180M
COUT1: SANYO 35MV220AX
COUT2: UNITED CHEMICON
NTS60X5R1H106MT
