Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MCF5206 TM ColdFire Integrated Microprocessor User's Manual Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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(505) 298-7177 UTAH, Salt Lake City Utah Component Sales, Inc. (801) 561-5099 WASHINGTON, Spokane Doug Kenley (509) 924-2322 ARGENTINA, Buenos Aires Argonics, S.A. (541) 343-1787 HYBRID COMPONENTS RESELLERS Elmo Semiconductor (818) 768-7400 Minco Technology Labs Inc. (512) 834-2022 Semi Dice Inc. (310) 594-4631 MCF5206 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. PREFACE The MCF5206 ColdFire Integrated Microprocessor User's Manual describes the programming, capabilities, and operation of the MCF5206 device. Refer to the MCF5200 ColdFire Family Programmer's Reference Manual for information on the ColdFire Family of microprocessors. TRADEMARKS All trademarks reside with their respective owners. CONTENTS Freescale Semiconductor, Inc... This user manual is organized as follows: Section 1: Introduction Section 2: Signal Description Section 3: ColdFire Core Section 4: Instruction Cache Section 5: SRAM Section 6: Bus Operation Section 7: System Integration Module (SIM) Section 8: Chip-Select Module Section 9: Parallel Port (General-Purpose I/O) Module Section 10: DRAM Controller Section 11: UART Module Section 12: M-Bus Module Section 13: Timer Module Section 14: Debug Support Section 15: IEEE 1149.1 Test Access Port (JTAG) Section 16: Electrical Characteristics Section 17: Mechanical Characteristics Appendix A: Memory Map Appendix B: Porting from M68K Architectures Index MOTOROLA MCF5206 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com v Date: 8-31-98 Freescale Semiconductor, Inc. Revision No.: 1.1 Pages affected: See change bars TABLE OF CONTENTS Freescale Semiconductor, Inc... Paragraph Number 1.1 1.2 1.3 1.3.1 1.3.1.1 1.3.1.2 1.3.1.3 1.3.1.4 1.3.1.5 1.3.1.6 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.8 1.3.8.1 1.3.8.2 1.3.9 1.3.10 1.3.11 1.3.12 1.3.13 1.3.14 Title Page Number Section 1 Introduction Background .......................................................................................... 1-1 MCF5206 Features .............................................................................. 1-2 Functional Blocks ................................................................................. 1-4 ColdFire Processor Core............................................................ 1-4 Processor States ............................................................1-4 Programming Model ....................................................... 1-5 Data Format Summary ................................................... 1-8 Addressing Capabilities Summary ..................................1-8 Notational Conventions................................................... 1-8 Instruction Set Overview................................................. 1-8 Instruction Cache ..................................................................... 1-14 Internal SRAM ..........................................................................1-14 DRAM Controller ...................................................................... 1-14 DUART Module ........................................................................ 1-15 Timer Module ........................................................................... 1-15 Motorola Bus (M-Bus) Module.................................................. 1-15 System Interface ...................................................................... 1-15 External Bus Interface .................................................. 1-15 Chip Selects.................................................................. 1-16 8-Bit Parallel Port (General-Purpose I/O)................................. 1-16 Interrupt Controller ................................................................... 1-16 System Protection .................................................................... 1-16 JTAG ........................................................................................ 1-16 System Debug Interface........................................................... 1-16 Pinout and Package ................................................................. 1-17 Section 2 Signal Description 2.1 2.2 2.2.1 2.2.2 2.2.3 2.3 2.3.1 MOTOROLA Introduction........................................................................................... 2-1 Address Bus .........................................................................................2-3 Address Bus (A[27:24]/ CS[7:4]/ WE[0:3]) ................................. 2-4 Address Bus (A[23:0]) ................................................................ 2-4 Data Bus (D[31:0])...................................................................... 2-4 Chip Selects ......................................................................................... 2-4 Chip Selects (A[27:24]/ CS[7:4]/ WE[0:3]).................................. 2-5 MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com i Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Freescale Semiconductor, Inc... 2.3.2 2.3.3 2.4 2.4.1 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.5.8 2.6 2.6.1 2.6.2 2.6.3 2.7 2.7.1 2.7.2 2.7.3 2.8 2.8.1 2.8.2 2.8.3 2.9 2.9.1 2.9.2 2.9.3 2.9.4 2.10 2.10.1 2.10.2 2.11 2.11.1 2.11.2 2.12 2.12.1 2.12.2 2.13 2.13.1 ii Title Page Number Chip Selects (CS[3:0])................................................................ 2-5 Byte Write Enables (A[27:24]/ CS[7:4]/ WE[0:3]) ....................... 2-5 Interrupt Control Signals ...................................................................... 2-7 Interrupt Priority Level/ Interrupt Request (IPL[2]/IRQ[7],IPL[1]/IRQ[4], IPL[0]/IRQ[1]) .............................................................................. 2-7 Bus Control Signals.............................................................................. 2-8 Read/Write (R/W)....................................................................... 2-8 Size (SIZ[1:0]) ............................................................................ 2-8 Transfer Type (TT[1:0]) .............................................................. 2-9 Access Type and Mode (ATM)................................................... 2-9 Transfer Start (TS) ................................................................... 2-10 Transfer Acknowledge (TA) ..................................................... 2-10 Asynchronous Transfer Acknowledge (ATA) ........................... 2-10 Transfer Error Acknowledge (TEA) .......................................... 2-11 Bus Arbitration Signals....................................................................... 2-11 Bus Request (BR) .................................................................... 2-11 Bus Grant (BG) ........................................................................ 2-11 Bus Driven (BD) ....................................................................... 2-11 Clock and Reset Signals .................................................................... 2-12 Clock Input (CLK) ..................................................................... 2-12 Reset (RSTI) ............................................................................ 2-12 Reset Out (RTS[2]/RSTO) ....................................................... 2-12 DRAM Controller Signals ................................................................... 2-12 Row Address Strobes (RAS[1:0]) ............................................. 2-13 Column Address Strobes (CAS[3:0]) ....................................... 2-13 DRAM Write (DRAMW) ............................................................ 2-14 UART Module Signals ........................................................................ 2-14 Receive Data (RxD[1], RxD[2]) ................................................ 2-14 Transmit Data (TxD[1], TxD[2]) ................................................ 2-14 Request To Send (RTS[1], RTS[2]/RSTO) .............................. 2-15 Clear To Send (CTS[1], CTS[2]) .............................................. 2-15 Timer Module Signals ........................................................................ 2-15 Timer Input (TIN[2], TIN[1]) ...................................................... 2-15 Timer Output (TOUT[2], TOUT[1]) ........................................... 2-15 M-Bus Module Signals ....................................................................... 2-15 M-Bus Serial Clock (SCL) ........................................................ 2-15 M-Bus Serial Data (SDA) ......................................................... 2-15 General Purpose I/O Signals ............................................................. 2-16 General Purpose I/O (PP[7:4]/PST[3:0]) .................................. 2-16 Parallel Port (General-Purpose I/O) (PP[3:0]/DDATA[3:0]) ...... 2-16 Debug Support Signals ...................................................................... 2-16 Processor Status (PP[7:4]/PST[3:0]) ........................................ 2-16 USEROS MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 2.13.2 2.13.3 2.13.4 2.13.5 2.13.6 2.14 2.14.1 2.14.2 2.14.3 2.14.4 2.14.5 2.15 2.15.1 2.15.2 2.16 Title Page Number Debug Data (PP[3:0]/DDATA[3:0])........................................... 2-17 Development Serial Clock (TRST/DSCLK) ..............................2-17 Break Point (TMS/BKPT) .........................................................2-17 Development Serial Input (TDI/DSI) .........................................2-18 Development Serial Output (TDO/DSO) ..................................2-18 JTAG Signals .....................................................................................2-18 Test Clock (TCK) ......................................................................2-18 Test Reset (TRST/DSCLK) ......................................................2-18 Test Mode Select (TMS/BKPT) ................................................2-19 Test Data Input (TDI/DSI) .........................................................2-19 Test Data Output (TDO/DSO) ..................................................2-19 Test Signals ........................................................................................2-19 Motorola Test Mode (MTMOD) ................................................2-19 High Impedance (HIZ) ..............................................................2-20 Signal Summary .................................................................................2-20 Section 3 ColdFire Core 3.1 3.2 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.1.4 3.2.1.5 3.2.2 3.2.2.1 3.2.2.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 MOTOROLA Processor Pipelines ..............................................................................3-1 Processor Register Description ............................................................3-2 User Programming Model ..........................................................3-2 Data Registers (D0D7) .................................................3-2 Address Registers (A0A6) ............................................3-2 Stack Pointer (A7) ...........................................................3-2 Program Counter (PC).....................................................3-2 Condition Code Register (CCR) ......................................3-3 Supervisor Programming Model .................................................3-4 Status Register ...............................................................3-4 Vector Base Register (VBR) ...........................................3-5 Exception Processing Overview ...........................................................3-5 Exception Stack Frame Definition ........................................................3-7 Processor Exceptions ...........................................................................3-8 Access Error Exception ..............................................................3-8 Address Error Exception ............................................................3-9 Illegal Instruction Exception ........................................................3-9 Privilege Violation .......................................................................3-9 Trace Exception .........................................................................3-9 Debug Interrupt ........................................................................3-10 RTE and Format Error Exceptions ...........................................3-10 TRAP Instruction Exceptions ....................................................3-10 Interrupt Exception ...................................................................3-10 USEROS MANUAL For More Information On This Product, Go to: www.freescale.com iii Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 3.5.10 3.5.11 3.6 3.6.1 3.6.2 Title Page Number Fault-on-Fault Halt ................................................................... 3-11 Reset Exception ....................................................................... 3-11 Instruction Execution Timing .............................................................. 3-11 Timing Assumptions ................................................................. 3-12 MOVE Instruction Execution Times ......................................... 3-12 Freescale Semiconductor, Inc... Section 4 Instruction Cache 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.4 4.4.1 4.4.2 4.4.2.1 4.4.2.2 Features Of Instruction Cache ............................................................. 4-1 Instruction Cache Physical Organization ............................................. 4-1 Instruction Cache Operation ................................................................ 4-2 Interaction With Other Modules .................................................. 4-3 Memory Reference Attributes .................................................... 4-3 Cache Coherency and Invalidation ............................................ 4-3 Reset .......................................................................................... 4-4 Cache Miss Fetch Algorithm/Line Fills ....................................... 4-4 Instruction Cache Programming Model ................................................ 4-5 Instruction Cache Registers Memory Map ................................. 4-5 Instruction Cache Register ......................................................... 4-6 Cache Control Register (CACR) ..................................... 4-6 Access Control Registers (ACR0, ACR1) ....................... 4-8 Section 5 SRAM 5.1 5.2 5.3 5.3.1 5.3.2 5.3.2.1 5.3.3 5.3.4 SRAM Features .................................................................................... 5-1 SRAM Operation .................................................................................. 5-1 Programming Model ............................................................................. 5-1 SRAM Register Memory Map .................................................... 5-1 SRAM Registers ......................................................................... 5-2 SRAM Base Address Register (RAMBAR) ..................... 5-2 SRAM Initialization ..................................................................... 5-3 Power Management ................................................................... 5-4 Section 6 Bus Operation 6.1 6.2 6.2.1 6.2.2 iv Features ............................................................................................... 6-1 Bus And Control Signals ...................................................................... 6-1 Address Bus (A[27:0]) ................................................................ 6-1 Data Bus (D[31:0]) ..................................................................... 6-2 USEROS MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.3 6.3.1 6.4 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 6.5.9 6.5.10 6.5.11 6.5.12 6.6 6.7 6.7.1 6.8 6.9 6.9.1 6.9.2 6.10 6.10.1 6.10.2 6.10.3 6.10.4 6.11 6.11.1 6.11.2 6.11.3 Title Page Number Transfer Start (TS) .....................................................................6-2 Read/Write (R/W) .......................................................................6-2 Size (SIZ[1:0]) ............................................................................6-2 Transfer Type (TT[1:0]) ..............................................................6-2 Access Type and Mode (ATM) ...................................................6-3 Asynchronous Transfer Acknowledge (ATA) .............................6-3 Transfer Acknowledge (TA) ........................................................6-4 Transfer Error Acknowledge (TEA) ............................................6-4 Bus Exceptions .....................................................................................6-5 Double Bus Fault ........................................................................6-5 Bus Characteristics ..............................................................................6-5 Data Transfer Mechanism ....................................................................6-6 Bus Sizing ..................................................................................6-7 Bursting Read Transfers: Word, Longword, and Line ..............6-15 Bursting Write Transfers: Word, Longword, and Line ..............6-18 Burst-Inhibited Read Transfer: Word, Longword, and Line ......6-21 Burst-Inhibited Write Transfer: Word, Longword, and Line ......6-24 Asynchronous-Acknowledge Read Transfer ............................6-27 Asynchronous Acknowledge Write Transfer ............................6-30 Bursting Read Transfers with Asynchronous Acknowledge .....6-32 Bursting Write Transfers with Asynchronous Acknowledge .....6-35 Burst-Inhibited Read Transfers with Async. Acknowledge .......6-39 Burst-Inhibited Write Transfers with Async. Acknowledge .......6-42 Termination Tied to GND .........................................................6-45 Misaligned Operands .........................................................................6-46 Acknowledge Cycles ..........................................................................6-47 Interrupt Acknowledge Cycle ....................................................6-48 Bus Errors ..........................................................................................6-51 Bus Arbitration ....................................................................................6-53 Two Master Bus Arbitration Protocol (Two-Wire Mode) ...........6-53 External Bus Master Arbitration Protocol (Three-Wire Mode) ...6-61 Alternate Bus Master Operation .........................................................6-67 Alternate Master Read Transfer (MCF5206 Termination).........6-68 Alternate Master Write Transfer (MCF5206 Termination) .........6-71 Alternate Master Bursting Read (MCF5206 Termination) ........6-73 Alternate Master Bursting Write (MCF5206 Termination) .........6-76 Reset Operation .................................................................................6-80 Master Reset ............................................................................6-80 Normal Reset ...........................................................................6-82 Software Watchdog Timer Reset Operation .............................6-83 Section 7 MOTOROLA USEROS MANUAL For More Information On This Product, Go to: www.freescale.com v Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Title Page Number Freescale Semiconductor, Inc... System Integration Module 7.1 7.1.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 7.3.1 7.3.2 7.3.2.1 7.3.2.2 7.3.2.3 7.3.2.4 7.3.2.5 7.3.2.6 7.3.2.7 7.3.2.8 7.3.2.9 7.3.2.10 Introduction .......................................................................................... 7-1 Features ..................................................................................... 7-1 SIM Operation ...................................................................................... 7-1 Module Base Address Register (MBAR) .................................... 7-1 Bus Time-Out Monitor ................................................................ 7-2 Spurious Interrupt Monitor .......................................................... 7-2 Software Watchdog Timer.......................................................... 7-3 Interrupt Controller ..................................................................... 7-3 Programming Model ............................................................................. 7-6 SIM Registers Memory Map ....................................................... 7-6 SIM Registers ............................................................................. 7-7 Module Base Address Register (MBAR) ........................ 7-7 SIM Configuration Register (SIMR) ................................ 7-9 Interrupt Control Register (ICR) ...................................... 7-9 Interrupt Mask Register (IMR) ...................................... 7-11 Interrupt-Pending Register (IPR) .................................. 7-12 Reset Status Register (RSR) ........................................ 7-13 System Protection Control Register (SYPCR) .............. 7-14 Software Watchdog Interrupt Vector Reg. (SWIVR)...... 7-15 Software Watchdog Service Register (SWSR) ............. 7-16 Pin Assignment Register (PAR) ................................... 7-16 Section 8 Chip-Select Module 8.1 8.1.1 8.2 8.2.1 8.2.1.1 8.2.1.2 8.2.1.3 8.2.1.4 8.2.1.5 8.3 8.3.1 8.3.1.1 8.3.1.2 8.3.1.3 vi Introduction .......................................................................................... 8-1 Features ..................................................................................... 8-1 Chip Select Module I/O ........................................................................ 8-1 Control Signals ........................................................................... 8-1 Chip Select (CS[7:0]) ...................................................... 8-1 Write Enable (WE[3:0]) ................................................... 8-1 Address Bus ................................................................... 8-3 Data Bus ......................................................................... 8-4 Transfer Acknowledge (TA) ............................................ 8-4 Chip Select Operation .......................................................................... 8-4 Chip Select Bank Definition ........................................................ 8-5 Base Address and Address Masking .............................. 8-5 Access Permissions ....................................................... 8-6 Control Features ............................................................. 8-6 USEROS MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 8.3.1.3.1 8.3.1.3.2 8.3.1.3.3 8.3.1.3.4 8.3.2 8.3.3 8.3.3.1 8.3.3.2 8.3.3.3 8.3.3.4 8.3.3.5 8.3.3.6 8.3.4 8.3.4.1 8.3.4.2 8.3.4.3 8.4 8.4.1 8.4.2 8.4.2.1 8.4.2.2 8.4.2.3 8.4.2.4 Title Page Number 8-, 16-, and 32-Bit Port Sizing ....................................................8-7 Termination ................................................................................8-7 Bursting Control ..........................................................................8-7 Address Setup and Hold Control ................................................8-8 Global Chip Select Operation .....................................................8-8 General Chip Select Operation ..................................................8-8 NonBurst Transfer with No Address Setup and Hold .....8-9 NonBurst Transfer with Address Setup ........................8-10 NonBurst Transfer With Address Setup and Hold ........8-12 Burst Transfer ...............................................................8-14 Burst Transfer With Address Setup ..............................8-16 Burst Transfer With Address Setup and Hold ...............8-18 Alternate Master Chip Select Operation ...................................8-21 Alternate Master NonBurst Transfer .............................8-21 Alternate Master Burst Transfer ....................................8-23 Alternate Master Burst Transfer With Address Setup and Hold .......................................................................................8-25 Programming Model ...........................................................................8-27 Chip Select Registers Memory Map......................................... 8-27 Chip Select Controller Registers ..............................................8-29 Chip Select Address Register (CSAR0 - CSAR7) ........8-29 Chip Select Mask Register (CSMR0 - CSMR7)............ 8-30 Chip Select Control Register (CSCR0 - CSCR7) .........8-32 Default MemoryControl Register (DMCR) ....................8-38 Section 9 Parallel Port (General-Purpose I/O) Module 9.1 9.2 9.3 9.3.1 9.3.2 9.3.2.1 9.3.2.2 Introduction ...........................................................................................9-1 Parallel Port Operation .........................................................................9-1 Programming Model .............................................................................9-1 Parallel Port Registers Memory Map ..........................................9-1 Parallel Port Registers ................................................................9-2 Port A Data Direction Register (PADDR) ........................9-2 Port A Data Register (PADAT) .......................................9-2 Section 10 DRAM Controller 10.1 10.1.1 10.2 MOTOROLA Introduction .........................................................................................10-1 Features ...................................................................................10-1 DRAM Controller I/O ..........................................................................10-1 USEROS MANUAL For More Information On This Product, Go to: www.freescale.com vii Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 10.2.1 10.2.1.1 10.2.1.2 10.2.1.3 10.2.2 10.2.3 10.3 10.3.1 10.3.1.1 10.3.1.2 10.3.2 10.3.2.1 10.3.2.2 10.3.2.3 10.3.2.4 10.3.2.5 10.3.2.6 10.3.3 10.3.3.1 10.3.3.2 10.3.4 10.3.4.1 10.3.4.2 10.3.4.3 10.3.4.4 10.3.4.5 10.3.5 10.3.6 10.3.7 10.3.8 10.3.8.1 10.3.8.2 10.3.8.3 10.3.8.4 10.4 10.4.1 10.4.2 10.4.2.1 10.4.2.2 10.4.2.3 10.4.2.4 viii Title Page Number Control Signals ......................................................................... 10-1 Row Address Strobes (RAS[0], RAS[1]) ....................... 10-1 Column Address Strobes (CAS[0:3])............................. 10-2 DRAM Write (DRAMW) ................................................ 10-3 Address Bus ............................................................................. 10-3 Data Bus .................................................................................. 10-4 DRAM Controller Operation ............................................................... 10-4 Reset Operation ....................................................................... 10-4 Master Reset ................................................................ 10-5 Normal Reset ................................................................ 10-5 Definition of DRAM Banks ........................................................ 10-5 Base Address and Address Masking ............................ 10-5 Access Permissions ..................................................... 10-7 Timing ........................................................................... 10-8 Page Mode ................................................................... 10-8 Port Size/Page Size ...................................................... 10-8 Address Multiplexing .................................................... 10-8 Normal Mode Operation ......................................................... 10-15 NonBurst Transfer In Normal Mode ............................ 10-16 Burst Transfer In Normal Mode .................................. 10-18 Fast Page Mode Operation .................................................... 10-20 Burst Transfer In Fast Page Mode ............................. 10-21 Page Hit Read Transfer In Fast Page Mode .............. 10-23 Page Hit Write Transfer in Fast Page Mode ............... 10-25 Page Miss Transfer in Fast Page Mode ..................... 10-27 Bus Arbitration ............................................................ 10-30 Burst Page Mode Operation ................................................... 10-32 Extended Data-Out (EDO) DRAM Operation ......................... 10-35 Refresh Operation .................................................................. 10-38 External Master Use of the DRAM Controller ........................ 10-40 External Master Non-Burst Transfer in Normal Mode ..................................................................................... 10-41 External Master Burst Transfer in Normal Mode ........ 10-44 External Master Burst Transfer in Burst Page Mode .. 10-47 Limitations .................................................................. 10-50 Programming Model ......................................................................... 10-51 DRAM Controller Registers Memory Map .............................. 10-51 DRAM Controller Registers .................................................... 10-51 DRAM Controller Refresh Register (DCRR) ............... 10-51 DRAM Controller Timing Register (DCTR) ................. 10-52 DRAM Controller Address Reg. (DCAR0 - DCAR1) ... 10-58 DRAM Controller Mask Reg. (DCMR0 - DCMR1) ....... 10-59 USEROS MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number Title Page Number 10.4.2.5 10.5 DRAM Controller Control Reg. (DCCR0 - DCCR1) .....10-60 DRAM Initialization Example ............................................................10-61 11.1 11.1.1 11.1.2 11.1.3 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.3 11.3.1 11.3.2 11.3.2.1 11.3.2.2 11.3.2.3 11.3.3 11.3.3.1 11.3.3.2 11.3.3.3 11.3.4 11.3.5 11.3.5.1 11.3.5.2 11.3.5.3 11.4 11.4.1 11.4.1.1 11.4.1.2 11.4.1.3 11.4.1.4 11.4.1.5 11.4.1.6 11.4.1.7 11.4.1.8 11.4.1.9 11.4.1.10 Section 11 UART Modules Module Overview.................................................................................11-2 Serial Communication Channel.................................................11-2 Baud-Rate Generator/Timer......................................................11-3 Interrupt Control Logic...............................................................11-3 UART Module Signal Definitions .........................................................11-3 Transmitter Serial Data Output (TxD)........................................11-3 Receiver Serial Data Input (RxD) ..............................................11-4 Request-to-Send (RTS).............................................................11-4 Clear-to-Send (CTS) .................................................................11-4 Operation.............................................................................................11-5 Baud-Rate Generator/Timer......................................................11-5 Transmitter and Receiver Operating Modes .............................11-6 Transmitter.....................................................................11-6 Receiver.........................................................................11-9 FIFO Stack...................................................................11-11 Looping Modes........................................................................11-12 Automatic Echo Mode..................................................11-12 Local Loopback Mode..................................................11-12 Remote Loopback Mode..............................................11-13 Multidrop Mode........................................................................11-14 Bus Operation .........................................................................11-16 Read Cycles ................................................................11-16 Write Cycles.................................................................11-16 Interrupt Acknowledge Cycles .....................................11-16 Register Description and Programming ............................................11-16 Register Description ................................................................11-16 Mode Register 1 (UMR1).............................................11-17 Mode Register 2 (UMR2).............................................11-19 Status Register (USR) .................................................11-21 Clock Select Register (UCSR).....................................11-24 Command Register (UCR)...........................................11-24 Receiver Buffer (URB) .................................................11-27 Transmitter Buffer (UTB) .............................................11-28 Input Port Change Register (UIPCR)...........................11-28 Auxiliary Control Register (UACR)...............................11-29 Interrupt Status Register (UISR)..................................11-29 MOTOROLA USEROS MANUAL For More Information On This Product, Go to: www.freescale.com ix Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 11.4.1.11 11.4.1.12 11.4.1.13 11.4.1.14 11.4.1.14.1 11.4.1.14.2 11.4.2 11.4.2.1 11.4.2.2 11.4.2.3 11.5 Title Page Number Interrupt Mask Register (UIMR)................................... 11-30 Timer Upper Preload Register 1 (UBG1)..................... 11-31 Timer Upper Preload Register 2 (UBG2)..................... 11-31 Interrupt Vector Register (UIVR) ................................. 11-31 Input Port Register (UIP)......................................................... 11-32 Output Port Data Registers (UOP1, UOP0) ............................ 11-32 Programming........................................................................... 11-33 UART Module Initializatin ............................................ 11-33 I/O Driver Example ...................................................... 11-33 Interrupt Handling ........................................................ 11-33 UART Module Initialization Sequence............................................... 11-34 Section 12 M-Bus Module 12.1 12.2 12.3 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.4.6 12.4.7 12.4.8 12.4.9 12.5 12.5.1 12.5.2 12.5.3 12.5.4 12.5.5 12.6 12.6.1 12.6.2 12.6.3 12.6.4 12.6.5 12.6.6 12.6.7 x Overview ............................................................................................ 12-1 Interface Features .............................................................................. 12-1 M-Bus System Configuration ............................................................. 12-2 M-Bus Protocol ................................................................................... 12-3 START Signal .......................................................................... 12-3 Slave Address Transmission .................................................... 12-3 Data Transfer ........................................................................... 12-4 Repeated START Signal .......................................................... 12-4 STOP Signal ............................................................................ 12-4 Arbitration Procedure ............................................................... 12-4 Clock Synchronization .............................................................. 12-5 Handshaking ............................................................................ 12-5 Clock Stretching ....................................................................... 12-5 Programming Model ........................................................................... 12-6 M-Bus Address Register (MADR). ........................................... 12-6 M-Bus Frequency Divider Register (MFDR) ............................ 12-6 M-Bus Control Register (MBCR) .............................................. 12-8 M-Bus Status Register (MBSR) ............................................... 12-9 M-Bus Data I/O Register (MBDR) .......................................... 12-11 M-Bus Programming Examples ....................................................... 12-11 Initialization Sequence ........................................................... 12-11 Generation of START ............................................................. 12-11 Post-Transfer Software Response ......................................... 12-12 Generation of STOP ............................................................... 12-14 Generation of Repeated START ............................................ 12-14 Slave Mode ............................................................................ 12-15 Arbitration Lost ....................................................................... 12-15 USEROS MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Title Page Number Freescale Semiconductor, Inc... Section 13 Timer Module 13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.4 13.4.1 13.4.1.1 13.4.1.2 13.4.1.3 13.4.1.4 13.4.1.5 Overview of the Timer Module ...........................................................13-1 Overview of Key Features ..................................................................13-1 Understanding the General-Purpose Timer Units ..............................13-2 Selecting the Prescaler ............................................................13-3 Working with Capture Mode .....................................................13-3 Configuring the Timer for Reference Compare ........................13-3 Configuring the Timer for Output Mode ....................................13-3 Interrupts ...................................................................................13-3 Programming Model ...........................................................................13-4 Understanding the General-Purpose Timer Registers .............13-4 Timer Mode Register (TMR) .........................................13-5 Timer Reference Register (TRR) ..................................13-6 Timer Capture Register (TCR) ......................................13-6 Timer Counter (TCN) ....................................................13-6 Timer Event Register (TER) .........................................13-7 14.1 14.2 14.2.1 14.2.2 14.2.3 14.2.3.1 14.2.3.2 14.2.3.3 14.2.3.4 Section 14 Debug Support Real-Time Trace..................................................................................14-1 Background Debug Mode....................................................................14-4 CPU Halt ...................................................................................14-5 BDM Serial Interface .................................................................14-6 BDM Command Set ..................................................................14-7 BDM Command Set Summary ......................................14-7 ColdFire BDM Commands.............................................14-8 Command Sequence Diagram ......................................14-9 Command Set Descriptions .........................................14-10 MOTOROLA USEROS MANUAL For More Information On This Product, Go to: www.freescale.com xi Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Freescale Semiconductor, Inc... Paragraph Number 14.2.3.4.1 14.2.3.4.2 14.2.3.4.3 14.2.3.4.4 14.2.3.4.5 14.2.3.4.6 14.2.3.4.7 14.2.3.4.8 14.2.3.4.9 14.2.3.4.10 14.2.3.4.11 14.2.3.4.12 14.2.3.4.13 14.3 14.3.1 14.3.1.1 14.3.1.2 14.3.1.3 14.3.1.4 14.3.1.5 14.3.1.6 14.3.2 14.3.2.1 14.3.3 14.4 14.4.1 Title Page Number Read A/D Register (RAREG/RDREG) .................................... 14-11 Write A/D Register (WAREG/WDREG)................................... 14-12 Read Memory Location (READ).............................................. 14-13 Write Memory Location (WRITE) ............................................ 14-15 Dump Memory Block (DUMP)................................................. 14-17 Fill Memory Block (FILL) ......................................................... 14-20 Resume Execution (GO) ......................................................... 14-21 No Operation (NOP)................................................................ 14-22 Read Control Register (RCREG) ............................................ 14-22 Write Control Register (WCREG)............................................ 14-24 Read Debug Module Register (REMREG).............................. 14-24 Write Debug Module Register (WDMREG)............................. 14-25 Unassigned Opcodes.............................................................. 14-26 Real-Time Debug Support ................................................................ 14-27 Programming Model................................................................ 14-27 Address Breakpoint Registers (ABLR, ABHR) ............ 14-28 Address Attribute Breakpoint Register (AATR) ........... 14-28 Program Counter Breakdown Register (PBR, PBMR) 14-30 Data Breakpoint Register (DBR, DBMR)..................... 14-30 Trigger Definition Register (TDR) ................................ 14-31 Configuration/Status Register (CSR)........................... 14-33 Theory of Operation ................................................................ 14-35 Reuse of Debug Module Hardware ............................. 14-37 Concurrent BDM and Processor Operation ............................ 14-37 Motorola Recommended BDM Pinout............................................... 14-38 Differences Between the ColdFire BDM and a CPU32 BDM.. 14-38 Section 15 IEEE 1149.1 Test Access Port (JTAG) 15.1 15.2 15.3 15.3.1 15.3.1.1 15.3.1.2 15.3.1.3 15.3.1.4 15.3.1.5 15.3.1.6 15.3.2 15.3.3 xii Overview ............................................................................................ 15-2 JTAG Pin Descriptions ....................................................................... 15-2 JTAG Register Descriptions ............................................................... 15-3 JTAG Instruction Shift Register ............................................... 15-3 EXTEST Instruction ...................................................... 15-3 ID Code ........................................................................ 15-4 SAMPLE/PRELOAD Instruction ................................... 15-4 HIGHZ Instruction ......................................................... 15-4 CLAMP Instruction ........................................................ 15-5 BYPASS Instruction ...................................................... 15-5 ID Code Register ...................................................................... 15-5 JTAG Boundary-Scan Register ................................................ 15-6 USEROS MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Freescale Semiconductor, Inc... 15.3.4 15.4 15.5 15.6 15.7 15.8 Title Page Number JTAG Bypass Register ...........................................................15-10 TAP Controller ..................................................................................15-10 Restrictions .......................................................................................15-12 Disabling the IEEE 1149.1 Standard Operation ...............................15-12 Motorola MCF5206 BSDL Description .............................................15-13 Obtaining the IEEE 1149.1 Standard ...............................................15-13 Section 16 Electrical Characteristics 16.1 16.1.1 16.1.2 16.1.3 16.1.4 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 16.3.8 16.3.9 16.3.10 16.3.11 16.3.12 16.3.12.1 16.3.12.2 16.3.12.3 16.3.13 16.3.14 16.3.15 16.3.16 16.3.17 Maximum Ratings ...............................................................................16-1 Supply, Input Voltage and Storage Temperature .....................16-1 Operating Temperature ............................................................16-1 Thermal Resistance .................................................................16-2 Output Loading .........................................................................16-2 DC Electrical Specifications ...............................................................16-2 AC Electrical Specifications ................................................................16-3 Clock Input Timing Specifications ............................................16-3 Clock Input Timing Diagram .....................................................16-3 Processor Bus Input Timing Specifications ..............................16-4 Input Timing Waveform Diagram ..............................................16-4 Processor Bus Output Timing Specifications ...........................16-5 Output Timing Waveform Diagram ...........................................16-6 Processor Bus Timing Diagrams ..............................................16-7 Timer Module AC Timing Specifications ................................16-13 Timer Module Timing Diagram ...............................................16-13 UART Module AC Timing Specifications ................................16-14 UART Module Timing Diagram ..............................................16-14 M-Bus Module AC Timing Specifications ...............................16-15 Input Timing Specifications Between SCL and SDA ...16-15 Output Timing Specifications Between SCL and SDA 16-15 Timing Specifications Between CLK and SCL, SDA ...16-16 M-Bus Module Timing Diagram ..............................................16-16 General Purpose I/O Port AC Timing Specifications ..............16-17 General Purpose I/O Port Timing Diagram ............................16-17 IEEE 1149.1 (JTAG) AC Timing Specifications ......................16-18 IEEE 1149.1 (JTAG) Timing Diagram ....................................16-18 Section 17 Mechanical Data MOTOROLA USEROS MANUAL For More Information On This Product, Go to: www.freescale.com xiii Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Title Page Number Appendix A McF5206 Memory Map Summary Freescale Semiconductor, Inc... Appendix B Porting From M68K Architecture B.1 B.2 B.3 B.4 B.5 xiv C Compilers and Host Software........................................................... B-1 Target Software Port ............................................................................B-1 Initialization Code .................................................................................B-2 Exception Handlers ..............................................................................B-2 Supervisor Registers ............................................................................B-3 USEROS MANUAL For More Information On This Product, Go to: www.freescale.com MOTOROLA Date: 8-31-98 Freescale Semiconductor, Inc. Revision No.: 1.1 Pages affected: See change bars LIST OF ILLUSTRATIONS Freescale Semiconductor, Inc... Figure Number Title Page Number 1-1. 1-2. MCF5206 Block Diagram ................................................................................. 1-4 Programming Model......................................................................................... 1-7 3-1. 3-2. 3-3. 3-4. 3-5. ColdFire Processor Core Pipelines .................................................................. 3-1 User Programming Model ................................................................................3-3 Supervisor Programming Mode ....................................................................... 3-4 Status Register................................................................................................. 3-4 Exception Stack Frame Form........................................................................... 3-7 4-1. Instruction Cache Block Diagram......................................................................4-2 6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 6-7. 6-8. 6-9. 6-10. 6-11. 6-12. 6-13. 6-14. 6-15. Signal Relationships to CLK............................................................................. 6-6 Internal Operand Representation..................................................................... 6-7 MCF5206 Interface to Various Port Sizes........................................................ 6-8 Byte-, Word-, and Longword-Read Transfer Flowchart ................................. 6-10 Longword-Read Transfer From a 32-Bit Port (No Wait States) ..................... 6-11 Byte-, Word-, and Longword-Write Transfer Flowchart ..................................6-13 Word-Write Transfer to a 16-Bit Port (No Wait States) .................................. 6-14 Bursting Word-, Longword-, and Line-Read Transfer Flowchart.................... 6-16 Bursting Word-Read From an 8-Bit Port (No Wait States)............................. 6-17 Word-, Longword-, and Line-Write Transfer Flowchart ...................................6-19 Line-Write Transfer to a 32-Bit Port (No Wait States) ....................................6-20 Burst-Inhibited Word-, Longword-, and Line-Read Transfer Flowchart.......... 6-22 Burst-Inhibited Longword Read From an 8-Bit Port (No Wait States) ............6-23 Burst-Inhibited Byte-, Word-, and Longword-Write Transfer Flowchart .........6-25 Burst-Inhibited Longword-Write Transfer to a 16-Bit Port (No Wait States) .............................................................................................6-26 Byte-, Word-, and Longword-Read Transfer with Asynchronous Termination Flowchart (One Wait State) ...................................................................................6-28 Byte-Read Transfer from an 8-Bit Port Using Asynchronous Termination (One Wait State) .............................................................................................................6-29 Byte-, Word-, and Longword-Write Transfer with Asynchronous Termination Flowchart ...............................................................................................................6-30 Byte-Write Transfer to a 32-Bit Port Using Asynchronous Termination (One Wait State) .............................................................................................................6-31 6-16. 6-17. 6-18. 6-19. MOTOROLA MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com xv Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 6-20. Bursting Word-, Longword-, and Line-Read Transfer with Asynchronous Termination Flowchart ....................................................................................................... 6-33 6-21. Bursting Longword-Read from 16-Bit Port Using Asynchronous Termination (One Wait State) ..................................................................................................... 6-34 6-22. Word-, Longword-, and Line-Write Transfer Flowchart with Asynchronous Termination ................................................................................................................. 6-36 6-23. Bursting Line-Write from 32-Bit Port Using Asynchronous Termination (One Wait State) ............................................................................................................. 6-37 6-24. Burst-Inhibited Word-, Longword-, and Line-Read Transfer with Asynchronous Termination Flowchart ......................................................................................... 6-40 6-25. Burst-Inhibited Word Read from 8-Bit Port Using Asynchronous Termination ..... ........................................................................................................................ 6-41 6-26. Burst-Inhibited Word-, Longword-, and Line-Write Transfer with Asynchronous Termination Flowchart ......................................................................................... 6-43 6-27. Burst-Inhibited Longword-Write Transfer to 16-Bit Port Using Asynchronous Termination (One Wait State) ................................................................................. 6-44 6-28. Example of a Misaligned Longword Transfer ................................................. 6-46 6-29. Example of a Misaligned Word Transfer........................................................ 6-46 6-30. Interrupt-Acknowledge Cycle Flowchart ........................................................ 6-49 6-31. Interrupt Acknowledge Bus Cycle Timing (No Wait States) ........................... 6-50 6-32. Bursting Longword-Read Access from 16-Bit Port Terminated with TEA Timing ........................................................................................................................ 6-52 6-33. MCF5206 Two-Wire Mode Bus Arbitration Interface ..................................... 6-54 6-34. Two-Wire Implicit and Explicit Bus Ownership............................................... 6-56 6-35. Two-Wire Bus Arbitration with Bus Lock Negated ......................................... 6-57 6-36. Two-Wire Bus Arbitration with Bus Lock Bit Asserted ................................... 6-58 6-37. MCF5206 Two-Wire Bus Arbitration Protocol State Diagram ........................ 6-59 6-38. Three-Wire Implicit and Explicit Bus Ownership ............................................ 6-62 6-39. Three-Wire Bus Arbitration with Bus Lock Bit Asserted ................................. 6-64 6-40. MCF5206 Bus Arbitration Protocol State Diagram ........................................ 6-65 6-41. Alternate Master Read Transfer using MCF5206-Generated Transfer Acknowledge Flowchart ................................................................... 6-69 6-42. Alternate Master Read Transfer Using MCF5206 Transfer Acknowledge Timing (No Wait States) ................................................................................................... 6-70 6-43. Alternate Master Write Transfer Using MCF5206-Generated Transfer Acknowledge Flowchart ................................................................... 6-71 6-44. Alternate Master Write Transfer Using MCF5206 Transfer-Acknowledge Timing (No Wait States) ................................................................................................... 6-72 6-45. Alternate Master Bursting Read Transfer Using MCF5206-Generated Transfer-Acknowledge Flowchart ..................................................................................... 6-74 6-46. Alternate Master Bursting Longword Read Transfer to an 8-Bit Port Using MCF5206 Transfer-Acknowledge Timing (No Wait States) ............................................ 6-75 xvi MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Number Title Page Number Freescale Semiconductor, Inc... 6-47. Alternate Master Bursting Write Transfer using MCF5206-Generated Transfer-Acknowledge Flowchart .....................................................................................6-78 6-48. Alternate Master Bursting Longword Write Transfer to a 16-Bit Port Using MCF5206 Transfer Acknowledge Timing (No Wait States) ............................................6-79 6-49. Master Reset Timing ......................................................................................6-81 6-50. Normal Reset Timing .....................................................................................6-82 6-51. Software Watchdog Timer Reset Timing .......................................................6-83 8-1. 8-2. 8-3. 8-4. 8-5. 8-6. 8-7. 8-8. 8-9. 8-10. 8-11. 8-12. 8-13. 8-14. 8-15. 8-16. 8-17. 8-18. 8-19. 8-20. MCF5206 Interface to Various Port Sizes ........................................................8-4 Longword Write Transfer from a 32-Bit Port (No Wait State, No Address Setup, No Address Hold) ..................................................................................................8-9 Word Write Transfer to a 16-Bit Port (One Wait State, Address Setup, No Address Hold) ...............................................................................................................8-11 Byte Write Transfer from an 8-Bit Port (One Wait State, Address Setup, Address Hold) ...............................................................................................................8-13 Longword Burst Read Transfer from a 16-Bit Port (No Wait States, No Address Setup, No Address Hold) ............................................................8-15 Longword Burst Read Transfer from a 16-Bit Port (No Wait States, Address Setup, No Address Hold) ...........................................................................................8-17 Word Burst Read Transfer from an 8-Bit Port (No Wait States, Address Setup, Address Hold) .....................................................................................................8-19 Alternate Master Longword Read Transfer from a 32-Bit Port (No Wait State, No Address Setup, No Address Hold) ......................................................................8-22 Alternate Master Longword Read Transfer from a 16-bit Port (no wait state, no address setup, no address hold) ........................................................................8-24 Alternate Master Longword Read Transfer from a 16-Bit Port (No Wait State, With Address Setup Or Read Address Hold) .........................................................8-26 Chip-Select and Write-Enable Assertion with ASET = 0 Timing ....................8-35 Chip-Select and Write-Enable Assertion with ASET = 1Timing .....................8-35 Address Hold Timing with WRAH = 0 ............................................................8-36 Address Hold Timing with WRAH = 1 ............................................................8-36 Address Hold Timing with RDAH = 0 .............................................................8-37 Address Hold Timing with RDAH = 1 .............................................................8-38 Default Memory Address Hold Timing with WRAH = 0 ..................................8-41 Default Memory Address Hold Timing with WRAH = 1 ..................................8-42 Default Memory Address Hold Timing with RDAH = 0 ...................................8-43 Default Memory Address Hold Timing with RDAH = 1 ...................................8-43 10-1. MCF5206 Interface to Various Port Sizes...................................................... 10-4 10-2. Address Multiplexing For 8-bit DRAM With 512 byte Page Size.................... 10-9 10-3. Connection Diagram for 4 MByte DRAM with 8-bit Port and 1 KByte Page 10-15 MOTOROLA MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com xvii Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Number 10-4. 10-5. 10-6. 10-7. 10-8. Page Number 10-17. 10-18. 10-19. 10-20. 10-21. 10-22. Connection Diagram for 1MByte DRAM with 8-bit Port and 1 KByte Page . 10-15 Byte Read Transfers in Normal Mode with 8-bit DRAM ............................... 10-17 Longword Write Transfer in Normal Mode with 16-bit DRAM ...................... 10-19 Word Write Transfer in Fast Page Mode with 8-bit DRAM .......................... 10-22 Longword Read Transfer Followed by a Page Hit Longword Read Transfer in Fast Page Mode with 32-bit DRAM ...................................................................... 10-24 Word Write Transfer Followed by a Page Hit Word Write Transfer in Fast Page Mode with 16-bit DRAM ......................................................................................... 10-26 Byte Read Transfer Followed by a Page Miss Byte Read Transfer in Fast Page Mode with 8-bit DRAM ........................................................................................... 10-28 Bus Arbitration in Fast Page Mode .............................................................. 10-31 Longword Write Transfer Followed by a Word Read Transfer in Burst Page Mode with 16-bit DRAM ......................................................................................... 10-33 Word Read Transfer Followed by a Page Miss Byte Read Transfer in Fast Page Mode with 8-bit EDO DRAM ........................................................................ 10-36 Alternate Master Byte Read Transfer Followed by Byte Write Transfer in Normal Mode with 16-bit DRAM ............................................................................... 10-42 Alternate Master Longword Write Transfer in Normal Mode with 16-bit DRAM ...................................................................................................................... 10-45 Alternate Master Word Read Transfer in Burst Page Mode with 8-bit DRAM ...................................................................................................................... 10-48 Normal Mode DRAM Transfer Timing .......................................................... 10-54 Fast Page Mode or Burst Page Mode DRAM Transfer Timing .................... 10-54 Fast Page Mode or Burst Page Mode DRAM Transfer Timing .................... 10-55 Fast Page Mode Page Hit and Page Miss DRAM Transfer Timing ............. 10-56 Fast Page Mode or Burst Page Mode EDO DRAM Transfer Timing ........... 10-57 CAS before RAS Refresh Cycle Timing ....................................................... 10-58 11-1. 11-2. 11-3. 11-4. 11-5. 11-6. 11-7. 11-8. 11-9. UART Block Diagram...................................................................................... 11-1 External and Internal Interface Signals ........................................................... 11-4 Baud-Rate Timer Generator Diagram............................................................. 11-5 Transmitter and Receiver Functional Diagram ............................................... 11-7 Transmitter Timing Diagram ........................................................................... 11-8 Receiver Timing Diagram ............................................................................. 11-10 Looping Modes Functional Diagram ............................................................. 11-13 Multidrop Mode Timing Diagram................................................................... 11-15 UART Software Flowchart ............................................................................ 11-35 10-9. Freescale Semiconductor, Inc... Title 10-10. 10-11. 10-12. 10-13. 10-14. 10-15. 10-16. xviii MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Number 12-1. 12-2. 12-3. 12-4. Title Page Number M-Bus Module Block Diagram.........................................................................12-2 M-Bus Standard Communication Protocol ......................................................12-3 Synchronized Clock SCL ................................................................................12-5 Flow-Chart of Typical M-Bus Interrupt Routine ............................................12-16 Freescale Semiconductor, Inc... 13-1. Timer Block Diagram Module Operation ........................................................13-2 14-1. 14-2. 14-3. 14-4. 14-5. 14-6. 14-7. Processor/Debug Module Interface.................................................................14-1 Pipeline Timing Example (Debug Output).......................................................14-3 BDM Signal Sampling .....................................................................................14-6 Command Sequence Diagram......................................................................14-10 Debug Programming Model ..........................................................................14-27 26-pin Berg Connector Arranged 2 x 13 .......................................................14-38 Serial Transfer Illustration .............................................................................14-39 15-1. 15-2. 15-3. 15-4. JTAG Test Logic Block Diagram ....................................................................15-2 JTAG TAP Controller State Machine ...........................................................15-11 Disabling JTAG in JTAG mode ....................................................................15-12 Disabling JTAG in Debug Mode ...................................................................15-13 17-1. MCF5206 Pin-out ........................................................................................... 17-2 MOTOROLA MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com xix Date: 8-31-98 Revision No.: 1.1 Freescale Semiconductor, Inc. Pages affected: See change bars LIST OF TABLES Freescale Semiconductor, Inc... Table Number Title Page Number 1-1. 1-2. 1-3. 1-4. 1-5. 1-6. 1-7. ColdFire MCF5206 Data Formats ...................................................................1-8 ColdFire Effective Addressing Modes ............................................................. 1-9 Specific Effective Addressing Modes .............................................................. 1-9 MOVE Specific Effective Addressing Modes .................................................. 1-9 Notational Conventions ................................................................................. 1-10 Supervisor-Mode Instruction Summary......................................................... 1-12 User-Mode Instruction Summary .................................................................. 1-12 2-1. 2-2. 2-3. 2-4. 2-5. 2-6. 2-7. 2-8. 2-9. 2-10. 2-11. MCF5206 Signal Index.................................................................................... 2-2 Address Bus ....................................................................................................2-3 Byte Write-Enable Signals .............................................................................. 2-6 Boot CS[0] Automatic Acknowledge (AA) Enable ........................................... 2-8 Interrupt Request Encodings for CS[0] ...........................................................2-8 Data Transfer Size Encoding .......................................................................... 2-9 Bus Cycle Transfer Type Encoding .................................................................2-9 ATM Encoding................................................................................................. 2-9 CAS Assertion............................................................................................... 2-13 Processor Status Encodings ......................................................................... 2-17 MCF5206 Signal Summary ........................................................................... 2-20 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. 3-7. 3-8. 3-9. 3-10. 3-11. Exception Vector Assignments ....................................................................... 3-7 Format Field Encodings .................................................................................. 3-8 Fault Status Encodings ...................................................................................3-8 Misaligned Operand References................................................................... 3-12 Move Byte and Word Execution Times ..........................................................3-13 Move Long Execution Times......................................................................... 3-13 One Operand Instruction Execution Times ................................................... 3-14 Two Operand Instruction Execution Times ................................................... 3-15 Miscellaneous Instruction Execution Times .................................................. 3-16 General Branch Instruction Execution Times................................................ 3-17 BRA, Bcc Instruction Execution Times.......................................................... 3-17 4-1. 4-2. 4-3. 4-4. Initial Fetch Offset vs. CLNF Bits .................................................................... 4-4 Instruction Cache Operation as Defined by CACR[31,10] .............................. 4-5 Memory Map of I-Cache Registers .................................................................4-6 External Fetch Size Based on Miss Address and CLNF................................. 4-8 MOTOROLA MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com xxi Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 5-1. 5-2. Memory Map of SIM Registers ....................................................................... 5-2 Examples of Typical RAMBAR Settings ......................................................... 5-4 6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 6-7. 6-8. 6-9. 6-10. 6-11. 6-12. 6-13. 6-14. SIZx Encoding................................................................................................. 6-2 Transfer Type Encoding.................................................................................. 6-3 ATM Encoding ................................................................................................ 6-3 Chip Select, DRAM and Default Memory Address Decoding Priority ............. 6-7 SIZx Encoding for Burst- and Bursting-Inhibited Ports ................................... 6-9 Address Offset Encoding ................................................................................ 6-9 Data Bus Requirement for Read Cycles ......................................................... 6-9 Internal to External Data Bus Multiplexer - Write Cycle ................................ 6-12 SIZx Encoding for Burst- and Bursting-Inhibited Ports ................................. 6-18 MCF5206 Two-Wire Bus Arbitration Protocol Transition Conditions ............ 6-59 MCF5206 Two-Wire Arbitration Protocol State Diagram .............................. 6-60 MCF5206 Three-Wire Bus Arbitration Protocol Transition Conditions.......... 6-65 MCF5206 Three-Wire Arbitration Protocol State Diagram............................ 6-66 Signal Source During Alternate Master Accesses ........................................ 6-68 7-1. 7-2. 7-3. 7-4. 7-5. Interrupt Levels for Encoded External Interrupts ............................................ 7-4 Interrupt Control Register Assignments ........................................................ 7-10 Interrupt Mask Register Bit Assignments...................................................... 7-11 Interrupt Pending Register Bit Assignments ................................................. 7-12 PAR3 - PAR0 Pin Assignment ...................................................................... 7-17 8-1. 8-2. 8-3. 8-4. 8-5. 8-6. 8-7. 8-8. 8-9. Data Bus Byte Write-Enable Signals .............................................................. 8-2 Maximum Memory Bank Sizes ....................................................................... 8-4 Chip-select, DRAM and Default Memory Address Decoding Priority ............. 8-6 Memory Map of Chip-select Registers.......................................................... 8-27 BA Field Comparisons for Alternate Master Transfers ................................. 8-29 IRQ4 and IRQ1 Selection of CS[0] Port Size................................................. 8-32 IRQ7 Selection of CS[0] Acknowledge Generation....................................... 8-32 Port Size Encodings...................................................................................... 8-34 Port Size Encodings...................................................................................... 8-40 9-1. 9-2. Data Direction Register Bit Assignments ........................................................ 9-2 Data Register Bit Assignments ....................................................................... 9-3 10-1. 10-2. 10-3. 10-4. 10-5. CAS Assertion............................................................................................... 10-2 Maximum DRAM Bank Sizes......................................................................... 10-3 DRAM Bank Programming Example 1 .......................................................... 10-6 Chip-select, DRAM and Default Memory Address Decoding Priority ........... 10-7 DRAM Bank Programming Example 2 .......................................................... 10-8 xxii MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Freescale Semiconductor, Inc... Figure Number Title Page Number 10-6. 10-7. 10-8. 10-9. 10-10. 8-bit Port Size Address Multiplexing Configurations ...................................10-11 16-bit Port Size Address Multiplexing Configurations .................................10-12 32-bit Port Size Address Multiplexing Configurations .................................10-13 Bank Page Size Versus Actual DRAM Page Size ......................................10-14 Memory Map of DRAM Controller Registers ...............................................10-51 11-1. 11-2. 11-3. 11-4. 11-5. 11-6. 11-7. 11-8. 11-9. 11-10. UART Module Programming Model .............................................................11-17 PMx and PT Control Bits..............................................................................11-19 B/CX Control Bits .........................................................................................11-19 CMx Control Bits ..........................................................................................11-19 SBx Control Bits ...........................................................................................11-21 RCSx Control Bits ........................................................................................11-24 TCSx Control Bits.........................................................................................11-24 MISCx Control Bits.......................................................................................11-25 TCx Control Bits ...........................................................................................11-26 RCx Control Bits...........................................................................................11-27 12-1. 12-2. M-Bus Interface ProgrammerOs Model ..........................................................12-6 MBUS Prescalar Values ................................................................................12-7 13-1. Programming Model for Timers .....................................................................13-3 14-1. 14-2. 14-3. 14-4. 14-5. 14-6. 14-7. 14-8. 14-9. 14-10. 14-11. 14-12. 14-13. 14-14. Processor PST Definition ...............................................................................14-2 CPU-Generated Message Encoding..............................................................14-7 BDM Command Summary .............................................................................14-7 BDM Size Field Encoding ..............................................................................14-8 Control Register Map ...................................................................................14-23 Definition of DRc Encoding - Read ..............................................................14-25 Definition of DRc Encoding - Write...............................................................14-26 SZ Encodings...............................................................................................14-29 Transfer Type Encodings .............................................................................14-29 Transfer Modifier Encodings for Normal Transfers ......................................14-30 Transfer Modifier Encodings for Alternate Access Transfers.......................14-30 Core Address, Access Size, and Operand Location ....................................14-31 DDATA, CSR[31:28] Breakpoint Response .................................................14-36 Shared BDM/Breakpoint Hardware..............................................................14-37 15-1. 15-2. 15-3. JTAG Pin Descriptions ..................................................................................15-3 JTAG Instructions ..........................................................................................15-3 Boundary Scan Bit Definitions .......................................................................15-6 A--1. MCF5206 User Programming Model ............................................................. A-1 MOTOROLA MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com xxiii Freescale Semiconductor, Inc. DATE: 9-1-98 REVISION NO.: 0.1 PAGES AFFECTED: SEE CHANGE BARS 1 Freescale Semiconductor, Inc... 2 SECTION 1 INTRODUCTION 3 1.1 BACKGROUND 4 The MCF5206 integrated microprocessor combines a ColdFire processor core with several peripheral functions such as a DRAM controller, timers, general-purpose I/O and serial interfaces, debug module, and system integration. Designed for embedded control applications, the ColdFire core delivers enhanced performance while maintaining low system costs. To speed program execution, the on-chip instruction cache and SRAM provide one-cycle access to critical code and data. The MCF5206 greatly reduces the time required for system design and implementation by packaging common system functions onchip and providing glueless interfaces to 8-, 16-, and 32-bit DRAM, SRAM, ROM, and I/O devices. The revolutionary ColdFire microprocessor architecture gives cost-sensitive, high-volume applications new levels of price and performance. Based on the concept of variable-length RISC technology, ColdFire combines the architectural simplicity of conventional 32-bit RISC with a memory-saving, variable-length instruction set. The denser binary code for ColdFire processors consumes less valuable memory than any fixed-length instruction set RISC processor available. This improved code density means more efficient system memory use for a given application and requires slower, less costly memory to help achieve a target performance level. The integrated peripheral functions provide high performance and flexibility: The DRAM controller supports as much as 512 Mbytes of DRAM; support for both page-mode and extended-data-out DRAMs; programmable full duplex DUART and a separate I2C1compatible Motorola bus (M-Bus interface). Two 16-bit general-purpose multimode timers provide separate input and output signals. For system protection, the processor includes a programmable 16-bit software watchdog timer and several bus monitors. In addition, common system functions such as chip-selects, interrupt control, bus arbitration, and IEEE 1149.1 Test (JTAG) support are included. A sophisticated debug interface supports both background-debug mode and real-time trace. This interface is common to all ColdFire-based processors and allows common emulator support across the entire ColdFire family. 1.2 MCF5206 FEATURES The primary features of the MCF5206 integrated processor include the following: 1. 6 7 8 9 10 11 12 13 14 15 I2C is a trademark of Phillips. MOTOROLA 5 16 MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com 1-1 Freescale Semiconductor, Inc. Introduction ColdFire Processor Core N N N N N N N N N N 2 3 Freescale Semiconductor, Inc... 4 Variable-length RISC 32-bit internal address bus with 28 bit external bus Chip Select and DRAM internal 32-bit decoding 32-bit data bus 16 user-visible 32-bit wide registers Supervisor / User modes for system protection Vector base register to relocate exception-vector table Optimized for high-level language constructs 17 MIPS at 33 MHz 512 Byte Direct-mapped instruction cache 512 Byte on-chip SRAM N Provides one-cycle access to critical code and data 6 DRAM Controller N N N N 7 8 Programmable refresh timer provides CAS-before-RAS refresh Support for 2 separate memory banks Support for page-mode DRAMs and extended-data-out (EDO) DRAMs Allows external bus master access Dual Universal Synchronous/Asynchronous Receiver/Transmitter (DUART) N N N N 9 1 Full duplex operation Baud-rate generator Modem control signals available (CTS, RTS) Processor-interrupt capability Dual 16-Bit General-Purpose Multimode Timers N N N N 11 12 Motorola Bus (M-Bus) Module N N N N 13 14 8-bit prescaler Timer input and output pins 30ns resolution with 33 MHz system clock Processor-interrupt capability Interchip bus interface for EEPROMs, LCD controllers, A/D converters, keypads Compatible with industry-standard I2C Bus Master or slave modes support multiple masters Automatic interrupt generation with programmable level System Interface N N N N N 15 16 1-2 Glueless bus interface to 8-, 16-, and 32-bit DRAM, SRAM, ROM, and I/O devices 8 programmable chip-select signals Programmable wait states and port sizes Allows external bus masters to access chip-selects System protection MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Introduction Freescale Semiconductor, Inc... 16-bit software watchdog timer with prescaler Double bus fault monitor Bus timeout monitor Spurious interrupt monitor N Programmable interrupt controller Low interrupt latency 3 external interrupt inputs Programmable interrupt priority and autovector generator N IEEE 1149.1 test (JTAG) support N 8-bit general-purpose I/O interface System Debug Support N Real-time trace N Background debug interface Fully Static 5.0-Volt Operation 160 Pin QFP Package MOTOROLA MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com 1-3 Freescale Semiconductor, Inc. Introduction 1.3 FUNCTIONAL BLOCKS Figure 1-1 is a block diagram of the MCF5206 processor. The paragraphs that follow provide an overview of the integrated processor. CLOCK 3 INPUT Freescale Semiconductor, Inc... 4 JTAG DRAM CONTROLLER CLOCK JTAG INTERFACE 512 BYTE ICACHE SYSTEM B US CONTR OLLER 2 CHIP SELECTS DRAM CONTROL CHIP SELECTS INTERRUPT CONTROLLER INTERRUPT EXTERNAL BUS INTERFACE EXTERNAL SUPPORT BUS 512 BYTE SRAM 6 PARALLEL PORT PARALLEL INTERFACE 7 DUART SERIAL INTERFACE 8 TIMERS 9 BDM COLDFIRE INTERFACE CORE M-BUS MODULE TIMER SUPPORT M-BUS INTERFACE 1 Figure 1-1. MCF5206 Block Diagram 11 1.3.1 ColdFire Processor Core 12 13 14 15 The ColdFire processor core consists of two independent, decoupled pipeline structures to maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP, thereby minimizing time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline featuring a traditional RISC datapath with a dual-read-ported register file feeding an arithmetic/logic unit. 1.3.1.1 PROCESSOR STATES. The processor is always in one of four states: normal processing, exception processing, stopped, or halted. It is in the normal processing state 16 1-4 MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Introduction when executing instructions, fetching instructions and operands, and storing instruction results. Freescale Semiconductor, Inc... Exception processing is the transition from program processing to system, interrupt, and exception handling; it includes fetching the exception vector, stacking operations, and refilling the instruction fetch pipe after an exception. The processor enters exception processing when an exceptional internal condition arises, such as tracing an instruction, an instruction resulting in a trap, or executing specific instructions; (External conditions, such as interrupts and access errors, also cause exceptions) and ends when the first instruction of the exception handler enters the operand execution pipeline. Stopped mode is a reduced power operation mode that causes the processor to remain quiescent until either a reset or nonmasked interrupt occurs. The STOP instruction is used to enter this operation mode. The processor halts when it receives an access error or generates an address error while in the exception processing state. For example, if during exception processing of one access error another access error occurs, the MCF5206 processor cannot complete the transition to normal processing nor can it save the internal machine state. The processor assumes that the system is not operational and halts. Only an external reset can restart a halted processor. When the processor executes a STOP instruction, it is in a special type of normal processing state, e.g., one without bus cycles. The processor stops but it does not halt. The processor can also halt in a restart mode because of Background-Debug mode events. 1.3.1.2 PROGRAMMING MODEL. The ColdFire programming model is separated into two privilege modes: supervisor and user. The S-bit in the status register (SR) indicates the current privilege mode. The processor identifies a logical address by accessing either the supervisor or user address space, which differentiates between supervisor and user modes. User programs can access only registers specific to the user mode. System software executing in the supervisor mode can access all registers using the control registers to perform supervisory functions. User programs are thus restricted from accessing privileged information. The operating system performs management and service tasks for user programs by coordinating their activities. This difference allows the supervisor mode to protect system resources from uncontrolled accesses. Most instructions execute in either mode but some instructions that have important system effects are privileged and can execute only in the supervisor mode. For instance, user programs cannot execute the STOP instructions. To prevent a program executing in user mode from entering the supervisor mode, instructions that can alter the S-bit in the SR are privileged. The TRAP instructions provide controlled access to operating system services for user programs. When in normal processing, the processor employs the user mode and the user programming model . During exception processing, the processor changes from user to supervisor mode. The current SR value on the stack is saved and then the S-bit is set, forcing the processor into the supervisor mode. To return to the user mode, a system routine must execute a MOVE to SR, or an RTE, which operate in the supervisor mode, modifying MOTOROLA MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com 1-5 Freescale Semiconductor, Inc. Introduction the S-bit of the SR. After these instructions execute, the instruction fetch pipeline flushes and is refilled from the appropriate address space. 2 3 Freescale Semiconductor, Inc... 4 6 The registers depicted in the programming model (see Figure 1-2) provide operand storage and control for the ColdFire processor core. The registers are also partitioned into user and supervisor privilege modes. The user programming model consists of 16 general-purpose, 32-bit registers and two control registers. The supervisor model consists of five more registers that can be accessed only by code running in supervisor mode. Only system programmers can use the supervisor programming model to implement operating system functions and I/O control. This supervisor/user distinction allows for the coding of application software that run without modification on any ColdFire Family processor. The supervisor programming model contains the control features that system designers would not want user code to erroneously access as this might effect normal system operation. Furthermore, the supervisor programming model may need to change slightly from ColdFire generation to generation to add features or improve performance as the architecture evolves. 7 8 9 1 11 12 13 14 15 16 1-6 MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Introduction 31 0 D0 D1 D2 DATA REGISTERS D3 D4 Freescale Semiconductor, Inc... D5 D6 D7 31 0 A0 A1 A2 ADDRESS REGISTERS A3 A4 A5 A6 A7 STACK POINTER PC PROGRAM COUNTER CCR CONDITION CODE REGISTER USER PROGRAMMING MODEL 15 31 19 (CCR) MUST BE ZEROS SR STATUS REGISTER VBR VECTOR BASE REGISTER CACR CACHE CONTROL REGISTER ACR0 ACCESS CONTROL REGISTER 0 ACR1 ACCESS CONTROL REGISTER 1 SUPERVISOR PROGRAMMING MODEL Figure 1-2. Programming Model The user programming model includes eight data registers, seven address registers, and a stack pointer register. The address registers and stack pointer can be used as base address registers or software stack pointers, and any of the 16 registers can be used as index registers. Two control registers are available in the user mode: the program counter (PC), which contains the address of the instruction that the MCF5206 device is executing, and the lower byte of the SR, which is accessible as the Condition Code Register (CCR). The CCR contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. MOTOROLA MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com 1-7 Freescale Semiconductor, Inc. Introduction 2 3 Freescale Semiconductor, Inc... 4 The supervisor programming model includes the upper byte of the SR, which contains operation control information. The Vector Base Register (VBR) contains the upper 12 bits of the base address of the exception vector table, which is used in exception processing. The lower 20 bits of the VBR are forced to zero, allowing the vector table to reside on any 1 Mbyte memory boundary. The Cache Control Register (CACR) controls enabling of the on-chip cache. Two access control registers (ACR1, ACR0) allow portions of the address space to be mapped as noncacheable. See subsections 4.3 and 4.4 for details on these registers. 1.3.1.3 DATA FORMAT SUMMARY. The processor performs all arithmetic using 2Os complement, but operands can be signed or unsigned. Registers, memory, or instructions themselves can contain operands. The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. Table1-1 summarizes the MCF5206 data formats. 6 Table 1-1. ColdFire MCF5206 Data Formats OPERAND DATA FORMAT Bit Byte Word Longword 7 8 9 1 11 12 13 SIZE 1-Bit 8-Bits 16-Bits 32-Bits 1.3.1.4 ADDRESSING CAPABILITIES SUMMARY. The MCF5206 processor supports seven addressing modes. The register indirect addressing modes support postincrement, predecrement, offset, and indexing, which are particularly useful for handling data structures common to sophisticated embedded applications and high-level languages. The program counter indirect mode also has indexing and offset capabilities. This addressing mode is typically required to support position-independent software. Besides these addressing modes, the MCF5206 processor provides index scaling features. An instructionOs addressing mode can specify the value of an operand or a register containing the operand. It can also specify how to derive the effective address of an operand in memory. Each addressing mode has an assembler syntax. Some instructions imply the addressing mode for an operand. These instructions include the appropriate fields for operands that use only one addressing mode. Table 1-2 summarizes the effective addressing modes of ColdFire processors. Table 1-3 summarizes the MOVE specific effective addressing modes. 1.3.1.5 NOTATIONAL CONVENTIONS. Table 1-4 lists the notation conventions used throughout this manual, unless otherwise specified. 14 15 16 1-8 MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Introduction Freescale Semiconductor, Inc... Table 1-2. ColdFire Effective Addressing Modes ADDRESSING MODES Register Direct Data Address Register Indirect Address Address with Postincrement Address with Predecrement Address with Displacement Address Register Indirect with Index 8-Bit Displacement SYNTAX (d8,An,Xi) Program Counter Indirect with Displacement (d16,PC) Program Counter Indirect with Index 8-Bit Displacement (d8,PC,Xi) Absolute Data Addressing Short Long Immediate (xxx).W (xxx).L # Dn An (An) (An)+ (An) (d16,An) Table 1-3. MOVE Specific Effective Addressing Modes SOURCE Dn An (An) (An)+ -(An) (d16 ,An) (d16 ,PC) (d8,An,Xi) (d8,PC,Xi) (xxx).W (xxx).L # MOTOROLA DESTINATION All All All All All Dn An (An) (An)+ -(An) (d16 ,An) Dn An (An) (An)+ -(An) Dn An (An) (An)+ -(An) Dn An (An) (An)+ -(An) MCF5206 USEROS MANUAL Rev 1.0 For More Information On This Product, Go to: www.freescale.com 1-9 Freescale Semiconductor, Inc. Introduction Table 1-4. Notational Conventions OPCODE WILDCARDS 2 cc Logical Condition (example: NE for not equal) REGISTER OPERANDS An Ay,Ax Dn Dy,Dx Rn Ry,Rx Rw Rc 3 Freescale Semiconductor, Inc... 4 Any Address Register n (example: A3 is address register 3) Source and destination address registers, respectively Any Data Register n (example: D5 is data register 5) Source and destination data registers, respectively Any Address or Data Register Any source and destination registers, respectively Any second destination register Any Control Register (example VBR is the vector base register) REGISTER/PORT NAMES DDATA CCR PC PST SR 6 7 MISCELLANEOUS OPERANDS # e y,x