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FEATURES
10 years minimu m data retent ion in the
absence o f exter na l po wer
Dat a is aut omatical ly pro tected during power
loss
D irectly replac es 2k x 8 volatile static RAM
or EE P R O M
Unlim ited writ e cycles
Low-power CMOS
JEDEC standard 28-pin DIP package
Read and wr it e acces s times of 150 ns
Full ±10% o perating r ange
Optional industr ial temperature range of
-40°C to +85°C, designated IND
PIN ASSIGNMENT
24-Pin ENC APSULATE D PACKAGE
720-mil EXTENDED
PIN DESCRIPTION
A0-A12 - Address Inputs
DQ0-DQ7 - Data I n/Dat a Out
CE
- Chip Enable
WE
- Wr ite E nable
OE
- Output Enable
VCC - Po w er (+5V)
GND - Ground
DESCRIPTION
The DS1225Y 64k Nonvolat ile SRAM is a 65,53 6-bit, fully static, nonvolat ile RAM organized as 8192
wo rds by 8 bits. Eac h NV SR AM ha s a self-contained lit hium energ y source and control c ircuit ry w hic h
constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. The NV SRAM can be used in place of existing 8k x 8 SRAMs directly conforming to
t he popular bytewide 28-pin D IP sta ndard. T he DS1225Y a lso matches the pinout o f t he 2764 EPROM or
the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the
number of write cycles that can be executed and no additional support circuitry is required for micro-
processor interfac ing.
DS1225Y
64k Nonvolatile SRAM
19-5603; Rev 10/10
www.maxim-ic.com
15
13
27
VCC
WE
NC
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
1
2
3
4
5
6
7
8
9
10
11
12
14
28
26
25
24
23
22
21
20
19
18
17
16
NC
NOT RECOMMENDED FOR NEW DESIGNS
NOT RECOMME NDED FOR NEW DESIGNS DS1225Y
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READ MODE
The DS1225Y executes a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
E na b le) a nd
OE
(Out put Enable) are active (low) . The unique address speci fied by the 13 address input s
(A0-A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be available to the
e ight dat a o ut put driver s w it hin t ACC (Access Time) after the last address input signal is stable, providing
that
CE
and
OE
access t imes are also sat isfied. I f
CE
and
OE
access t imes are not sat isfied, then dat a
access must be measured from the later-occurring signal and the limit ing parameter is either tCO for
CE
or tOE for
OE
rather than address access.
WRITE MODE
The DS1225Y executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
inputs are stable. The later-occurring falling edge of
CE
or
WE
will determine the start of the write
cycle. T he wr ite c ycle is t erminat ed by t he ear lier r is ing ed ge o f
CE
or
WE
. All address inputs must be
kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR ) before another cyc le can be init iated. The
OE
control signa l shou ld be kept inactive (high) during
wr ite c ycles t o avoid bus cont ent ion. Ho wever, if the out put drivers are e nab led (
CE
and
OE
act ive) t he n
WE
will disable the outp uts in tODW fr om its falling edge.
DATA RETENTION MODE
The DS1225Y provides full fu nct ional capabilit y fo r VCC greater than 4.5 vo lts and write pro t ects at 4.25
nominal. Data is maintained in the absence of VCC without any additional support circuitry. The
DS1225Y constant ly mon itor s V CC. Shou ld th e supp ly vo ltage deca y, t he NV SR AM aut o mat ically wr ite
protects itself, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls
below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to
ret ain dat a. Dur ing po wer-u p, w he n V CC r ises a bove ap pro ximat ely 3. 0 vo lts, t he po wer sw it ching c ircu it
connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can
resu me aft er VCC exceed s 4. 5 volts.
NOT RECOMME NDED FOR NEW DESIGNS DS1225Y
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ABSOLUTE MAXIMUM RA TINGS
Voltage on Any Pin Relative to Ground -0.3V to +6.0V
Operating Temperat ur e Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Stor ag e T emperat ur e -40°C to +85°C
Lead Temperature ( soldering, 10s) +260°C
Note: EDI P is w ave or hand soldered only.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA : See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Po wer Supply Voltage
VCC
4.5
5.0
5.5
V
Input Logic 1
VIH
2.2
VCC
V
Input Logic 0
VIL
0.0
+0.8
V
DC ELECTRICAL CHARACTERISTICS (TA : See Note 10; VCC = 5V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Leakage Cu r r ent
IIL
-1.0
+1.0
µA
I/O Leakage Cu r r ent
CE
≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.4V
IOH
-1.0
mA
Output Current @ 0.4V
IOL
2.0
mA
St andby Current
CE
= 2.2V 1CCS1 5 10 mA
St andby Current
CE
=VCC -0.5V
1CCS2 3 5 mA
Operating Curren t t
CYC
=200ns
(Commercial)
1CCO1 75 mA
Operating Curren t t
CYC
= 200ns
(Industrial)
ICCO1 85 mA
Write Protection Voltage
V
TP
4.25
V
10
NOT RECOMME NDED FOR NEW DESIGNS DS1225Y
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AC ELECTRICAL CHARACTERISTICS (TA: See Note 10; VCC =5.0V ± 10%)
PARAMETER SYMBOL
DS1225Y-150
UNITS NOTES
MIN
MAX
Read Cyc le Time
tRC
150
ns
Acce ss Time
tACC
150
ns
OE
to Output Val id
t
OE
70
ns
CE
t o Output Va lid
t
CO
150
ns
OE
or
CE
to
Output Active
t
COE
5
ns
5
Outpu t High Z from
Deselection
t
OD
35
ns
5
Output Hold from
AddressChange
t
OH
5
ns
Writ e Cycle Time
tWC
150
ns
Writ e P ulse Width
tWP
100
ns
3
A ddress Setup Tim e
t
AW
0
ns
Writ e Recovery Time
t
WR1
t
WR2
0
10
ns
ns
12
13
Outpu t High Z from
WE
t
ODW
35
ns
5
Output Active from
WE
t
OEW
5
ns
5
Da ta S etup T ime
tDS
60
ns
4
Da ta Hold Time
t
DH1
tDH2
0
10
ns
ns
12
13
CAPACITANCE (TA = +25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
10
pF
I npu t/O utput Ca pacita nc e
CI/O
10
pF
NOT RECOMME NDED FOR NEW DESIGNS DS1225Y
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTE 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTE 2, 3, 4, 6, 7, 8 AND 13
NOT RECOMME NDED FOR NEW DESIGNS DS1225Y
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POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
CE
at V
IH
before Power-Down
t
PD
0
µs
11
V
CC
Slew from V
TP
to 0V
t
F
100
µ
s
V
CC
Sle w from 0V to V
TP
t
R
0
µ
s
CE
at VIH after Power-Up
t
REC
2
ms
(TA = +25°C)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Expect ed Data Retention T ime
tDR
10
years
9
WARNING:
Under no c ircumst anc e ar e negative under shoots, of any amp l it ud e, allowed when device is in batter y
backup mo de.
NOTES:
1.
WE
is h igh fo r a r ead cycle.
2.
OE
= VIH or VIL. If
OE
= VIH during a writ e c ycle, the output buffers remain in a high impedance
state.
3. tWP is specif ied as t he logical AND o f
CE
and
WE
. tWP is measur ed from the latter of
CE
or
WE
go ing lo w t o t he ear lier o f
CE
or
WE
go ing h ig h.
4. tDS is measured fro m the ear lier of
CE
or
WE
going high.
5. T hese para met er s ar e sampled with a 5 pF lo ad an d ar e not 100 % tested .
6. If the
CE
lo w transition oc curs simultane ously with or la ter t ha n the
WE
low t ransition i n W rite
Cycle 1, t he outp ut buffers remain in a high-impedance state during this per iod.
7. If t he
CE
hig h t rans it io n o cc urs pr io r to or s imult a ne ou sly w it h t he
WE
high transit ion, t he output
buffe rs r emain in a high-impeda nce state dur ing this period.
NOT RECOMME NDED FOR NEW DESIGNS DS1225Y
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8. If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low tra nsition,
the outp ut buf fer s remai n in a h igh-i mpedance state during this period.
9. Each DS1225Y is marked with a 4-digit date code AABB. AA designates the year of manufacture.
BB designates the week of manufacture. The expected tDR is defined as starting at the date of
manufacture.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industria l product s (IND), this range is -40°C to
+85°C.
11. In a p ower down c ondition the voltage on a ny pin may no t exc eed the voltage on V CC.
12. tWR1 , tDH1 are measured from
WE
going high.
13. tWR2 , tDH2 are measured from
CE
going high.
14. DS1225Y modules are recognized by Underwriter s Laboratories (UL) under file E99151 (R).
DC TEST CONDITIONS
Outputs open .
All volt ages ar e r eferenced to ground.
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0-3.0V
Timing Measur ement Reference Levels
Input:1. 5V Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
PART TEMP RANGE
SUPPLY
TOLERANCE
SPEED GRADE
(ns)
PIN-PACKAGE
DS1225Y-150+
0°C to +70°C
5V ± 10%
150
28 720 EDIP
DS1225Y-
150IND+
-40°C to +85°C 5V ± 10% 150 28 720 EDIP
+Denotes a lead(Pb)-free/RoHS-compliant package.
PACKAGE INFORMATION
For the latest package outline infor mation an d lan d pat terns, g o to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, but the dr awin g pertains to the pa ckage r e gardl ess of RoH S s tatus .
PACKAGE TYPE PACK AG E CODE OUTLINE NO. LAND PATTERN NO.
28 EDIP MDT28+2 21-0245 —
NOT RECOMME NDED FOR NEW DESIGNS DS1225Y
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REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
121907
Added the Package Information table; removed the DIP module
package drawing and dimension table
7
10/10
Added Not Recommended for New Designs status; updated th e
sto r age information, so ldering temperature, and l ead tem perature
information in the Absolute Maximum R atings section; removed the
-170 and -200 MIN/MAX info rmation from the AC Electrical
Characteristics table; added the updated th e Ordering Information
table
1, 3, 4, 7