LMC7101, LMC7101Q
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LMC7101/LMC7101Q Tiny Low Power Operational Amplifier with Rail-to-Rail Input and
Output
Check for Samples: LMC7101,LMC7101Q
1FEATURES • Rail-to-Rail Input and Output
• Temperature Range –40°C to 125°C
2• Tiny 5-Pin SOT-23 Package Saves (LMC7101Q)
Space—Typical Circuit Layouts Take Half the
Space of 8-Pin SOIC Designs APPLICATIONS
• Guaranteed Specs at 2.7V, 3V, 5V, 15V
Supplies • Mobile Communications
• Typical Supply Current 0.5 mA at 5V • Notebooks and PDAs
• Typical Total Harmonic Distortion of 0.01% at • Battery Powered Products
5V • Sensor Interface
• 1.0 MHz Gain-Bandwidth • Automotive Applications (LMC7101Q)
• Similar to Popular LMC6482/LMC6484
DESCRIPTION
The LMC7101 is a high performance CMOS operational amplifier available in the space saving 5-Pin SOT-23
Tiny package. This makes the LMC7101 ideal for space and weight critical designs. The performance is similar
to a single amplifier of the LMC6482/LMC6484 type, with rail-to-rail input and output, high open loop gain, low
distortion, and low supply currents.
The main benefits of the Tiny package are most apparent in small portable electronic devices, such as mobile
phones, pagers, notebook computers, personal digital assistants, and PCMCIA cards. The tiny amplifiers can be
placed on a board where they are needed, simplifying board layout.
Connection Diagram
Figure 1. 5-Pin SOT-23
Top View
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMC7101, LMC7101Q
SNOS719F –SEPTEMBER 1999–REVISED MARCH 2013
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Absolute Maximum Ratings(1)(2)
ESD Tolerance (3)
Human Body Model 1000V
Machine Model 200V
Charged Device Model 1000V
Difference Input Voltage ±Supply Voltage
Voltage at Input/Output Pin (V+) + 0.3V, (V−)−0.3V
Supply Voltage (V+−V−) 16V
Current at Input Pin ±5 mA
Current at Output Pin (4) ±35 mA
Current at Power Supply Pin 35 mA
Lead Temp. (Soldering, 10 sec.) 260°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (5) 150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Human Body Model is 1.5 kΩin series with 100 pF.
(4) Applies to both single-supply and split-supply operation. Continuous short operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature at 150°C.
(5) The maximum power dissipation is a function of TJ(MAX),θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) −TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Recommended Operating Conditions(1)
Supply Voltage 2.7V ≤V+≤15.5V
Temperature Range
LMC7101AI, LMC7101BI −40°C to 85°C
LMC7101Q −40°C to 125°C
Thermal Resistance (θJA)
5-Pin SOT-23 325°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
2.7V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 2.7V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩ.Boldface
limits apply at the temperature extremes. LMC7101AI LMC7101BI LMC7101Q
Symbol Parameter Conditions Typ(1) Limit Limit Limit Units
(2) (2) (2) (3)
mV
VOS Input Offset Voltage Average Drift V+= 2.7V 0.11 6 9 9 max
TCVOS Input Offset Voltage 1 μV/°C
IBInput Bias Current 1.0 64 64 1000 pA max
IOS Input Offset Current 0.5 32 32 2000 pA max
RIN Input Resistance >1 Tera Ω
0V ≤VCM ≤2.7V
CMRR Common-Mode Rejection Ratio 70 55 50 50 dB min
V+= 2.7V 0.0 0.0 0.0 0.0 V min
Input Common Mode Voltage
VCM For CMRR ≥50 dB
Range 3.0 2.7 2.7 2.7 V max
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) When operated at temperature between −40°C and 85°C, the LMC7101Q will meet LMC7101BI specifications.
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2.7V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 2.7V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩ.Boldface
limits apply at the temperature extremes. LMC7101AI LMC7101BI LMC7101Q
Symbol Parameter Conditions Typ(1) Limit Limit Limit Units
(2) (2) (2) (3)
V+= 1.35V to 1.65V
PSRR Power Supply Rejection Ratio V−=−1.35V to −1.65V 60 50 45 45 dB min
VCM = 0
CIN Common-Mode Input Capacitance 3 pF
2.45 2.15 2.15 2.15 V min
RL= 2 kΩ0.25 0.5 0.5 0.5 V max
VOOutput Swing 2.68 2.64 2.64 2.64 V min
RL= 10 kΩ0.025 0.06 0.06 0.06 V max
0.5 0.81 0.81 0.81 mA
ISSupply Current 0.95 0.95 0.95 max
SR Slew Rate (4) 0.7 V/μs
GBW Gain-Bandwidth Product 0.6 MHz
(4) V+= 15V. Connected as a voltage follower with a 10V step input. Number specified is the slower of the positive and negative slew rates.
RL= 100 kΩconnected to 7.5V. Amp excited with 1 kHz to produce VO= 10 VPP.
3V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 3V, V−= 0V, VCM = 1.5V, VO= V+/2 and RL= 1 MΩ.
Boldface limits apply at the temperature extremes. LMC7101AI LMC7101BI LMC7101Q
Typ
Symbol Parameter Conditions Limit Limit Limit Units
(1) (2) (2) (2) (3)
4 7 mV
VOS Input Offset Voltage 0.11 7
6 9 max
TCVOS Input Offset Voltage Average Drift 1 μV/°C
IBInput Current 1.0 64 64 1000 pA max
IOS Input Offset Current 0.5 32 32 2000 pA max
RIN Input Resistance >1 Tera Ω
0V ≤VCM ≤3V
CMRR Common-Mode Rejection Ratio 74 64 60 60 db min
V+= 3V 0.0 0.0 0.0 0.0 V min
Input Common-Mode Voltage
VCM For CMRR ≥50 dB
Range 3.3 3.0 3.0 3.0 V max
V+= 1.5V to 7.5V
PSRR Power Supply Rejection Ratio V−=−1.5V to −7.5V 80 68 60 60 dBmin
VO= VCM = 0
CIN Common-Mode Input Capacitance 3 pF
2.8 2.6 2.6 2.6 V min
RL= 2 kΩ0.2 0.4 0.4 0.4 V max
VOOutput Swing 2.7 2.5 2.5 2.5 V min
RL= 600Ω0.37 0.6 0.6 0.6 V max
0.81 0.81 0.81 mA
ISSupply Current 0.5 0.95 0.95 0.95 max
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) When operated at temperature between −40°C and 85°C, the LMC7101Q will meet LMC7101BI specifications.
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5V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 5V, V−= 0V, VCM = 1.5V, VO= V+/2 and RL= 1 MΩ.
Boldface limits apply at the temperature extremes. LMC7101AI LMC7101BI LMC7101Q
Typ
Symbol Parameter Conditions Limit Limit Limit Units
(1) (2) (2) (2) (3)
0.11 3 7 7 mV
VOS Input Offset Voltage V+= 5V 599max
TCVOS Input Offset Voltage Average Drift 1.0 μV/°C
IBInput Current 1 64 64 1000 pA max
IOS Input Offset Current 0.5 32 32 2000 pA max
RIN Input Resistance >1 Tera Ω
0V ≤VCM ≤5V 82 65 60 60 db min
CMRR Common-Mode Rejection Ratio LMC7101Q @ 125°C 60 55 55
0.2V ≤VCM ≤4.8V
Positive Power Supply Rejection V+= 5V to 15V 82 70 65 65 dB min
+PSRR Ratio V−= 0V, VO= 1.5V 65 62 62
Negative Power Supply Rejection V−=−5V to −15V 82 70 65 65 dB min
−PSRR Ratio V+= 0V, VO=−1.5V 65 62 62
−0.3 −0.20 −0.20 −0.2 V min
For CMRR ≥50 dB 0.00 0.00 0.2
Input Common-Mode Voltage
VCM Range 5.3 5.20 5.20 5.2 V max
5.00 5.00 4.8
CIN Common-Mode Input Capacitance 3 pF
4.9 4.7 4.7 4.7 V min
RL= 2 kΩ4.6 4.6 4.54
0.1 0.18 0.18 0.18 V max
0.24 0.24 0.28
VOOutput Swing 4.7 4.5 4.5 4.5 V min
RL= 600Ω4.24 4.24 4.28
0.3 0.5 0.5 0.5 V max
0.65 0.65 0.8
16 16 16 mA min
VO= 0V 24 Sourcing 24 11 11 9
ISC Output Short Circuit Current 11 11 11 mA min
VO= 5V Sinking 19 7.5 7.5 5.8
0.85 0.85 0.85 mA
ISSupply Current 0.5 1.0 1.0 1.0 max
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) When operated at temperature between −40°C and 85°C, the LMC7101Q will meet LMC7101BI specifications.
5V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 5V, V−= 0V, VCM = 1.5V, VO= V+/2 and RL= 1 MΩ.
Boldface limits apply at the temperature extremes. LMC7101AI LMC7101BI
Typ
Symbol Parameter Conditions Limit Limit Units
(1) (2) (2)
f = 10 kHz, AV=−2
THD Total Harmonic Distortion 0.01 %
RL= 10 kΩ, VO= 4.0 VPP
SR Slew Rate 1.0 V/μs
GBW Gain Bandwidth Product 1.0 MHz
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
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15V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 15V, V−= 0V, VCM = 1.5V, VO= V+/2 and RL= 1 MΩ.
Boldface limits apply at the temperature extremes. LMC7101AI LMC7101BI LMC7101Q
Typ
Symbol Parameter Conditions Limit Limit Limit Units
(1) (2) (2) (2) (3)
mV
VOS Input Offset Voltage 0.11 max
TCVOS Input Offset Voltage Average Drift 1.0 μV/°C
IBInput Current 1.0 64 64 1000 pA max
IOS Input Offset Current 0.5 32 32 2000 pA max
RIN Input Resistance >1 Tera Ω
0V ≤VCM ≤15V 82 70 65 65 dB min
CMRR Common-Mode Rejection Ratio LMC7101Q @°125C 65 60 60
0.2V ≤VCM ≤14.8V
Positive Power Supply Rejection V+= 5V to 15V 82 70 65 65 dB min
+PSRR Ratio V−= 0V, VO= 1.5V 65 62 62
Negative Power Supply Rejection V−=−5V to −15V 82 70 65 65 dB min
−PSRR Ratio V+= 0V, VO=−1.5V 65 62 62
V+= 5V −0.3 −0.20 −0.20 −0.2 V min
For CMRR ≥50 dB 0.00 0.00 0.2
Input Common-Mode Voltage
VCM Range 15.3 15.20 15.20 15.2 V max
15.00 15.00 14.8
340 80 80 80
Sourcing 40 40 30
RL= 2 kΩV/mV
24 15 15 15
Large Signal Voltage Gain Sinking
AV10 10 4
(4)
Sourcing 300 34 34 34
RL= 600ΩV/mV
Sinking 15 6 6 6
CIN Input Capacitance 3 pF
V+= 15V 14.7 14.4 14.4 14.4 V min
RL= 2 kΩ14.2 14.2 14.2
0.16 0.32 0.32 0.32 V max
0.45 0.45 0.45
VOOutput Swing V+= 15V 14.1 13.4 13.4 13.4 V min
RL= 600Ω13.0 13.0 12.85
0.5 1.0 1.0 1.0 V max
1.3 1.3 1.5
50 30 30 30
VO= 0V Sourcing 20 20 20
Output Short Circuit Current
ISC mA min
(5) 50 30 30 30
VO= 12V Sinking 20 20 20
0.8 1.50 1.50 1.50 mA
ISSupply Current 1.71 1.71 1.75 max
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) When operated at temperature between −40°C and 85°C, the LMC7101Q will meet LMC7101BI specifications.
(4) V+= 15V, VCM = 1.5V and RLconnect to 7.5V. For sourcing tests, 7.5V ≤VO≤12.5V. For sinking tests, 2.5V ≤VO≤7.5V.
(5) Do not short circuit output to V+when V+is greater than 12V or reliability will be adversely affected.
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15V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 15V, V−= 0V, VCM = 1.5V, VO= V+/2 and RL= 1 MΩ.
Boldface limits apply at the temperature extremes. LMC7101AI LMC7101BI LMC7101Q
Typ
Symbol Parameter Conditions Limit Limit Limit Units
(1) (2) (2) (2) (3)
Slew Rate 0.5 0.5 0.5 V/μs
SR V+= 15V 1.1
(4) 0.4 0.4 0.4 min
GBW Gain-Bandwidth Product V+= 15V 1.1 MHz
φmPhase Margin 45 deg
GmGain Margin 10 dB
enInput-Referred Voltage Noise f = 1 kHz, VCM = 1V 37
InInput-Referred Current Noise f = 1 kHz 1.5
f = 10 kHz, AV=−2
THD Total Harmonic Distortion 0.01 %
RL= 10 kΩ, VO= 8.5 VPP
(1) Typical Values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) When operated at temperature between −40°C and 85°C, the LMC7101Q will meet LMC7101BI specifications.
(4) V+= 15V. Connected as a voltage follower with a 10V step input. Number specified is the slower of the positive and negative slew rates.
RL= 100 kΩconnected to 7.5V. Amp excited with 1 kHz to produce VO= 10 VPP.
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2.7V Typical Performance Characteristics
V+= 2.7V, V−= 0V, TA= 25°C, unless otherwise specified.
Open Loop Frequency Response Input Voltage vs. Output Voltage
Figure 2. Figure 3.
Gain and Phase vs. Capacitance Load Gain and Phase vs. Capacitance Load
Figure 4. Figure 5.
dVOS vs. Supply Voltage dVOS vs. Common Mode Voltage
Figure 6. Figure 7.
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2.7V Typical Performance Characteristics (continued)
V+= 2.7V, V−= 0V, TA= 25°C, unless otherwise specified.
Sinking Current vs. Output Voltage Sourcing Current vs. Output Voltage
Figure 8. Figure 9.
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3V Typical Performance Characteristics
V+= 3V, V−= 0V, TA= 25°C, unless otherwise specified.
Open Loop Frequency Response Input Voltage vs. Output Voltage
Figure 10. Figure 11.
Input Voltage Noise vs. Input Voltage Sourcing Current vs. Output Voltage
Figure 12. Figure 13.
Sinking Current vs. Output Voltage CMRR vs. Input Voltage
Figure 14. Figure 15.
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5V Typical Performance Characteristics
V+= 5V, V−= 0V, TA= 25°C, unless otherwise specified.
Open Loop Frequency Response Input Voltage vs. Output Voltage
Figure 16. Figure 17.
Input Voltage Noise vs. Input Voltage Sourcing Current vs, Output Voltage
Figure 18. Figure 19.
Sinking Current vs. Output Voltage CMRR vs. Input Voltage
Figure 20. Figure 21.
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15V Typical Performance Characteristics
V+= +15V, V−= 0V, TA= 25°C, unless otherwise specified.
Open Loop Frequency Response Input Voltage vs. Output Voltage
Figure 22. Figure 23.
Input Voltage Noise vs. Input Voltage Sourcing Current vs. Output Voltage
Figure 24. Figure 25.
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15V Typical Performance Characteristics (continued)
V+= +15V, V−= 0V, TA= 25°C, unless otherwise specified.
Sinking Current vs. Output Voltage CMRR vs. Input Voltage
Figure 26. Figure 27.
Supply Current vs. Supply Voltage Input Current vs. Temperature
Figure 28. Figure 29.
Output Voltage Swing vs. Supply Voltage Input Voltage Noise vs. Frequency
Figure 30. Figure 31.
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15V Typical Performance Characteristics (continued)
V+= +15V, V−= 0V, TA= 25°C, unless otherwise specified.
Positive PSRR vs. Frequency Negative PSRR vs. Frequency
Figure 32. Figure 33.
CMRR vs. Frequency Open Loop Frequency Response @ −40°C
Figure 34. Figure 35.
Open Loop Frequency Response @ 25°C Open Loop Frequency Response @ 85°C
Figure 36. Figure 37.
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15V Typical Performance Characteristics (continued)
V+= +15V, V−= 0V, TA= 25°C, unless otherwise specified.
Maximum Output Swing vs. Frequency Gain and Phase vs. Capacitive Load
Figure 38. Figure 39.
Gain and Phase vs. Capacitive Load Output Impedance vs. Frequency
Figure 40. Figure 41.
Slew Rate vs. Temperature Slew Rate vs. Supply Voltage
Figure 42. Figure 43.
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15V Typical Performance Characteristics (continued)
V+= +15V, V−= 0V, TA= 25°C, unless otherwise specified.
Inverting Small Signal Pulse Response Inverting Small Signal Pulse Response
Figure 44. Figure 45.
Inverting Small Signal Pulse Response Inverting Large Signal Pulse Response
Figure 46. Figure 47.
Inverting Large Signal Pulse Response Inverting Large Signal Pulse Response
Figure 48. Figure 49.
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15V Typical Performance Characteristics (continued)
V+= +15V, V−= 0V, TA= 25°C, unless otherwise specified.
Non-Inverting Small Signal Pulse Response Non-Inverting Small Signal Pulse Response
Figure 50. Figure 51.
Non-Inverting Small Signal Pulse Response Non-Inverting Large Signal Pulse Response
Figure 52. Figure 53.
Non-Inverting Large Signal Pulse Response Non-Inverting Large Signal Pulse Response
Figure 54. Figure 55.
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15V Typical Performance Characteristics (continued)
V+= +15V, V−= 0V, TA= 25°C, unless otherwise specified.
Stability vs. Capacitive Load Stability vs. Capacitive Load
Figure 56. Figure 57.
Stability vs. Capacitive Load Stability vs. Capacitive Load
Figure 58. Figure 59.
Stability vs. Capacitive Load Stability vs. Capacitive Load
Figure 60. Figure 61.
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APPLICATION INFORMATION
BENEFITS OF THE LMC7101 TINY AMP
Size
The small footprint of the SOT-23-5 packaged Tiny amp, (0.120 x 0.118 inches, 3.05 x 3.00 mm) saves space on
printed circuit boards, and enable the design of smaller electronic products. Because they are easier to carry,
many customers prefer smaller and lighter products.
Height
The height (0.056 inches, 1.43 mm) of the Tiny amp makes it possible to use it in PCMCIA type III cards.
Signal Integrity
Signals can pick up noise between the signal source and the amplifier. By using a physically smaller amplifier
package, the Tiny amp can be placed closer to the signal source, reducing noise pickup and increasing signal
integrity. The Tiny amp can also be placed next to the signal destination, such as a buffer for the reference of an
analog to digital converter.
Simplified Board Layout
The Tiny amp can simplify board layout in several ways. First, by placing an amp where amps are needed,
instead of routing signals to a dual or quad device, long pc traces may be avoided.
By using multiple Tiny amps instead of duals or quads, complex signal routing and possibly crosstalk can be
reduced.
Low THD
The high open loop gain of the LMC7101 amp allows it to achieve very low audio distortion—typically 0.01% at
10 kHz with a 10 kΩload at 5V supplies. This makes the Tiny an excellent for audio, modems, and low
frequency signal processing.
Low Supply Current
The typical 0.5 mA supply current of the LMC7101 extends battery life in portable applications, and may allow
the reduction of the size of batteries in some applications.
Wide Voltage Range
The LMC7101 is characterized at 15V, 5V and 3V. Performance data is provided at these popular voltages. This
wide voltage range makes the LMC7101 a good choice for devices where the voltage may vary over the life of
the batteries.
INPUT COMMON MODE
Voltage Range
The LMC7101 does not exhibit phase inversion when an input voltage exceeds the negative supply voltage.
Figure 62 shows an input voltage exceeding both supplies with no resulting phase inversion of the output.
The absolute maximum input voltage is 300 mV beyond either rail at room temperature. Voltages greatly
exceeding this maximum rating, as in Figure 63, can cause excessive current to flow in or out of the input pins,
adversely affecting reliability.
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An input voltage signal exceeds the LMC7101 power supply voltages with no output phase inversion.
Figure 62. Input Voltage
A ±7.5V input signal greatly exceeds the 3V supply in Figure 64 causing no phase inversion due to RI.
Figure 63. Input Signal
Applications that exceed this rating must externally limit the maximum input current to ±5 mA with an input
resistor as shown in Figure 64.
Figure 64. RIInput Current Protection for
Voltages Exceeding the Supply Voltage
RAIL-TO-RAIL OUTPUT
The approximate output resistance of the LMC7101 is 180Ωsourcing and 130Ωsinking at VS= 3V and 110Ω
sourcing and 80Ωsinking at VS= 5V. Using the calculated output resistance, maximum output voltage swing can
be estimated as a function of load.
CAPACITIVE LOAD TOLERANCE
The LMC7101 can typically directly drive a 100 pF load with VS= 15V at unity gain without oscillating. The unity
gain follower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of op amps.
The combination of the op amp's output impedance and the capacitive load induces phase lag. This results in
either an underdamped pulse response or oscillation.
Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 65. This simple
technique is useful for isolating the capacitive input of multiplexers and A/D converters.
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Figure 65. Resistive Isolation
of a 330 pF Capacitive Load
COMPENSATING FOR INPUT CAPACITANCE WHEN USING LARGE VALUE FEEDBACK
RESISTORS
When using very large value feedback resistors, (usually > 500 kΩ) the large feed back resistance can react with
the input capacitance due to transducers, photo diodes, and circuit board parasitics to reduce phase margins.
The effect of input capacitance can be compensated for by adding a feedback capacitor. The feedback capacitor
(as in Figure 66), Cfis first estimated by:
(1)
or R1CIN ≤R2Cf(2)
which typically provides significant overcompensation.
Printed circuit board stray capacitance may be larger or smaller than that of a breadboard, so the actual optimum
value for CFmay be different. The values of CFshould be checked on the actual circuit. (Refer to the LMC660
quad CMOS amplifier data sheet for a more detailed discussion.)
Figure 66. Cancelling the Effect of Input Capacitance
20 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LMC7101 LMC7101Q
LMC7101, LMC7101Q
www.ti.com
SNOS719F –SEPTEMBER 1999–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision E (March 2013) to Revision F Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 20
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LMC7101 LMC7101Q
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMC7101AIM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A00A
LMC7101AIM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00A
LMC7101AIM5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 A00A
LMC7101AIM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00A
LMC7101BIM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A00B
LMC7101BIM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00B
LMC7101BIM5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 A00B
LMC7101BIM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00B
LMC7101QM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AT6A
LMC7101QM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AT6A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMC7101AIM5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMC7101AIM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMC7101AIM5X SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMC7101BIM5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMC7101BIM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMC7101BIM5X SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMC7101BIM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMC7101QM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMC7101QM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMC7101AIM5 SOT-23 DBV 5 1000 210.0 185.0 35.0
LMC7101AIM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMC7101AIM5X SOT-23 DBV 5 3000 210.0 185.0 35.0
LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMC7101BIM5 SOT-23 DBV 5 1000 210.0 185.0 35.0
LMC7101BIM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMC7101BIM5X SOT-23 DBV 5 3000 210.0 185.0 35.0
LMC7101BIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMC7101QM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMC7101QM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 2
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