LM4871 www.ti.com SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 LM4871 3W Audio Power Amplifier with Shutdown Mode Check for Samples: LM4871 FEATURES DESCRIPTION * The LM4871 is a mono bridged audio power amplifier capable of delivering 3W of continuous average power into a 3 load with less than 10% THD when powered by a 5V power supply (see Note). To conserve power in portable applications, the LM4871's micropower shutdown mode (IQ = 0.6A, typ) is activated when VDD is applied to the SHUTDOWN pin. 1 2 * * * * No Output Coupling Capacitors, Bootstrap Capacitors, or Snubber Circuits Required Unity-gain Stable WSON, VSSOP, SOIC, or PDIP Packaging External Gain Configuration Capability Pin Compatible with the LM4861 APPLICATIONS * * * Portable Computers Desktop Computers Low Voltage Audio Systems KEY SPECIFICATIONS * * * * PO at 10% THD+N, 1kHz - LM4871LD: 3 , 4 Loads; 3W (typ), 2.5 W (typ) - All other LM4871 Packages: 8 load 1.5 W (typ) Shutdown Current 0.6A (typ) Supply Voltage Range 2.0V to 5.5 V THD at 1kHz at 1W Continuous Average Output Power into 8 0.5% (max) Boomer audio power amplifiers are designed specifically to provide high power, high fidelity audio output. They require few external components and operate on low supply voltages from 2.0V to 5.5V. Since the LM4871 does not require output coupling capacitors, bootstrap capacitors, or snubber networks, it is ideally suited for low-power portable systems that require minimum volume and weight. Additional LM4871 features include thermal shutdown protection, unity-gain stability, and external gain set. Note: An LM4871LD that has been properly mounted to a circuit board will deliver 3W into 3 (at 10% THD). The other package options for the LM4871 will deliver 1.5W into 8 (at 10% THD). See the Application Information section for further information concerning the LM4871LD, LM4871MM, LM4871M, and the LM4871N. Connection Diagrams Figure 1. VSSOP, Small Outline, and PDIP Package Top View See Package Number DGK0008A, D0008A, or D0008E Figure 2. WSON Package (Top View) See Package Number NGN0008A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2013, Texas Instruments Incorporated LM4871 SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 www.ti.com Typical Application Figure 3. Typical Audio Amplifier Application Circuit These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 LM4871 www.ti.com SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 Absolute Maximum Ratings (1) (2) Supply Voltage 6.0V -65C to +150C Supply Temperature -0.3V to VDD to +0.3V Input Voltage Power Dissipation (3) Internally Limited (4) 5000V ESD Susceptibility ESD Susceptibility (5) 250V Junction Temperature 150C Soldering Information Small Outline Package Vapor Phase (60 sec.) 215C Infrared (15 sec.) 220C JC (typ)--D0008A 35C/W JA (typ)--D0008A 140C/W JC (typ)--D0008E 37C/W JA (typ)--D0008E 107C/W JC (typ)--DGK0008A 56C/W JA (typ)--DGK0008A 210C/W JC (typ)--NGN0008A 4.3C/W JA (typ)--NGN0008A 56C/W (6) (1) (2) (3) (4) (5) (6) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature TA. The maximum allowable power dissipation is PDMAX = (TJMAX-TA)/JA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4871, TJMAX = 150C. For the JA's for different packages, please see the Application Information section or the absolute maximum ratings section. Human body model, 100pF discharged through a 1.5k resistor. Machine Model, 220pF-240pF discharged through all pins. The given JA is for an LM4871 packaged in an NGN0008A with the Exposed-DAP soldered to an exposed 1in2 area of 1oz printed circuit board copper. Operating Ratings Temperature Range TMIN TA TMAX -40C TA 85C 2.0V VDD 5.5V Supply Voltage Electrical Characteristics (1) (2) The following specifications apply for VDD = 5V and RL = 8 unless otherwise specified. Limits apply for TA = 25C. LM4871 Symbol Parameter Conditions Min (3) Units (Limits) Typical (4) Limit (3) 5.5 V 10.0 mA VDD Supply Voltage IDD Quiescent Power Supply Current VIN = 0V, Io = 0A 6.5 ISD Shutdown Current VPIN1 = VDD 0.6 2 A VOS Output Offset Voltage VIN = 0V 5.0 50 mV (1) (2) (3) (4) 2.0 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. All voltages are measured with respect to the ground pin, unless otherwise specified. Typicals are specified at 25C and represent the parametric norm. Limits are specified to TI's AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 3 LM4871 SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 www.ti.com Electrical Characteristics(1)(2) (continued) The following specifications apply for VDD = 5V and RL = 8 unless otherwise specified. Limits apply for TA = 25C. LM4871 Symbol Po Output Power THD+N PSRR (5) Parameter Conditions Min (3) Typical (4) Limit (3) Units (Limits) THD = 1%, f = 1kHz LM4871LD, RL = 3 (5) LM4871LD, RL = 4 (5) LM4871, RL = 8 (5) 2.38 2 1.2 THD+N = 10%, f = 1kHz LM4871LD, RL = 3 (5) LM4871LD, RL = 4 (5) LM4871, RL = 8 (5) 3 2.5 1.5 Total Harmonic Distortion+Noise 20Hz f 20kHz, AVD = 2 LM4871LD, RL = 4, P O = 1.6W LM4871, RL = 8, P O = 1W 0.13 0.25 % Power Supply Rejection Ratio VDD = 4.9V to 5.1V 60 dB W W When driving 3 or 4 loads from a 5V supply, the LM4871LD must be mounted to a circuit board. External Components Description (Figure 3) Components 4 Functional Description 1. Ri Inverting input resistance that sets the closed-loop gain in conjunction with Rf. This resistor also forms a high pass filter with Ci at fC= 1/(2 RiCi). 2. Ci Input coupling capacitor that blocks the DC voltage at the amplifiers input terminals. Also creates a highpass filter with Ri at fc = 1/(2 RiCi). Refer to the section, Proper Selection of External Components, for an explanation of how to determine the value of Ci. 3. Rf Feedback resistance that sets the closed-loop gain in conjunction with Ri. 4. CS Supply bypass capacitor that provides power supply filtering. Refer to the Power Supply Bypassing section for information concerning proper placement and selection of the supply bypass capacitor. 5. CB Bypass pin capacitor that provides half-supply filtering. Refer to the section, Proper Selection of External Components, for information concerning proper placement and selection of CB. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 LM4871 www.ti.com SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 Typical Performance Characteristics NGN Specific Characteristics LM4871LD THD+N vs Output Power LM4871LD THD+N vs Frequency Figure 4. Figure 5. LM4871LD THD+N vs Frequency LM4871LD THD+N vs Output Power Figure 6. Figure 7. LM4871LD Power Dissipation vs Output Power LM4871LD Power Derating Curve Figure 8. This curve shows the LM4871LD's thermal dissipation ability at different ambient temperatures given the exposed-DAP of the part is soldered to a plane of 1oz. Cu with an area given in the label of each curve. This label also designates whether the plane exists on the same (top) layer as the chip, on the bottom layer, or on both layers. Infinite heatsink and unattached (no heatsink) conditions are also shown. Figure 9. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 5 LM4871 SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 www.ti.com Typical Performance Characteristics Non-NGN Specific Characteristics 6 THD+N vs Frequency THD+N vs Frequency Figure 10. Figure 11. THD+N vs Frequency THD+N vs Output Power Figure 12. Figure 13. THD+N vs Output Power THD+N vs Output Power Figure 14. Figure 15. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 LM4871 www.ti.com SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 Typical Performance Characteristics Non-NGN Specific Characteristics (continued) Output Power vs Supply Voltage Output Power vs Supply Voltage Figure 16. Figure 17. Output Power vs Supply Voltage Output Power vs Load Resistance Figure 18. Figure 19. Power Dissipation vs Output Power Figure 20. Power Derating Curve Figure 21. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 7 LM4871 SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 www.ti.com Typical Performance Characteristics Non-NGN Specific Characteristics (continued) Clipping Voltage vs Supply Voltage 8 Noise Floor Figure 22. Figure 23. Frequency Response vs Input Capacitor Size Power Supply Rejection Ratio Figure 24. Figure 25. Open Loop Frequency Response Supply Current vs Supply Voltage Figure 26. Figure 27. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 LM4871 www.ti.com SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 APPLICATION INFORMATION EXPOSED-DAP PACKAGE PCB MOUNTING CONSIDERATION The LM4871's exposed-DAP (die attach paddle) package (NGN) provides a low thermal resistance between the die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the surrounding PCB copper traces, ground plane, and surrounding air. The result is a low voltage audio power amplifier that produces 2W at 1% THD with a 4 load. This high power is achieved through careful consideration of necessary thermal design. Failing to optimize thermal design may compromise the LM4871's high power performance and activate unwanted, though necessary, thermal shutdown protection. The NGN package must have its DAP soldered to a copper pad on the PCB. The DAP's PCB copper pad is connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat sink, and radiation area. Place the heat sink area on either outside plane in the case of a two-sided PCB, or on an inner layer of a board with more than two layers. Connect the DAP copper pad to the inner layer or backside copper heat sink area with 4(2x2) vias. The via diameter should be 0.012in-0.013in with a 1.27mm pitch. Ensure efficient thermal conductivity by plating through the vias. Best thermal performance is achieved with the largest practical heat sink area. If the heatsink and amplifier share the same PCB layer, a nominal 2.5in2 area is necessary for 5V operation with a 4 load. Heatsink areas not placed on the same PCB layer as the LM4871 should be 5in2 (min) for the same supply voltage and load resistance. The last two area recommendations apply for 25C ambient temperature. Increase the area to compensate for ambient temperatures above 25C. The LM4871's power de-rating curve in the Typical Performance Characteristics shows the maximum power dissipation versus temperature. An example PCB layout for the NGN package is shown in the Demonstration Board Layout section. Further detailed and specific information concerning PCB layout, fabrication, and mounting an NGN (WSON) package is available from TI's Package Engineering Group under application note AN-1187 (Literature Number SNOA401). PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3 AND 4 LOADS Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependant on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1 trace resistance reduces the output power dissipated by a 4 load from 2.0W to 1.95W. This problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. BRIDGE CONFIGURATION EXPLANATION As shown in Figure 3, the LM4871 has two operational amplifiers internally, allowing for a few different amplifier configurations. The first amplifier's gain is externally configurable; the second amplifier is internally fixed in a unity-gain, inverting configuration. The closed-loop gain of the first amplifier is set by selecting the ratio of Rf to Ri while the second amplifier's gain is fixed by the two internal 40k resistors. Figure 3 shows that the output of amplifier one serves as the input to amplifier two, which results in both amplifiers producing signals identical in magnitude, but 180 out of phase. Consequently, the differential gain for the IC is AVD= 2 *(Rf/Ri) (1) By driving the load differentially through outputs Vo1 and Vo2, an amplifier configuration commonly referred to as "bridged mode" is established. Bridged mode operation is different from the classical single-ended amplifier configuration where one side of its load is connected to ground. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 9 LM4871 SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 www.ti.com A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited or clipped. In order to choose an amplifier's closedloop gain without causing excessive clipping, please refer to the Audio Power Amplifier Design section. Another advantage of the differential bridge output is no net DC voltage across load. This results from biasing VO1 and VO2 at the same DC voltage, in this case VDD/2 . This eliminates the coupling capacitor that single supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a single-ended configuration forces a single supply amplifier's half-supply bias voltage across the load. The current flow created by the halfsupply bias voltage increases internal IC power dissipation and my permanently damage loads such as speakers. POWER DISSIPATION Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation. Equation 2 states the maximum power dissipation point for a bridge amplifier operating at a given supply voltage and driving a specified output load. PDMAX = 4*(VDD)2/(22RL) (2) Since the LM4871 has two operational amplifiers in one package, the maximum internal power dissipation is 4 times that of a single-ended ampifier. Even with this substantial increase in power dissipation, the LM4871 does not require heatsinking under most operating conditions and output loading. From Equation 2, assuming a 5V power supply and an 8 load, the maximum power dissipation point is 625 mW. The maximum power dissipation point obtained from Equation 2 must not be greater than the power dissipation that results from Equation 3: PDMAX = (TJMAX-TA)/JA (3) For the SOIC package, JA = 140C/W, for the PDIP package, JA = 107C/W, and for the VSSOP package, JA = 210C/W assuming free air operation. For the NGN package soldered to a DAP pad that expands to a copper area of 1.0in2 on a PCB, the LM4871's JA is 56C/W. TJMAX = 150C for the LM4871. The JA can be decreased by using some form of heat sinking. The resultant JA will be the summation of the JC, CS, and SA. JC is the junction to case of the package (or to the exposed DAP, as is the case with the NGN package), CS is the case to heat sink thermal resistance and SA is the heat sink to ambient thermal resistance. By adding additional copper area around the LM4871, the JA can be reduced from its free air value for the SOIC and VSSOP packages. Increasing the copper area around the NGN package from 1.0in2 to 2.0in2 area results in a JA decrease to 46C/W. Depending on the ambient temperature, TA, and the JA, Equation 3 can be used to find the maximum internal power dissipation supported by the IC packaging. If the result of Equation 2 is greater than that of Equation 3, then either the supply voltage must be decreased, the load impedance increased, the JA decreased, or the ambient temperature reduced. For the typical application of a 5V power supply, with an 8 load, and no additional heatsinking, the maximum ambient temperature possible without violating the maximum junction temperature is approximately 61C provided that device operation is around the maximum power dissipation point and assuming surface mount packaging. For the NGN package in a typical application of a 5V power supply, with a 4 load, and 1.0in2 copper area soldered to the exposed DAP pad, the maximum ambient temperature is approximately 77C providing device operation is around the maximum power dissipation point. Internal power dissipation is a function of output power. If typical operation is not around the maximum power dissipation point, the ambient temperature can be increased. Refer to the Typical Performance Characteristics curves for power dissipation information for different output powers and output loading. POWER SUPPLY BYPASSING As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on both the bypass and power supply pins should be as close to the LM4871 as possible. The capacitor connected between the bypass pin and ground improves the internal bias voltage's stability, producing improved PSRR. The improvements to PSRR increase as the bypass pin capacitor increases. Typical applications employ a 5V regulator with 10F and a 0.1F bypass capacitors which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of the LM4871 with a 1F tantalum capacitor. The selection of bypass capacitors, especially CB, is dependent upon PSRR requirements, click and pop performance as explained in the section, Proper Selection of External Components, system cost, and size constraints. 10 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 LM4871 www.ti.com SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 SHUTDOWN FUNCTION In order to reduce power consumption while not in use, the LM4871 contains a shutdown pin to externally turn off the amplifier's bias circuitry. This shutdown feature turns the amplifier off when a logic high is placed on the shutdown pin. The trigger point between a logic low and logic high level is typically half- supply. It is best to switch between ground and supply to provide maximum device performance. By switching the shutdown pin to VDD, the LM4871 supply current draw will be minimized in idle mode. While the device will be disabled with shutdown pin voltages less then VDD, the idle current may be greater than the typical value of 0.6A. In either case, the shutdown pin should be tied to a definite voltage to avoid unwanted state changes. In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry which provides a quick, smooth transition into shutdown. Another solution is to use a single-pole, single-throw switch in conjunction with an external pull-up resistor. When the switch is closed, the shutdown pin is connected to ground and enables the amplifier. If the switch is open, then the external pull-up resistor will disable the LM4871. This scheme ensures that the shutdown pin will not float thus preventing unwanted state changes. PROPER SELECTION OF EXTERNAL COMPONENTS Proper selection of external components in applications using integrated power amplifiers is critical to optimize device and system performance. While the LM4871 is tolerant of external component combinations, consideration to component values must be used to maximize overall system quality. The LM4871 is unity-gain stable which gives a designer maximum system flexibility. The LM4871 should be used in low gain configurations to minimize THD+N values, and maximize the signal to noise ratio. Low gain configurations require large input signals to obtain a given output power. Input signals equal to or greater than 1 Vrms are available from sources such as audio codecs. Please refer to the section, Audio Power Amplifier Design, for a more complete explanation of proper gain selection. Besides gain, one of the major considerations is the closed-loop bandwidth of the amplifier. To a large extent, the bandwidth is dictated by the choice of external components shown in Audio Power Amplifier Design. The input coupling capacitor, Ci, forms a first order high pass filter which limits low frequency response. This value should be chosen based on needed frequency response for a few distinct reasons. Selection Of Input Capacitor Size Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized capacitor is needed to couple in low frequencies without severe attenuation. But in many cases the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 100Hz to 150Hz. Thus, using a large input capacitor may not increase actual system performance. In addition to system cost and size, click and pop performance is effected by the size of the input coupling capacitor, Ci. A larger input coupling capacitor requires more charge to reach its quiescent DC voltage (nominally 1/2 VDD). This charge comes from the output via the feedback and is apt to create pops upon device enable. Thus, by minimizing the capacitor size based on necessary low frequency response, turn-on pops can be minimized. Besides minimizing the input capacitor size, careful consideration should be paid to the bypass capacitor value. Bypass capacitor, CB, is the most critical component to minimize turn-on pops since it determines how fast the LM4871 turns on. The slower the LM4871's outputs ramp to their quiescent DC voltage (nominally 1/2 VDD), the smaller the turn-on pop. Choosing CB equal to 1.0F along with a small value of Ci (in the range of 0.1F to 0.39F), should produce a virtually clickless and popless shutdown function. While the device will function properly, (no oscillations or motorboating), with CB equal to 0.1F, the device will be much more susceptible to turn-on clicks and pops. Thus, a value of CB equal to 1.0F is recommended in all but the most cost sensitive designs. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 11 LM4871 SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 www.ti.com AUDIO POWER AMPLIFIER DESIGN Design a 1W/8 Audio Amplifier Given: Power Output 1 Wrms Load Impedance 8 Input Level 1 Vrms Input Impedance 20 k Bandwidth 100 Hz-20 kHz 0.25 dB A designer must first determine the minimum supply rail to obtain the specified output power. By extrapolating from the Output Power vs Supply Voltage graphs in the Typical Performance Characteristics section, the supply rail can be easily found. A second way to determine the minimum supply rail is to calculate the required Vopeak using Equation 4 and add the output voltage. Using this method, the minimum supply voltage would be (Vopeak + (VODTOP + VODBOT)), where VODBOT and VODTOP are extrapolated from the Dropout Voltage vs Supply Voltage curve in the Typical Performance Characteristics section. (4) Using the Output Power vs Supply Voltage graph for an 8 load, the minimum supply rail is 4.6V. But since 5V is a standard voltage in most applications, it is chosen for the supply rail. Extra supply voltage creates headroom that allows the LM4871 to reproduce peaks in excess of 1W without producing audible distortion. At this time, the designer must make sure that the power supply choice along with the output impedance does not violate the conditions explained in the POWER DISSIPATION section. Once the power dissipation equations have been addressed, the required differential gain can be determined from Equation 5. (5) (6) Rf/Ri = AVD/2 From Equation 5, the minimum AVD is 2.83; use AVD = 3. Since the desired input impedance was 20k, and with a AVD impedance of 2, a ratio of 1.5:1 of Rf to Ri results in an allocation of Ri = 20k and Rf = 30k. The final design step is to address the bandwidth requirements which must be stated as a pair of -3dB frequency points. Five times away from a -3dB point is 0.17dB down from passband response which is better than the required 0.25dB specified. fL = 100Hz/5 = 20Hz fH = 20kHz * 5 = 100kHz As stated in the External Components Description section, Ri in conjunction with Ci create a highpass filter. Ci 1/(2*20k*20Hz) = 0.397F; use 0.39F The high frequency pole is determined by the product of the desired frequency pole, fH, and the differential gain, AVD. With a AVD = 3 and fH = 100kHz, the resulting GBWP = 150kHz which is much smaller than the LM4871 GBWP of 4MHz. This figure displays that if a designer has a need to design an amplifier with a higher differential gain, the LM4871 can still be used without running into bandwidth limitations. 12 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 LM4871 www.ti.com SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 Demonstration Board Layout Figure 28. Recommended NGN PC Board Layout: Component-Side Silkscreen Figure 29. Recommended NGN PC Board Layout: Component-Side Layout Figure 30. Recommended NGN PC Board Layout: Bottom-Side Layout LM4871 MDA MWA 3W Audio Power Amplifier With Shutdown Mode Figure 31. Die Layout (C - Step) Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 13 LM4871 SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 www.ti.com Die/Wafer Characteristics Fabrication Attributes General Die Information Physical Die Identification LM4871C Bond Pad Opening Size (min) 102m x 102m Die Step C Bond Pad Metalization 0.5% COPPER_BAL. ALUMINUM Passivation NITRIDE Wafer Diameter Physical Attributes 150mm Back Side Metal BARE BACK Dise Size (Drawn) 1372m x 1758m 54mils x 69mils Back Side Connection GND Thickness 406m Nominal Min Pitch 164m Nominal Special Assembly Requirements: Note: Actual die size is rounded to the nearest micron. Die Bond Pad Coordinate Locations (C - Step) (Referenced to die center, coordinates in m) NC = No Connection SIGNAL NAME PAD# NUMBER X/Y COORDINATES PAD SIZE X Y X Y SHUTDOWN 1 -559 541 102 x 102 BYPASS 2 -559 376 102 x 102 NC 3 -559 -45 102 x 210 INPUT + 4 -559 -248 102 x 102 INPUT - 5 -559 -486 102 x 102 GND 6 -476 -725 102 x 102 VOUT 1 7 -135 -598 102 x 210 GND 8 554 -686 102 x 102 VDD 9 554 -4 102 x 210 GND 10 554 568 102 x 102 VOUT 2 11 -135 598 102 x 210 GND 12 -473 752 102 x 102 14 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 LM4871 www.ti.com SNAS002F - FEBRUARY 2000 - REVISED MAY 2013 REVISION HISTORY Changes from Revision E (May 2013) to Revision F * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM4871 15 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM4871LD/NOPB ACTIVE WSON NGN 8 1000 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR -40 to 85 L4871 LM4871M ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 85 4871 LM4871M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 4871 LM4871MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 G71 LM4871MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 G71 LM4871MX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 85 4871 LM4871MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 4871 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM4871LD/NOPB WSON NGN 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM4871MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM4871MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM4871MX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM4871MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4871LD/NOPB WSON NGN 8 1000 210.0 185.0 35.0 LM4871MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM4871MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LM4871MX SOIC D 8 2500 367.0 367.0 35.0 LM4871MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE NGN0008A WSON - 0.8 mm max height SCALE 3.000 PLASTIC SMALL OUTLINE - NO LEAD 4.1 3.9 A B PIN 1 INDEX AREA 4.1 3.9 PIN 1 ID DETAIL A PIN 1 ID C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 C 2.2 0.05 EXPOSED THERMAL PAD SYMM (0.2) TYP 6X 0.8 4 5 2X 2.4 SYMM 9 3 0.05 SEE DETAIL A 8 1 8X (0.25) (0.25) PIN 1 ID (0.2) 8X 0.6 0.4 0.35 0.25 0.1 0.05 (0.15) C A B C 4214794/A 11/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT NGN0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (2.2) SYMM 8X (0.5) 1 8 8X (0.3) SYMM 9 (3) (1.25) 6X (0.8) 4 (R0.05) TYP 5 ( 0.2) VIA TYP (0.85) (3.3) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND EXPOSED METAL SOLDER MASK OPENING METAL EXPOSED METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4214794/A 11/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN NGN0008A WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 0.59 SYMM 8X (0.5) METAL TYP 1 8 8X (0.3) 4X (1.31) SYMM 9 (0.755) 6X (0.8) 5 4 (R0.05) TYP 4X (0.98) (3.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4214794/A 11/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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