Rev. A | Page 17 of 174 | July 2017
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
blocks on the processor. The digital audio interface carries three
types of information: audio data, nonaudio data (compressed
data), and timing information.
The S/PDIF interface supports one stereo channel or com-
pressed audio streams. The S/PDIF transmitter and receiver are
AES3 compliant and support the sample rate from 24 KHz to
192 KHz. The S/PDIF receiver supports professional jitter
standards.
The S/PDIF receiver/transmitter has no separate DMA chan-
nels. It receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left justified, I
2
S, or
right justified with word widths of 16, 18, 20, or 24 bits. The
serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from various sources, such as the
SPORTs, external pins, and the precision clock generators
(PCGs), and are controlled by the SRU control registers.
Precision Clock Generators (PCG)
The precision clock generators (PCG) consist of four units:
units A/B located in the DAI0 block, and units C/D located in
the DAI1 block. The PCG can generate a pair of signals (clock
and frame sync) derived from a clock input signal (CLKIN1-0,
SCLK0, or DAI pin buffer). Each unit can also access the oppo-
site DAI unit. All units are identical in functionality and operate
independently of each other. The two signals generated by each
unit are normally used as a serial bit clock/frame sync pair.
Enhanced Parallel Peripheral Interface (EPPI)
The processors provide an enhanced parallel peripheral inter-
face (EPPI) that supports data widths up to 24 bits. The EPPI
supports direct connection to TFT LCD panels, parallel ADCs
and DACs, video encoders and decoders, image sensor mod-
ules, and other general-purpose peripherals.
The features supported in the EPPI module include the
following:
• Programmable data length of 8 bits, 10 bits, 12 bits, 14 bits,
16 bits, 18 bits, and 24 bits per clock.
• Various framed, nonframed, and general-purpose operat-
ing modes. Frame syncs can be generated internally or can
be supplied by an external device.
• ITU-656 status word error detection and correction for
ITU-656 receive modes and ITU-656 preamble and status
word decoding.
• Optional packing and unpacking of data to/from 32 bits
from/to 8 bits, 16 bits, and 24 bits. If packing/unpacking is
enabled, configure endianness to change the order of pack-
ing/unpacking of the bytes/words.
• RGB888 can be converted to RGB666 or RGB565 for trans-
mit modes.
• Various deinterleaving/interleaving modes for receiv-
ing/transmitting 4:2:2 YCrCb data.
• Configurable LCD data enable output available on Frame
Sync 3.
Universal Asynchronous Receiver/Transmitter
(UART) Ports
The processors provide three full-duplex universal asynchro-
nous receiver/transmitter (UART) ports, fully compatible with
PC standard UARTs. Each UART port provides a simplified
UART interface to other peripherals or hosts, supporting full-
duplex, DMA supported, asynchronous transfers of serial data.
A UART port includes support for five to eight data bits as well
as no parity, even parity, or odd parity.
Optionally, an additional address bit can be transferred to inter-
rupt only addressed nodes in multidrop bus (MDB) systems. A
frame is terminated by a configurable number of stop bits.
The UART ports support automatic hardware flow control
through the clear to send (CTS) input and request to send (RTS)
output with programmable assertion first in, first out (FIFO)
levels.
To help support the Local Interconnect Network (LIN) proto-
cols, a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a pro-
grammable interframe space.
Serial Peripheral Interface (SPI) Ports
The processors have three industry-standard SPI-compatible
ports that allow the processors to communicate with multiple
SPI-compatible devices.
The baseline SPI peripheral is a synchronous, four-wire inter-
face consisting of two data pins, one device select pin, and a
gated clock pin. The two data pins allow full-duplex operation
to other SPI-compatible devices. An extra two (optional) data
pins are provided to support quad SPI operation. Enhanced
modes of operation, such as flow control, fast mode, and dual-
I/O mode (DIOM), are also supported. A direct memory access
(DMA) mode allows for transferring several words with mini-
mal central processing unit (CPU) interaction.
With a range of configurable options, the SPI ports provide a
glueless hardware interface with other SPI-compatible devices
in master mode, slave mode, and multimaster environments.
The SPI peripheral includes programmable baud rates, clock
phase, and clock polarity. The peripheral can operate in a multi-
master environment by interfacing with several other devices,
acting as either a master device or a slave device. In a multimas-
ter environment, the SPI peripheral uses open-drain outputs to
avoid data bus contention. The flow control features enable slow
slave devices to interface with fast master devices by providing
an SPI ready pin (SPI_RDY) which flexibly controls the
transfers.
The baud rate and clock phase/polarities of the SPI port are pro-
grammable. The port has integrated DMA channels for both
transmit and receive data streams.
Link Ports (LP)
Two 8-bit wide link ports (LP) can connect to the link ports of
other DSPs or peripherals. LP are bidirectional ports that have
eight data lines, an acknowledge line, and a clock line.