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SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.

SHARC+ Dual Core

DSP with ARM Cortex-A5

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

Rev. A Document Feedback

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SYSTEM FEATURES

Dual enhanced SHARC+ high performance floating-point

cores

Up to 500 MHz per SHARC+ core

Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core

with parity (optional ability to configure as cache)

32-bit, 40-bit, and 64-bit floating-point support

32-bit fixed point

Byte, short-word, word, long-word addressed

ARM Cortex-A5 core

500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle

32 kB L1 instruction cache/32 kB L1 data cache

256 kB Level 2 (L2) cache with parity

Powerful DMA system

On-chip memory protection

Integrated safety features

19 mm × 19 mm 349/529 BGA (0.8 pitch), RoHS compliant

Low system power across automotive temperature range

MEMORY

Large on-chip L2 SRAM with ECC protection, up to 256 kB

On-chip L2 ROM (512 kB)

Two Level 3 (L3) interfaces optimized for low system power,

providing a 16-bit interface to DDR3 (supporting 1.5 V

capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices

ADDITIONAL FEATURES

Security and Protection

Cryptographic hardware accelerators

Fast secure boot with IP protection

Support for ARM TrustZone

Accelerators

High performance pipelined FFT/IFFT engine

FIR, IIR, HAE, SINC offload engines

Figure 1. Processor Block Diagram

SYSTEM CONTROL

FAULT MANAGEMENT

SYSTEM PROTECTION (SPU)

SECURITY AND PROTECTION

ARM® TrustZone® SECURITY

DUAL CRC

WATCHDOGS

THERMAL MONITOR UNIT (TMU)

OTP MEMORY

TRIGGER ROUTING (TRU)

SYS EVENT CORE 0 (GIC)

PROGRAM FLOW

REAL TIME CLOCK (RTC)

CLOCK GENERATION (CGU)

CLOCK, RESET, AND POWER

POWER MANAGEMENT (DPM)

RESET CONTROL (RCU)

WATCHPOINTS (SWU)

ARM® CoreSight

DEBUG UNIT

SYSTEM MEMORY

PROTECTION UNIT (SMPU)

CLOCK DISTRIBUTION

UNIT (CDU)

DATA

L1 SRAM (PARITY)

5 Mb (640 kB)

SRAM/CACHE

32 kB L1 I-CACHE

32 kB L1 D-CACHE

SYSTEM

L2 MEMORY

SYSTEM

ACCELERATION

L3 MEMORY

INTERFACES

DDR3

DDR2

LPDDR1

DDR3

DDR2

LPDDR1

DSP FUNCTIONS

(FFT/IFFT, FIR, IIR, HAE/SINC)

L1 SRAM (PARITY)

5 Mb (640 kB)

SRAM/CACHE

ENCRYPTION/DECRYPTION

L1 CACHE

L2 CACHE

256 kB (PARITY)

DATA

SYSTEM CROSSBAR AND DMA SUBSYSTEM

CORE 1 CORE 2CORE 0

PERIPHERALS

3× I

2× LINK PORTS

2× SPI + 1× QUAD SPI

3× UARTs

3× ePWM

8× TIMERS + 1× COUNTER

1× EPPI

ADC CONTROL MODULE

(ACM)

ASYNC MEMORY (16-BIT)

SD/SDIO/eMMC

MLB 3-PIN

2× CAN2.0

2× USB 2.0 HS

MLB 6-PIN

PCIe2.0 (1 lane)

HADC (8 CHAN, 12-BIT)

2× EMAC

SINC FILTER

8x SHARC FLAGS

ASRC

2×4 PAIRS

2×1 S/PDIF Rx/Tx

2×2 PRECISION CLOCK

GENERATORS

FULL SPORT

2×4

2x DAI

2x PIN

BUFFER

SIGNAL ROUTING UNIT (SRU)

SRAM

(ECC)

2 Mb

(256 kB)

40–28

102–80

SYS EVENT CORES 1-2 (SEC)

ROM

2 Mb

(256 kB)

ROM

2 Mb

(256 kB)

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TABLE OF CONTENTS

System Features ....................................................... 1

Memory ................................................................ 1

Additional Features .................................................. 1

Table Of Contents .................................................... 2

Revision History ...................................................... 3

General Description ................................................. 4

ARM Cortex-A5 Processor ...................................... 6

SHARC Processor ................................................. 7

SHARC+ Core Architecture .................................... 9

System Infrastructure ........................................... 11

System Memory Map ........................................... 12

Security Features ................................................ 15

Safety Features ................................................... 15

Processor Peripherals ........................................... 16

System Acceleration ............................................ 21

System Design .................................................... 21

System Debug .................................................... 24

Development Tools ............................................. 24

Additional Information ........................................ 25

Related Signal Chains .......................................... 25

Security Features Disclaimer .................................. 25

ADSP-SC58x/ADSP-2158x Detailed Signal

Descriptions ...................................................... 26

349-Ball CSP_BGA Signal Descriptions ....................... 31

GPIO Multiplexing for the 349-Ball CSP_BGA Package .. 40

529-Ball CSP_BGA Signal Descriptions ....................... 43

GPIO Multiplexing for the 529-Ball CSP_BGA Package .. 55

ADSP-SC58x/ADSP-2158x Designer Quick Reference .... 58

Specifications ........................................................ 80

Operating Conditions ........................................... 80

Electrical Characteristics ....................................... 84

HADC .............................................................. 88

TMU ................................................................ 88

Absolute Maximum Ratings ................................... 89

ESD Caution ...................................................... 89

Package Information ............................................ 89

Timing Specifications ........................................... 90

Output Drive Currents ....................................... 154

Test Conditions ................................................ 156

Environmental Conditions .................................. 158

ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball

Assignments .................................................... 159

Numerical by Ball Number .................................. 159

Alphabetical by Pin Name ................................... 161

Configuration of the 349-Ball CSP_BGA ................. 163

ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball

Assignments .................................................... 164

Numerical by Ball Number .................................. 164

Alphabetical by Pin Name ................................... 167

Configuration of the 529-Ball CSP_BGA ................. 170

Outline Dimensions .............................................. 171

Surface-Mount Design ........................................ 172

Planned Automotive Production Products .............. 173

Ordering Guide ................................................ 174

Rev. A | Page 3 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

REVISION HISTORY

7/2017—Rev. 0 to Rev. A

Changes to Processor Block Diagram ............................ 1

Changes to Table 2 and Table 3 in General Description ..... 4

Changes to ARM Cortex-A5 Processor Block Diagram ..... 6

Changes to ADSP-SC58x/ADSP-2158x Memory Map ....... 9

Change to Power Supplies ......................................... 23

Change to Table 10 in Power Management ................... 24

Change to DMC_VREF Description, Table 11 in ADSP-

SC58x/ADSP-2158x Detailed Signal Descriptions ........... 26

Change to VDD_HADC Signal Description, Table 12 in

349-Ball CSP_BGA Signal Descriptions ........................ 31

Change to VDD_HADC Signal Description, Table 19 in

529-Ball CSP_BGA Signal Descriptions ........................ 43

Changes to HADC0_VREFN, HADC0_VREFP, and

VDD_HADC Signal Description and Notes, Table 27 in

ADSP-SC58x/ADSP-2158x Designer Quick Reference ..... 58

Change to PC_10 Driver Type, Table 27 in

ADSP-SC58x/ADSP-2158x Designer Quick Reference ..... 58

Changes to Operating Conditions ............................... 80

Changes to Table 29 and Table 30 in Clock Related Operating

Conditions ............................................................ 82

Changes to Electrical Characteristics ........................... 84

Changes to Table 31, Table 34, and Table 35 in Total Internal

Power Dissipation .................................................. 86

Added Table 41 in TMU .......................................... 88

Changes to Table 42 in Absolute Maximum Ratings ....... 89

Added Table 47 and Figure 13 in SMC Read Cycle Timing With

Reference to SYS_CLKOUT ...................................... 93

Added Table 51 and Figure 17 in SMC Write Cycle Timing

With Reference to SYS_CLKOUT .............................. 97

Change to t

Parameter, Table 55 in DDR2 SDRAM Read

Cycle Timing ....................................................... 100

Change to t

DQSQ

Parameter, Table 61 in DDR3 SDRAM Read

Cycle Timing ....................................................... 106

Changed Timing Requirement Parameter Heading to Switching

Characteristics Heading, Table 84 in DAIx Pin to DAIx Pin

Direct Routing (DAI0 Block and DAI1 Block) .............. 134

Added Table 87 and Figure 58 in PWM — Medium Precision

(MP) Mode Timing ............................................... 136

Changes to Table 88, Table 89, Figure 59, and Figure 62 in

PWM — Heightened Precision (HP) Mode Timing ....... 136

Added Figure 60 and Figure 61 in PWM — Heightened Preci-

sion (HP) Mode Timing .......................................... 136

Changes to Planned Automotive Production Products ... 173

Changes to Ordering Guide ..................................... 174

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ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

GENERAL DESCRIPTION

The ADSP-SC58x/ADSP-2158x processors are members of the

SHARC

family of products. The ADSP-SC58x processor is

based on the SHARC+ dual core and the ARM

Cortex

-A5

core. The ADSP-SC58x/ADSP-2158x SHARC processors are

members of the SIMD SHARC family of digital signal proces-

sors (DSPs) that feature Analog Devices Super Harvard

Architecture. These 32-bit/40-bit/64-bit floating-point proces-

sors are optimized for high performance audio/floating-point

applications with large on-chip static random-access memory

(SRAM), multiple internal buses that eliminate input/output

(I/O) bottlenecks, and innovative digital audio interfaces (DAI).

New additions to the SHARC+ core include cache enhance-

ments and branch prediction, while maintaining instruction set

compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and

memory (see Table 1, Table 2, and Table 3), the ARM Cortex-

A5 and SHARC processor is the platform of choice for applica-

tions that require programmability similar to RISC (reduced

instruction set computing), multimedia support, and leading

edge signal processing in one integrated package. These applica-

tions span a wide array of markets, including automotive, pro

audio, and industrial-based applications that require high float-

ing-point performance.

Table 2 provides comparison information for features that vary

across the standard processors. (N/A in the table means not

applicable.)

Table 3 provides comparison information for features that vary

across the automotive processors. (N/A in the table means not

applicable.)

Table 1. Common Product Features

Product Features ADSP-SC58x/ADSP-2158x

DAI (includes SRU) 2

Full SPORTs 4 per DAI

S/PDIF receive/transmit 1per DAI

ASRCs 4 pair per DAI

PCGs 2 per DAI

C (TWI) 3

Quad-data bit SPI 1

Dual-data bit SPI 2

CAN2.0 2

UARTs 3

Link ports 2

Enhanced PPI 1

GP timer

GP counter 1

Enhanced PWMs

Watchdog timers 2

ADC control module Yes

Static memory controller Yes

Hardware accelerators

High performance FFT/IFFT Yes

FIR/IIR Yes

Harmonic analysis engine Yes

SINC filter Yes

Security cryptographic engine Yes

Multichannel 12-bit ADC 8-channel

Eight timers are available in the 529-BGA package only. The 349-BGA package

does not include Timer 6 and 7.

On the 349-BGA package, the PWM2_AH/AL and PWM2_BH/BL signals are

not available. The PWM2_CH/CL and PWM2_DH/DL signals, however, are

available and can be used in conjunction with PWM2_TRIP0 and PWM2_SYNC

signals.

Rev. A | Page 5 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

Table 2. Comparison of ADSP-SC58x/ADSP-2158x Processor Features

Processor Feature

ADSP-

SC582

ADSP-

SC583

ADSP-

SC584

ADSP-

SC587

ADSP-

SC589

ADSP-

21583

ADSP-

21584

ADSP-

21587

ARM Cortex-A5 (MHz, Max) 500 500 500 500 500 N/A N/A N/A

ARM Core L1 Cache (I, D kB) 32, 32 32, 32 32, 32 32, 32 32, 32 N/A N/A N/A

ARM Core L2 Cache (kB) 256 256 256 256 256 N/A N/A N/A

SHARC+ Core1 (MHz, Max) 500 500 500 500 500 500 500 500

SHARC+ Core2 (MHz, Max) N/A 500 500 500 500 500 500 500

SHARC L1 SRAM (kB) 640 384 640 640 640 384 640 640

System

Memory

L2 SRAM (Shared) (kB) 256 256 256 256 256 256 256 256

L2 ROM (Shared) (kB) 512 512 512 512 512 512 512 512

DDR3/DDR2/LPDDR1

Controller (16-bit) 11122112

USB 2.0 HS + PHY (Host/Device/OTG)11111N/AN/AN/A

USB 2.0 HS + PHY (Host/Device) N/A N/A N/A 1 1 N/A N/A N/A

10/100 Std EMAC N/A N/A N/A 1 1 N/A N/A N/A

10/100/1000 /AVB EMAC + Timer

IEEE 1588 11111N/AN/AN/A

SDIO/eMMC N/A N/A N/A 1 1 N/A N/A N/A

PCIe 2.0 (1 Lane) N/A N/A N/A N/A 1 N/A N/A N/A

RTC N/A N/A N/A 1 1 N/A N/A 1

GPIO Ports Port A to E Port A to E Port A to E Port A to G Port A to G Port A to E Port A to E Port A to G

GPIO + DAI Pins 80 + 28 80 + 28 80 + 28 102 + 40 102 + 40 80 + 28 80 + 28 102 + 40

19 mm × 19 mm Package Options 349-BGA 349-BGA 349-BGA 529-BGA 529-BGA 349-BGA 349-BGA 529-BGA

Table 3. Comparison of ADSP-SC58x/ADSP-2158x Processor Features for Automotive

Processor Feature ADSP-SC582W ADSP-SC583W ADSP-SC584W ADSP-SC587W ADSP-21583W ADSP-21584W

ARM Cortex-A5 (MHz, Max) 500 500 500 500 N/A N/A

ARM Core L1 Cache (I, D kB) 32, 32 32, 32 32, 32 32, 32 N/A N/A

ARM Core L2 Cache (kB) 256 256 256 256 N/A N/A

SHARC+ Core1 (MHz, Max) 500 500 500 500 500 500

SHARC+ Core2 (MHz, Max) N/A 500 500 500 500 500

SHARC L1 SRAM (kB) 640 384 640 640 384 640

System

Memory

L2 SRAM (Shared) (kB) 256 256 256 256 256 256

L2 ROM (Shared) (kB) 512 512 512 512 512 512

DDR3/DDR2/LPDDR1

Controller (16-bit) 111211

USB 2.0 HS + PHY (Host/Device/OTG)1111N/AN/A

USB 2.0 HS + PHY (Host/Device) N/A N/A N/A 1 N/A N/A

10/100 Std EMAC N/A N/A N/A 1 N/A N/A

10/100/1000/AVB EMAC + Timer

IEEE 1588 1111N/AN/A

SDIO/eMMC N/A N/A N/A 1 N/A N/A

PCIe 2.0 (1 Lane) N/A N/A N/A N/A N/A N/A

MLB 3-Pin/6-Pin 111111

RTC N/A N/A N/A 1 N/A N/A

GPIO Ports Port A to E Port A to E Port A to E Port A to G Port A to E Port A to E

GPIO + DAI Pins 80 + 28 80 + 28 80 + 28 102 + 40 80 + 28 80 + 28

19 mm × 19 mm Package Options 349-BGA 349-BGA 349-BGA 529-BGA 349-BGA 349-BGA

Rev. A | Page 6 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

ARM CORTEX-A5 PROCESSOR

The ARM Cortex-A5 processor (see Figure 2) is a high perfor-

mance processor with the following features:

• Instruction cache unit (32 Kb) and data L1 cache unit

(32 Kb)

• In order pipeline with dynamic branch prediction

• ARM, Thumb, and ThumbEE instruction set support

•ARM TrustZone

security extensions

• Harvard L1 memory system with a memory management

unit (MMU)

•ARM v7 debug architecture

• Trace support through an embedded trace macrocell

(ETM) interface

• Extension—vector floating-point unit (IEEE 754) with

trapless execution

• Extension—media processing engine (MPE) with NEON

technology

• Extension—Jazelle hardware acceleration

Figure 2. ARM Cortex-A5 Processor Block Diagram

DATA STORE

BUFFER (STB)

BUS INTERFACE UNIT (BIU)

PREFETCH UNIT AND BRANCH PREDICTOR (PFU)

DATA PROCESSING UNIT (DPU)

DATA MICRO-TLB INSTRUCTION MICRO-TLB

DEBUG

DATA CACHE

UNIT (DCU) MAIN TRANSMISSION

LOOKINSIDE BUFFER (TLB)

INSTRUCTION CACHE

UNIT (ICU)

CORTEX-A5

PROCESSOR

EMBEDDED TRACE MACROCELL

(ETM) INTERFACE

L2 CACHE

CONTROLLER

(CoreLinkTM PL-310)

256 KB

SYSTEM FABRIC

TO OTHER CORES

ARM Cortex-A5 BUS MASTER PORT

CoreSight INTERFACE

CP15

NEON MEDIA

PROCESSING

ENGINE

32 KB 32 KB

GENERIC INTERRUPT

CONTROLLER

(PrimeCell® PL-390)

DATA MASTER PORTS

SHARC PROCESSORS

Rev. A | Page 7 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

Generic Interrupt Controller (GIC), PL390

(ADSP-SC58x Only)

The generic interrupt controller (GIC) is a centralized resource

for supporting and managing interrupts. The GIC splits into the

distributor block (GICPORT0) and the CPU interface block

(GICPORT1).

Generic Interrupt Controller Port0 (GICPORT0)

The GICPORT0 distributor block performs interrupt prioritiza-

tion and distribution to the GICPORT1 blocks that connect to

the processors in the system. It centralizes all interrupt sources,

determines the priority of each interrupt, and forwards the

interrupt with the highest priority to the interface, for priority

masking and preemption handling.

Generic Interrupt Controller Port1 (GICPORT1)

The GICPORT1 CPU interface block performs priority masking

and preemption handling for a connected processor in the sys-

tem. GICPORT1 supports 8 software generated interrupts

(SGIs) and 254 shared peripheral interrupts (SPIs).

L2 Cache Controller, PL310 (ADSP-SC58x Only)

The L2 cache controller, PL310 (see Figure 2), works efficiently

with the ARM Cortex-A5 processors that implement system

fabric. The cache controller directly interfaces on the data and

instruction interface. The internal pipelining of the cache con-

troller is optimized to enable the processors to operate at the

same clock frequency. The cache controller supports the

following:

• Two read/write 64-bit slave ports, one connected to the

ARM Cortex-A5 instruction and data interfaces, and one

connecting the ARM Cortex-A5 and SHARC+ cores for

data coherency.

• Two read/write 64-bit master ports for interfacing with the

system fabric.

SHARC PROCESSOR

Figure 3 shows the SHARC processor integrates a SHARC+

SIMD core, L1 memory crossbar, I/D cache controller, L1 mem-

ory blocks, and the master/slave ports. Figure 4 shows the

SHARC+ SIMD core block diagram.

The SHARC processor supports a modified Harvard architec-

ture in combination with a hierarchical memory structure. L1

memories typically operate at the full processor speed with little

or no latency.

Figure 3. SHARC Processor Block Diagram

RAM

I-CACHE

RAM

P-CACHE

RAM

P-CACHE

RAM

D-CACHE

RAM

P-CACHE

RAM

P-CACHE

RAM

D-CACHE

RAM

P-CACHE

RAM

P-CACHEB0

RAM

B3 (64)

B2 (64)

B1 (64)

B0 (64)

IO (32)

INTERNAL MEMORY INTERFACE (IMIF)

I/D CACHE CONTROL

SHARC+

SIMD CORE

DM (64)

PM (64)

SLAVE

PORT 1

SLAVE

PORT 2

IO (32)

CORE

MMR

DM (64)

PM (64)

PS (64/48)

(32)

MASTER

PORT INSTRUCTION

MASTER

PORT DATA

IO (32)

CMD (64)

CMI (64)

SYSTEM FABRIC

SYSCLK

DOMAIN

INTERRUPT

SEC

SIMD Processor

CCLK DOMAIN

Rev. A | Page 8 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

L1 Memory

Figure 5 shows the ADSP-SC58x/ADSP-2158x memory map.

Each SHARC+ core has a tightly coupled L1 SRAM of up to

5 Mb. Each SHARC+ core can access code and data in a single

cycle from this memory space. The ARM Cortex-A5 core can

also access this memory space with multicycle accesses.

In the SHARC+ core private address space, both cores have L1

memory.

SHARC+ core memory-mapped register (CMMR) address

space is 0x 0000 0000 through 0x 0003 FFFF in normal word

(32-bit). Each block can be configured for different combina-

tions of code and data storage. Of the 5 Mb SRAM, up to

1024 Kb can be configured for data memory (DM), program

memory (PM), and instruction cache. Each memory block sup-

ports single-cycle, independent accesses by the core processor

and I/O processor. The memory architecture, in combination

with its separate on-chip buses, allows two data transfers from

the core and one from the DMA engine in a single cycle. The

SRAM of the processor can be configured as a maximum of

160k words of 32-bit data, 320k words of 16-bit data,

106.7k words of 48-bit instructions (or 40-bit data), or combi-

nations of different word sizes up to 5 Mb. All of the memory

can be accessed as 8-bit, 16-bit, 32-bit, 48-bit, or 64-bit words.

Support of a 16-bit floating-point storage format doubles the

amount of data that can be stored on chip.

Conversion between the 32-bit floating-point and 16-bit float-

ing-point formats is performed in a single instruction. While

each memory block can store combinations of code and data,

accesses are most efficient when one block stores data using the

DM bus for transfers, and the other block stores instructions

and data using the PM bus for transfers.

Using the DM and PM buses, with each bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache. The system configuration is flexible, but a typical config-

uration is 512 Kb DM, 128 Kb PM, and 128 Kb of instruction

cache, with the remaining L1 memory configured as SRAM.

Each addressable memory space outside the L1 memory can be

accessed either directly or via cache.

Figure 4. SHARC+ SIMD Core Block Diagram

11-STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

PM DATA 64

DM DATA 64

DM ADDRESS 32

DAG1

16 × 32

MRF

80-BIT

ALU

MULTIPLIER SHIFTER

PEx

DATA

16 × 40-BIT

DMD/PMD 64

ASTATx

STYKx

ASTATy

STYKy

PEy

DATA

16 × 40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

DAG2

16 × 32

ALU MULTIPLIER

SHIFTER

DATA

SWAP

SYSTEM

I/F

USTAT

PM ADDRESS 24

PM DATA 48

DEBUG

TRACE FLAGS CEC BTB

CONFLICT

CACHE

IMIF

SIMD Core

Rev. A | Page 9 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

The memory map in Table 4 gives the L1 memory address space

and shows multiple L1 memory blocks offering a configurable

mix of SRAM and cache.

L1 Master and Slave Ports

Each SHARC+ core has two master and two slave ports to and

from the system fabric. One master port fetches instructions.

The second master port drives data to the system world. Both

slave ports allow conflict free core/direct memory access (DMA)

streams to the individual memory blocks. For slave port

addresses, refer to the L1 memory address map in Table 4.

L1 On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks, assuming no

block conflicts. The total bandwidth is realized using both the

DMD and PMD buses.

Instruction and Data Cache

The ADSP-SC58x/ADSP-2158x processors also include a

traditional instruction cache (I-cache) and two data caches

(D-cache) (PM and DM caches). These caches support one

instruction access and two data accesses over the DM and PM

buses, per CCLK cycle. The cache controllers automatically

manage the configured L1 memory. The system can configure

part of the L1 memory for automatic management by the cache

controllers. The sizes of these caches are independently configu-

rable from 0 kB to a maximum of 128 kB each. The memory not

managed by the cache controllers is directly addressable by the

processors. The controllers ensure the data coherence between

the two data caches. The caches provide user-controllable fea-

tures such as full and partial locking, range-bound invalidation,

and flushing.

System Event Controller (SEC) Input

The output of the system event controller (SEC) controller is

forwarded to the core event controller (CEC) to respond

directly to all unmasked system-based interrupts. The SEC also

supports nesting including various SEC interrupt channel arbi-

tration options. For all SEC channels, the processor

automatically stacks the arithmetic status (ASTATx and

ASTATy) registers and mode (MODE1) register in parallel with

the interrupt servicing.

Core Memory-Mapped Registers (CMMR)

The core memory-mapped registers control the L1 instruction

and data cache, BTB, L2 cache, parity error, system control,

debug, and monitor functions.

SHARC+ CORE ARCHITECTURE

The ADSP-SC58x/ADSP-2158x processors are code compatible

at the assembly level with the ADSP-2148x, ADSP-2147x,

ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x,

ADSP-2116x, and with the first-generation ADSP-2106x

SHARC processors.

The ADSP-SC58x/ADSP-2158x processors share architectural

features with the ADSP-2126x, ADSP-2136x, ADSP-2137x,

ADSP-214xx, and ADSP-2116x SIMD SHARC processors,

shown in Figure 4 and detailed in the following sections.

SIMD Computational Engine

The SHARC+ core contains two computational processing ele-

ments that operate as a single-instruction, multiple data (SIMD)

engine.

Figure 5. ADSP-SC58x/ADSP-2158x Memory Map

0x FFFF FFFF

0x C000 0000

0x 8000 0000

0x 6000 0000

0x 5000 0000

0x 4C00 0000

0x 4800 0000

0x 4400 0000

0x 4000 0000

0x 3000 0000

0x 28F9 FFFF

0x 28A4 0000

0x 2879 FFFF

0x 2824 0000

0x 202B FFFF

0x 201B FFFF

0x 2028 0000

0x 2020 7FFF

0x 2020 0000

0x 2018 0000

0x 2010 7FFF

0x 2010 0000

0x 200B FFFF

0x 2008 0000

0x 2000 7FFF

DMC1 (1GB)

DMC0 (1GB)

SPI2 FLASH (512MB)

PCIe (256MB)

SMC BANK 3 (64MB)

SMC BANK 2 (64MB)

SMC BANK 1 (64MB)

SMC BANK 0 (64MB)

SYSTEM MMR

RESERVED

SHARC2 L1 MULTI-MEMORY SPACE

RESERVED

SHARC1 L1 MULTI-MEMORY SPACE

RESERVED

L2 ROM 2 (2Mb)

RESERVED

L2 BOOT ROM 2 (0.25Mb)

(SHARC Cores)

RESERVED

L2 ROM 1 (2Mb)

RESERVED

L2 SRAM (2Mb)

RESERVED

L2 BOOT ROM 0 (0.25Mb)

(ARM CORE 0)

L2 BOOT ROM 1 (0.25Mb)

(SHARC Cores)

0x 2000 0000

0x 0039 FFFF

0x 0038 0000

0x 0031 FFFF

0x 0030 0000

0x 002E FFFF

0x 002C 0000

0x 0026 FFFF

0x 0024 0000

0x 0000 0000

RESERVED

L1 BLOCK 3 SRAM (1Mb)

RESERVED

L1 BLOCK 2 SRAM (1Mb)

L1 BLOCK 1 SRAM (1.5Mb)

L1 BLOCK 0 SRAM (1.5Mb)

RESERVED/CORE MMRs/

OTHER MEMORY ALIASES

RESERVED

ARM L2 CONFIG REGS (4KB)

RESERVED

ARM BOOT (32KB)

0x 2000 0000

0x 1000 1000

0x 1000 0000

0x 0000 7FFF

0x 0000 0000

ARM

ADDRESS SPACE

UNIFIED

BYTE ADDRESS

SPACE

SHARC PRIVATE

ADDRESS SPACE

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The processing elements are referred to as PEx and PEy data

registers and each contain an arithmetic logic unit (ALU), mul-

tiplier, shifter, and register file. PEx is always active and PEy is

enabled by setting the PEYEN mode bit in the mode control

Single instruction multiple data (SIMD) mode allows the pro-

cessors to execute the same instruction in both processing

elements, but each processing element operates on different

data. This architecture efficiently executes math intensive DSP

algorithms. In addition to all the features of previous generation

SHARC cores, the SHARC+ core also provides a new and sim-

pler way to execute an instruction only on the PEy data register.

SIMD mode also affects the way data transfers between memory

and processing elements because to sustain computational

operation in the processing elements requires twice the data

bandwidth. Therefore, entering SIMD mode doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

transfer with each memory or register file access.

Independent, Parallel Computation Units

Within each processing element is a set of pipelined computa-

tional units. The computational units consist of a multiplier,

arithmetic/logic unit (ALU), and shifter. These units are

arranged in parallel, maximizing computational throughput.

These computational units support IEEE 32-bit single-precision

floating-point, 40-bit extended-precision floating-point, IEEE

64-bit double-precision floating-point, and 32-bit fixed-point

data formats.

A multifunction instruction set supports parallel execution of

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments per core.

All processing operations take one cycle to complete. For all

floating-point operations, the processor takes two cycles to

complete in case of data dependency. Double-precision float-

ing-point data take two to six cycles to complete. The processor

stalls for the appropriate number of cycles for an interlocked

pipeline plus data dependency check.

Core Timer

Each SHARC+ processor core also has a timer. This extra timer

is clocked by the internal processor clock and is typically used as

a system tick clock for generating periodic operating system

interrupts.

Data Register File

Each processing element contains a general-purpose data regis-

ter file. The register files transfer data between the computation

units and the data buses, and store intermediate results. These

10-port, 32-register register files (16 primary, 16 secondary),

combined with the enhanced Harvard architecture of the pro-

cessor, allow unconstrained data flow between computation

units and internal memory. The registers in the PEx data regis-

ter file are referred to as R0–R15 and in the PEy data register file

as S0–S15.

Context Switch

Many of the registers of the processor have secondary registers

that can activate during interrupt servicing for a fast context

switch. The data, DAG, and multiplier result registers have sec-

ondary registers. The primary registers are active at reset, while

control bits in MODE1 activate the secondary registers.

Universal Registers (USTAT)

General-purpose tasks use the universal registers. The four

USTAT registers allow easy bit manipulations (set, clear, toggle,

test, XOR) for all control and status peripheral registers.

The data bus exchange register (PX) permits data to pass

between the 64-bit PM data bus and the 64-bit DM data bus or

between the 40-bit register file and the PM or DM data bus.

These registers contain hardware to handle the data width

difference.

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

For indirect addressing and implementing circular data buffers

in hardware, the ADSP-SC58x/ADSP-2158x processor uses the

two data address generators (DAGs). Circular buffers allow effi-

cient programming of delay lines and other data structures

required in digital signal processing, and are commonly used in

digital filters and Fourier transforms. The two DAGs of the pro-

cessors contain sufficient registers to allow the creation of up to

32 circular buffers (16 primary register sets and 16 secondary

sets). The DAGs automatically handle address pointer wrap-

around, reduce overhead, increase performance, and simplify

implementation. Circular buffers can start and end at any mem-

ory location.

Flexible Instruction Set Architecture (ISA)

The ISA, a 48-bit instruction word, accommodates various par-

allel operations for concise programming. For example, the

processors can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction. Additionally, the double-precision floating-point

instruction set is an addition to the SHARC+ core.

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions from

previous SHARC processors, the SHARC+ core processors sup-

port 16-bit and 32-bit opcodes for many instructions, formerly

48-bit in the ISA. This feature, called variable instruction set

architecture (VISA), drops redundant or unused bits within the

48-bit instruction to create more efficient and compact code.

The program sequencer supports fetching these 16-bit and 32-

bit instructions from both internal and external memories.

VISA is not an operating mode; it is only address dependent

(refer to memory map ISA/VISA address spaces in Table 7).

Furthermore, it allows jumps between ISA and VISA instruc-

tion fetches.

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Single-Cycle Fetch of Instructional Four Operands

The ADSP-SC58x/ADSP-2158x processors feature an enhanced

Harvard architecture in which the DM bus transfers data and

PM bus transfers both instructions and data.

With the separate program memory bus, data memory buses,

and on-chip instruction conflict-cache, the processor can simul-

taneously fetch four operands (two over each data bus) and one

instruction from the conflict cache, in a single cycle.

Core Event Controller (CEC)

The SHARC+ core generates various core interrupts (including

arithmetic and circular buffer instruction flow exceptions) and

SEC events (debug/monitor and software). The core only

responds to unmasked interrupts (enabled in the IMASK

Instruction Conflict-Cache

The processors include a 32-entry instruction cache that enables

three-bus operation for fetching an instruction and four data

values. The cache is selective—only the instructions that require

fetches conflict with the PM bus data accesses cache. This cache

allows full speed execution of core, looped operations, such as

digital filter multiply accumulates, and fast Fourier transforms

(FFT) butterfly processing. The conflict cache serves for on-chip

bus conflicts only.

Branch Target Buffer/Branch Predictor

Implementation of a hardware-based branch predictor (BP) and

branch target buffer (BTB) reduce branch delay. The program

sequencer supports efficient branching using the BTB for condi-

tional and unconditional instructions.

Addressing Spaces

In addition to traditionally supported long word, normal word,

extended precision word and short word addressing aliases, the

processors support byte addressing for the data and instruction

accesses. The enhanced ISA/VISA provides new instructions for

accessing all sizes of data from byte space as well as converting

word addresses to byte and byte to word addresses.

Additional Features

The enhanced ISA/VISA of the ADSP-SC58x/ADSP-2158x pro-

cessors also provides a memory barrier instruction for data

synchronization, exclusive data access support for multicore

data sharing, and exclusive data access to enable multiprocessor

programming. To enhance the reliability of the application, L1

data RAMs support parity error detection logic for every byte.

Additionally, the processors detect illegal opcodes. Core inter-

rupts flag both errors. Master ports of the core also detect for

failed external accesses.

SYSTEM INFRASTRUCTURE

The following sections describe the system infrastructure of the

ADSP-SC58x/ADSP-2158x processors.

System L2 Memory

A system L2 SRAM memory of 2 Mb (256 kB) and two ROM

memories, each 2 Mb (256 kB), are available to both SHARC+

cores, the ARM Cortex-A5 core, and the system DMA channels

(see Table 5). All L2 SRAM/ROM blocks are subdivided into

eight banks to support concurrent access to the L2 memory

ports. Memory accesses to the L2 memory space are multicycle

accesses by both the ARM Cortex-A5 and SHARC+ cores.

The memory space is used for various cases including

• ARM Cortex-A5 to SHARC+ core data sharing and inter-

core communications

• Accelerator and peripheral sources and destination mem-

ory to avoid accessing data in the external memory

• A location for DMA descriptors

• Storage for additional data for either the ARM Cortex-A5

or SHARC+ cores to avoid external memory latencies and

reduce external memory bandwidth

• Storage for incoming Ethernet traffic to improve

performance

• Storage for data coefficient tables cached by the

SHARC+ core

See the System Memory Protection Unit (SMPU) section for

options in limiting access by specific cores and DMA masters.

The ARM Cortex-A5 core has an L1 instruction and data cache,

each of which is 32 kB in size. The core also has an L2 cache

controller of 256 kB. When enabling the caches, accesses to all

other memory spaces (internal and external) go through the

cache.

SHARC+ Core L1 Memory in Multiprocessor Space

The ARM Cortex-A5 core can access the L1 memory of the

SHARC+ core. See Table 6 for the L1 memory address in multi-

processor space. The SHARC+ core can access the L1 memory

of the other SHARC+ core in the multiprocessor space.

One Time Programmable Memory (OTP)

The processors feature 7 Kb of one time programmable (OTP)

memory which is memory-map accessible. This memory stores

a unique chip identification and supports secure boot and

secure operation.

I/O Memory Space

The static memory controller (SMC) is programmed to control

up to two blocks of external memories or memory-mapped

devices, with flexible timing parameters. Each block occupies an

8 Kb segment regardless of the size of the device used. Mapped

I/Os also include PCIe data and SPI2 memory address space

(see Table 7).

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SYSTEM MEMORY MAP

Table 4. L1 Block 0, Block 1, Block 2, and Block 3 SHARC+ Addressing Memory Map (Private Address Space)

Memory Long Word (64 Bits)

Extended Precision/

ISA Code (48 Bits) Normal Word (32 Bits)

Short Word/

VISA Code (16 Bits) Byte Access (8 Bits)

L1 Block 0 SRAM

(1.5 Mb)

0x00048000–

0x0004DFFF

0x00090000–

0x00097FFF

0x00090000–

0x0009BFFF

0x00120000–

0x00137FFF

0x00240000–

0x0026FFFF

L1 Block 1 SRAM

(1.5 Mb)

0x00058000–

0x0005DFFF

0x000B0000–

0x000B7FFF

0x000B0000–

0x000BBFFF

0x00160000–

0x00177FFF

0x002C0000–

0x002EFFFF

L1 Block 2 SRAM

(1 Mb)

0x00060000–

0x00063FFF

0x000C0000–

0x000C5554

0x000C0000–

0x000C7FFF

0x00180000–

0x0018FFFF

0x00300000–

0x0031FFFF

L1 Block 3 SRAM

(1 Mb)

0x00070000–

0x00073FFF

0x000E0000–

0x000E5554

0x000E0000–

0x000E7FFF

0x001C0000–

0x001CFFFF

0x00380000–

0x0039FFFF

Table 5. L2 Memory Addressing Map

Memory

All L2 RAM/ROM blocks are subdivided into eight banks.

Byte Address Space

ARM Cortex-A5 – Data Access

and Instruction Fetch

SHARC+ – Data Access

Normal Word Address

Space for Data Access

SHARC+

Instruction Fetch VISA

Address Space SHARC+

Instruction Fetch ISA

Address Space SHARC+

L2 Boot ROM0

For ADSP-SC58x products, the L2 Boot ROM0 byte address space is 0x 0000 0000–0x 0000 7FFF.

ARM: 0x00000000–0x00007FFF

0x08000000–0x08001FFF 0x00B80000–0x00B83FFF 0x00580000–0x00581555SHARC+/DMA: 0x20000000–0x20007FFF

L2 RAM (2 Mb) 0x20080000–0x200BFFFF 0x08020000–0x0802FFFF 0x00BA0000–0x00BBFFFF 0x005A0000–0x005AAAAF

L2 Boot ROM1 0x20100000–0x20107FFF 0x08040000–0x08041FFF 0x00B00000–0x00B03FFF 0x00500000–0x00501555

L2 ROM1 0x20180000–0x201BFFFF 0x08060000–0x0806FFFF 0x00B20000–0x00B3FFFF 0x00520000–0x0052AAAF

L2 Boot ROM2

L2 Boot ROM address for ADSP-2158x products.

0x20200000–0x20207FFF 0x08080000–0x08081FFF 0x00B40000–0x00B43FFF 0x00540000–0x00541555

L2 ROM2 0x20280000–0x202BFFFF 0x080A0000–0x080AFFFF 0x00B60000–0x00B7FFFF 0x00560000–0x0056AAAF

Table 6. SHARC+ L1 Memory in Multiprocessor Space

Memory

Block

Byte Address Space

for ARM Cortex-A5 and SHARC+

Normal Word Address Space

for SHARC+

L1 memory of SHARC1 in

multiprocessor space

Address via Slave1 Port Block 0 0x28240000–0x2826FFFF 0x0A090000–0xA09BFFF

Block 1 0x282C0000–0x282EFFFF 0x0A0B0000–0xA0BBFFF

Block 2 0x28300000–0x2831FFFF 0x0A0C0000–0x0A0C7FFF

Block 3 0x28380000–0x2839FFFF 0x0A0E0000–0x0A0E7FFF

Address via Slave2 Port Block 0 0x28640000–0x2866FFFF 0x0A190000–0x0A19BFFF

Block 1 0x286C0000–0x286EFFFF 0x0A1B0000–0x0A1BBFFF

Block 2 0x28700000–0x2871FFFF 0x0A1C0000–0x0A1C7FFF

Block 3 0x28780000–0x2879FFFF 0x0A1E0000–0x0A1E7FFF

L1 memory of SHARC2 in

multiprocessor space

Address via Slave1 Port Block 0 0x28A40000–0x28A6FFFF 0x0A290000–0x0A29BFFF

Block 1 0x28AC0000–0x28AEFFFF 0x0A2B0000–0x0A2BBFFF

Block 2 0x28B00000–0x28B1FFFF 0x0A2C0000–0x0A2C7FFF

Block 3 0x28B80000–0x28B9FFFF 0x0A2E0000–0x0A2E7FFF

Address via Slave2 Port Block 0 0x28E40000–0x28E6FFFF 0x0A390000–0x0A39BFFF

Block 1 0x28EC0000–0x28EEFFFF 0x0A3B0000–0x0A3BBFFF

Block 2 0x28F00000–0x28F1FFFF 0x0A3C0000–0x0A3C7FFF

Block 3 0x28F80000–0x28F9FFFF 0x0A3E0000–0x0A3E7FFF

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System Crossbars (SCBs)

The system crossbars (SCBs) are the fundamental building

blocks of a switch-fabric style for on-chip system bus intercon-

nection. The SCBs connect system bus masters to system bus

slaves, providing concurrent data transfer between multiple bus

masters and multiple bus slaves. A hierarchical model—built

from multiple SCBs—provides a power and area efficient sys-

tem interconnection.

The SCBs provide the following features:

• Highly efficient, pipelined bus transfer protocol for sus-

tained throughput

• Full-duplex bus operation for flexibility and reduced

latency

• Concurrent bus transfer support to allow multiple bus

masters to access bus slaves simultaneously

• Protection model (privileged/secure) support for selective

bus interconnect protection

Direct Memory Access (DMA)

The processors use direct memory access (DMA) to transfer

data within memory spaces or between a memory space and a

peripheral. The processors can specify data transfer operations

and return to normal processing while the fully integrated DMA

controller carries out the data transfers independent of proces-

sor activity.

DMA transfers can occur between memory and a peripheral or

between one memory and another memory. Each memory to

memory DMA stream uses two channels: one channel is the

source channel and the second is the destination channel.

All DMA channels can transport data to and from all on-chip

and off-chip memories. Programs can use two types of DMA

transfers: descriptor-based or register-based.

control registers directly to initiate a DMA transfer. On comple-

tion, the DMA control registers automatically update with

original setup values for continuous transfer. Descriptor-based

DMA transfers require a set of parameters stored within mem-

ory to initiate a DMA sequence. Descriptor-based DMA

transfers allow multiple DMA sequences to be chained together.

Program a DMA channel to set up and start another DMA

transfer automatically after the current sequence completes.

The DMA engine supports the following DMA operations:

• A single linear buffer that stops on completion

• A linear buffer with negative, positive, or zero stride length

• A circular autorefreshing buffer that interrupts when each

buffer becomes full

• A similar circular buffer that interrupts on fractional buf-

fers, such as at the halfway point

• The 1D DMA uses a set of identical ping pong buffers

defined by a linked ring of two-word descriptor sets, each

containing a link pointer and an address

• The 1D DMA uses a linked list of four-word descriptor sets

containing a link pointer, an address, a length, and a

configuration

• The 2D DMA uses an array of one-word descriptor sets,

specifying only the base DMA address

• The 2D DMA uses a linked list of multiword descriptor

sets, specifying all configurable parameters

Table 7. Memory Map of Mapped I/Os

Byte Address Space

ARM Cortex-A5 – Data Access

and Instruction Fetch

SHARC+ – Data Access

Normal Word Address

Space for Data Access SHARC+

SHARC+ Core Instruction Fetch

VISA Space ISA Space

SMC Bank 0 (64 MB) 0x40000000–0x43FFFFFF 0x01000000–0x01FFFFFF 0x00F00000–0x00F3FFFF 0x00700000–0x0073FFFF

SMC Bank 1 (64 MB) 0x44000000–0x47FFFFFF Not applicable Not applicable Not applicable

SMC Bank 2 (64 MB) 0x48000000–0x4BFFFFFF Not applicable Not applicable Not applicable

SMC Bank 3 (64 MB) 0x4C000000–0x4FFFFFFF Not applicable Not applicable Not applicable

PCIe Data (256 MB) 0x50000000–0x5FFFFFFF 0x02000000–0x03FFFFFF 0x00F40000–0x00F7FFFF 0x00740000–0x0077FFFF

SPI2 Memory (512 MB) 0x60000000–0x7FFFFFFF 0x04000000–0x07FFFFFF 0x00F80000–0x00FFFFFF 0x00780000–0x007FFFFF

Table 8. DMC Memory Map

Byte Address Space

ARM Cortex-A5 – Data Access and

Instruction Fetch

SHARC+ – Data Access

Normal Word Address

Space for Data Access SHARC+

SHARC+ Core Instruction Fetch

VISA Space ISA Space

DMC0 (1 GB) 0x80000000–0xBFFFFFFF 0x10000000–0x17FFFFFF 0x00800000–0x00AFFFFF 0x00400000–0x004FFFFF

DMC1 (1 GB) 0xC0000000–0xFFFFFFFF 0x18000000–0x1FFFFFFF 0x00C00000–0x00EFFFFF 0x00600000–0x006FFFFF

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Memory Direct Memory Access (MDMA)

The processor supports various MDMA operations, including,

• Standard bandwidth MDMA channels with CRC protec-

tion (32-bit bus width, runs on SCLK0)

• Enhanced bandwidth MDMA channel (32-bit bus width,

runs on SYSCLK)

• Maximum bandwidth MDMA channels (64-bit bus width,

run on SYCLK, one channel can be assigned to the FFT

accelerator)

Extended Memory DMA

Extended memory DMA supports various operating modes

such as delay line (which allows processor reads and writes to

external delay line buffers and to the external memory) with

limited core interaction and scatter/gather DMA (writes to and

from noncontiguous memory blocks).

Cyclic Redundant C ode (CRC) Protection

The cyclic redundant codes (CRC) protection modules allow

system software to calculate the signature of code, data, or both

in memory, the content of memory-mapped registers, or peri-

odic communication message objects. Dedicated hardware

circuitry compares the signature with precalculated values and

triggers appropriate fault events.

For example, every 100 ms the system software initiates the sig-

nature calculation of the entire memory contents and compares

these contents with expected, precalculated values. If a mis-

match occurs, a fault condition is generated through the

processor core or the trigger routing unit.

The CRC is a hardware module based on a CRC32 engine that

computes the CRC value of the 32-bit data-words presented to

it. The source channel of the memory to memory DMA (in

memory scan mode) provides data. The data can be optionally

forwarded to the destination channel (memory transfer mode).

The main features of the CRC peripheral are as follows:

•Memory scan mode

• Memory transfer mode

•Data verify mode

• Data fill mode

•User-programmable CRC32 polynomial

• Bit/byte mirroring option (endianness)

• Fault/error interrupt mechanisms

• 1D and 2D fill block to initialize an array with constants

• 32-bit CRC signature of a block of a memory or an MMR

block

Event Handling

The processors provide event handling that supports both nest-

ing and prioritization. Nesting allows multiple event service

routines to be active simultaneously. Prioritization ensures that

servicing a higher priority event takes precedence over servicing

a lower priority event.

The processors provide support for five different types of

events:

• An emulation event causes the processors to enter emula-

tion mode, allowing command and control of the

processors through the JTAG interface.

• A reset event resets the processors.

• An exceptions event occur synchronously to program flow

(in other words, the exception is taken before the instruc-

tion is allowed to complete). Conditions triggered on the

one side by the SHARC+ core, such as data alignment

(SIMD/long word) or compute violations (fixed or floating

point), and illegal instructions cause core exceptions. Con-

ditions triggered on the other side by the SEC, such as error

correcting codes (ECC)/parity/watchdog/system clock,

cause system exceptions.

• An interrupts event occurs asynchronously to program

flow. They are caused by input signals, timers, and other

peripherals, as well as by an explicit software instruction.

System Event Controller (SEC)

Both SHARC+ cores feature a system event controller. The SEC

features include the following:

• Comprehensive system event source management includ-

ing interrupt enable, fault enable, priority, core mapping,

and source grouping

• A distributed programming model where each system

event source control and all status fields are independent of

each other

• Determinism where all system events have the same propa-

gation delay and provide unique identification of a specific

system event source

• A slave control port that provides access to all SEC registers

for configuration, status, and interrupt/fault services

• Global locking that supports a register level protection

model to prevent writes to locked registers

• Fault management including fault action configuration,

time out, external indication, and system reset

Trigger Routing Unit (TRU)

The trigger routing unit (TRU) provides system-level sequence

control without core intervention. The TRU maps trigger

masters (generators of triggers) to trigger slaves (receivers of

triggers). Slave endpoints can be configured to respond to trig-

gers in various ways. Common applications enabled by the TRU

include,

• Automatically triggering the start of a DMA sequence after

a sequence from another DMA channel completes

• Software triggering

• Synchronization of concurrent activities

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SECURITY FEATURES

The following sections describe the security features of the

ADSP-SC58x/ADSP-2158x processors.

ARM TrustZone

The ADSP-SC58x processors provide TrustZone technology

that is integrated into the ARM Cortex-A5 processors. The

TrustZone technology enables a secure state that is extended

throughout the system fabric.

Cryptographic Hardware Accelerators

The ADSP-SC58x/ADSP-2158x processors support standards-

based hardware accelerated encryption, decryption, authentica-

tion, and true random number generation.

Support for the hardware-accelerated cryptographic ciphers

includes the following:

• AES in ECB, CBC, ICM, and CTR modes with 128-bit,

192-bit, and 256-bit keys

• DES in ECB and CBC mode with 56-bit key

• 3DES in ECB and CBC mode with 3x 56-bit key

• ARC4 in stateful, stateless mode, up to 128-bit key

Support for the hardware accelerated hash functions includes

the following:

•SHA-1

• SHA-2 with 224-bit and 256-bit digests

• HMAC transforms for SHA-1 and SHA-2

•MD5

Public key accelerator (PKA) is available to offload computation

intensive public key cryptography operations.

Both a hardware-based nondeterministic random number gen-

erator and pseudorandom number generator are available.

Secure boot is also available with 224-bit elliptic curve digital

signatures ensuring integrity and authenticity of the boot

stream. Optionally, ensuring confidentiality through AES-128

encryption is available.

Employ secure debug to allow only trusted users to access the

system with debug tools.

System Protection Unit (SPU)

The system protection unit (SPU) guards against accidental or

unwanted access to an MMR space of the peripheral by provid-

ing a write protection mechanism. The user can choose and

configure the protected peripherals as well as configure which of

the four system MMR masters (two SHARC+ cores, memory

DMA, and CoreSight debug) the peripherals are guarded

against.

The SPU is also part of the security infrastructure. Along with

providing write protection functionality, the SPU is employed

to define which resources in the system are secure or nonsecure

and to block access to secure resources from nonsecure masters.

System Memory Protection Unit (SMPU)

Synonymously, the system memory protection unit (SMPU)

provides memory protection against read and/or write transac-

tions to defined regions of memory. There are SMPU units in

the ADSP-SC58x/ADSP-2158x processors for each memory

space, except for SHARC L1 and SPI direct memory slave.

The SMPU is also part of the security infrastructure. It allows

the user to protect against arbitrary read and/or write transac-

tions and allows regions of memory to be defined as secure and

prevent nonsecure masters from accessing those memory

regions.

SAFETY FEATURES

The ADSP-SC58x/ADSP-2158x processors are designed to sup-

port functional safety applications. While the level of safety is

mainly dominated by the system concept, the following primi-

tives are provided by the processors to build a robust safety

concept.

Multiparity Bit Protected SHARC+ Core L1 Memories

In the SHARC+ core L1 memory space, whether SRAM or

cache, multiple parity bits protect each word to detect the single

event upsets that occur in all RAMs. Parity does not protect the

cache tags.

Error Correcting Codes (ECC) Protected L2 Memories

Error correcting codes (ECC) correct single event upsets. A sin-

gle error correct-double error detect (SEC-DED) code protects

the L2 memory. By default, ECC is enabled, but it can be dis-

abled on a per bank basis. Single-bit errors correct

transparently. If enabled, dual-bit errors can issue a system

event or fault. ECC protection is fully transparent to the user,

even if L2 memory is read or written by 8-bit or 16-bit entities.

Cyclic Redundant Code (CRC) Protected Memories

While parity bit and ECC protection mainly protect against ran-

dom soft errors in L1 and L2 memory cells, the cyclic redundant

code (CRC) engines can protect against systematic errors

(pointer errors) and static content (instruction code) of L1, L2,

and even L3 memories (DDR2, LPDDR). The processors feature

two CRC engines that are embedded in the memory to memory

DMA controllers.

CAUTION

This product includes security features that can be

used to protect embedded nonvolatile memory

contents and prevent execution of unauthorized

code. When security is enabled on this device

(either by the ordering party or the subsequent

receiving parties), the ability of Analog Devices to

conduct failure analysis on returned devices is

limited. Contact Analog Devices for details on the

failure analysis limitations for this device.

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CRC checksums can be calculated or compared automatically

during memory transfers, or one or multiple memory regions

can be continuously scrubbed by a single DMA work unit as per

DMA descriptor chain instructions. The CRC engine also pro-

tects data loaded during the boot process.

Signal Watchdogs

The eight general-purpose timers feature modes to monitor off-

chip signals. The watchdog period mode monitors whether

external signals toggle with a period within an expected range.

The watchdog width mode monitors whether the pulse widths

of external signals are within an expected range. Both modes

help to detect undesired toggling or lack of toggling of system

level signals.

System Event Controller (SEC)

Besides system events, the system event controller (SEC) further

supports fault management including fault action configuration

as timeout, internal indication by system interrupt, or external

indication through the SYS_FAULT pin and system reset.

PROCESSOR PERIPHERALS

The following sections describe the peripherals of the ADSP-

SC58x/ADSP-2158x processors.

Dynamic Memory Controller (DMC)

The 16-bit dynamic memory controller (DMC) interfaces to:

• LPDDR1 (JESD209A) maximum frequency 200 MHz,

DDRCLK (64 Mb to 2 Gb)

• DDR2 (JESD79-2E) maximum frequency 400 MHz,

DDRCLK (256 Mb to 4 Gb)

• DDR3 (JESD79-3E) maximum frequency 450 MHz,

DDRCLK (512 Mb to 8 Gb)

• DDR3L (1.5 V compatible only) maximum frequency

450 MHz, DDRCLK (512 Mb to 8 Gb)

See Table 8 for the DMC memory map.

Digital Audio Interface (DAI)

The processors support two mirrored digital audio interface

(DAI) units. Each DAI can connect various peripherals to any of

the DAI pins (DAI_PIN20–DAI_PIN01).

The application code makes these connections using the signal

routing unit (SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to interconnect

under software control. This functionality allows easy use of the

DAI associated peripherals for a wider variety of applications by

using a larger set of algorithms than is possible with nonconfig-

urable signal paths.

The DAI includes the peripherals described in the following sec-

tions (SPORTs, ASRC, S/PDIF, and PCG). DAI Pin Buffers 20

and 19 can change the polarity of the input signals. Most signals

of the peripherals belonging to different DAIs cannot be inter-

connected, with few exceptions.

The DAI_PINx pin buffers may also be used as GPIO pins. DAI

input signals allow the triggering of interrupts on the rising

edge, the falling edge, or both edges.

See the Digital Audio Interface (DAI) chapter of the ADSP-

SC58x/ADSP-2158x SHARC+ Processor Hardware Reference

for complete information on the use of the DAIs and SRUs.

Serial Ports (SPORTs)

The processors feature eight synchronous full serial ports. These

ports provide an inexpensive interface to a wide variety of digi-

tal and mixed-signal peripheral devices. These devices include

Analog Devices AD19xx and ADAU19xx family of audio

codecs, analog-to-digital converters (ADCs) and digital-to-ana-

log converters (DACs). Two data lines, a clock, and frame sync

make up the serial ports. The data lines can be programmed to

either transmit or receive data and each data line has a dedicated

DMA channel.

An individual full SPORT module consists of two inde-

pendently configurable SPORT halves with identical

functionality. Two bidirectional data lines—primary (0) and

secondary (1)—are available per SPORT half and are configu-

rable as either transmitters or receivers. Therefore, each SPORT

half permits two unidirectional streams into or out of the same

SPORT. This bidirectional functionality provides greater

flexibility for serial communications. For full-duplex configura-

tion, one half SPORT provides two transmit signals, while the

other half SPORT provides the two receive signals. The frame

sync and clock are shared.

Serial ports operate in the following six modes:

• Standard DSP serial mode

• Multichannel time division multiplexing (TDM) mode

•I

S mode

•Packed I

S mode

• Left justified mode

• Right justified mode

Asynchronous Sample Rate Converter (ASRC)

The asynchronous sample rate converter (ASRC) contains eight

ASRC blocks. It is the same core in the AD1896 192 kHz stereo

asynchronous sample rate converter. The ASRC provides up to

140 dB signal-to-noise ratio (SNR). The ASRC block performs

synchronous or asynchronous sample rate conversion across

independent stereo channels, without using internal processor

resources. The ASRC blocks can also be configured to operate

together to convert multichannel audio data without phase mis-

matches. Finally, the ASRC can clean up audio data from jittery

clock sources such as the S/PDIF receiver.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The Sony/Philips Digital Interface Format (S/PDIF) is a stan-

dard audio data transfer format that allows the transfer of digital

audio signals from one device to another without converting

them to an analog signal. There are two S/PDIF transmit/receive

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blocks on the processor. The digital audio interface carries three

types of information: audio data, nonaudio data (compressed

data), and timing information.

The S/PDIF interface supports one stereo channel or com-

pressed audio streams. The S/PDIF transmitter and receiver are

AES3 compliant and support the sample rate from 24 KHz to

192 KHz. The S/PDIF receiver supports professional jitter

standards.

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the

receiver/transmitter can be formatted as left justified, I

S, or

right justified with word widths of 16, 18, 20, or 24 bits. The

serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from various sources, such as the

SPORTs, external pins, and the precision clock generators

(PCGs), and are controlled by the SRU control registers.

Precision Clock Generators (PCG)

The precision clock generators (PCG) consist of four units:

units A/B located in the DAI0 block, and units C/D located in

the DAI1 block. The PCG can generate a pair of signals (clock

and frame sync) derived from a clock input signal (CLKIN1-0,

SCLK0, or DAI pin buffer). Each unit can also access the oppo-

site DAI unit. All units are identical in functionality and operate

independently of each other. The two signals generated by each

unit are normally used as a serial bit clock/frame sync pair.

Enhanced Parallel Peripheral Interface (EPPI)

The processors provide an enhanced parallel peripheral inter-

face (EPPI) that supports data widths up to 24 bits. The EPPI

supports direct connection to TFT LCD panels, parallel ADCs

and DACs, video encoders and decoders, image sensor mod-

ules, and other general-purpose peripherals.

The features supported in the EPPI module include the

following:

• Programmable data length of 8 bits, 10 bits, 12 bits, 14 bits,

16 bits, 18 bits, and 24 bits per clock.

• Various framed, nonframed, and general-purpose operat-

ing modes. Frame syncs can be generated internally or can

be supplied by an external device.

• ITU-656 status word error detection and correction for

ITU-656 receive modes and ITU-656 preamble and status

word decoding.

• Optional packing and unpacking of data to/from 32 bits

from/to 8 bits, 16 bits, and 24 bits. If packing/unpacking is

enabled, configure endianness to change the order of pack-

ing/unpacking of the bytes/words.

• RGB888 can be converted to RGB666 or RGB565 for trans-

mit modes.

• Various deinterleaving/interleaving modes for receiv-

ing/transmitting 4:2:2 YCrCb data.

• Configurable LCD data enable output available on Frame

Sync 3.

Universal Asynchronous Receiver/Transmitter

(UART) Ports

The processors provide three full-duplex universal asynchro-

nous receiver/transmitter (UART) ports, fully compatible with

PC standard UARTs. Each UART port provides a simplified

UART interface to other peripherals or hosts, supporting full-

duplex, DMA supported, asynchronous transfers of serial data.

A UART port includes support for five to eight data bits as well

as no parity, even parity, or odd parity.

Optionally, an additional address bit can be transferred to inter-

rupt only addressed nodes in multidrop bus (MDB) systems. A

frame is terminated by a configurable number of stop bits.

The UART ports support automatic hardware flow control

through the clear to send (CTS) input and request to send (RTS)

output with programmable assertion first in, first out (FIFO)

levels.

To help support the Local Interconnect Network (LIN) proto-

cols, a special command causes the transmitter to queue a break

command of programmable bit length into the transmit buffer.

Similarly, the number of stop bits can be extended by a pro-

grammable interframe space.

Serial Peripheral Interface (SPI) Ports

The processors have three industry-standard SPI-compatible

ports that allow the processors to communicate with multiple

SPI-compatible devices.

The baseline SPI peripheral is a synchronous, four-wire inter-

face consisting of two data pins, one device select pin, and a

gated clock pin. The two data pins allow full-duplex operation

to other SPI-compatible devices. An extra two (optional) data

pins are provided to support quad SPI operation. Enhanced

modes of operation, such as flow control, fast mode, and dual-

I/O mode (DIOM), are also supported. A direct memory access

(DMA) mode allows for transferring several words with mini-

mal central processing unit (CPU) interaction.

With a range of configurable options, the SPI ports provide a

glueless hardware interface with other SPI-compatible devices

in master mode, slave mode, and multimaster environments.

The SPI peripheral includes programmable baud rates, clock

phase, and clock polarity. The peripheral can operate in a multi-

master environment by interfacing with several other devices,

acting as either a master device or a slave device. In a multimas-

ter environment, the SPI peripheral uses open-drain outputs to

avoid data bus contention. The flow control features enable slow

slave devices to interface with fast master devices by providing

an SPI ready pin (SPI_RDY) which flexibly controls the

transfers.

The baud rate and clock phase/polarities of the SPI port are pro-

grammable. The port has integrated DMA channels for both

transmit and receive data streams.

Link Ports (LP)

Two 8-bit wide link ports (LP) can connect to the link ports of

other DSPs or peripherals. LP are bidirectional ports that have

eight data lines, an acknowledge line, and a clock line.

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ADC Control Module (ACM) Interface

The ADC control module (ACM) provides an interface that

synchronizes the controls between the processors and an ADC.

The analog-to-digital conversions are initiated by the proces-

sors, based on external or internal events.

The ACM allows for flexible scheduling of sampling instants

and provides precise sampling signals to the ADC.

The ACM synchronizes the ADC conversion process, generat-

ing the ADC controls, the ADC conversion start signal, and

other signals. The actual data acquisition from the ADC is done

by an internal DAI routing of the ACM with the SPORT0 block.

The processors interface directly to many ADCs without any

glue logic required.

3-Phase Pulse Width Modulator (PWM) Units

The pulse width modulator (PWM) module is a flexible and

programmable waveform generator. With minimal CPU inter-

vention, the PWM generates complex waveforms for motor

control, pulse coded modulation (PCM), DAC conversions,

power switching, and power conversion. The PWM module has

four PWM pairs capable of 3-phase PWM generation for source

inverters for ac induction and dc brushless motors.

Each of the three 3-phase PWM generation units features the

following:

• 16-bit center-based PWM generation unit

•Programmable PWM pulse width

• Single update mode with an option for asymmetric duty

• Programmable dead time and switching frequency

• Programmable dead time per channel

• Twos complement implementation which permits smooth

transition to full on and full off states

• Dedicated asynchronous PWM shutdown signal

Ethernet Media Access Controller (EMAC)

The processor features two ethernet media access controllers

(EMACs): 10/100 Ethernet and 10/100/1000/AVB Ethernet

with precision time protocol IEEE 1588.

The processors can directly connect to a network through

embedded fast EMAC that supports 10-BaseT (10 Mb/sec),

100-BaseT (100 Mb/sec) and 1000-BaseT (1 Gb/sec) operations.

The 10/100 EMAC peripheral on the processors is fully compli-

ant to the IEEE 802.3-2002 standard. The peripheral provides

programmable features designed to minimize supervision, bus

use, or message processing by the rest of the processor system.

Some standard features of the EMAC are as follows:

• Support and RMII/RGMII protocols for external PHYs

• Full-duplex and half-duplex modes

• Media access management (in half-duplex operation)

• Flow control

• Station management, including the generation of

MDC/MDIO frames for read/write access to PHY registers

Some advanced features of the EMAC are as follows:

• Automatic checksum computation of IP header and IP

payload fields of receive frames

• Independent 32-bit descriptor driven receive and transmit

DMA channels

• Frame status delivery to memory through DMA, including

frame completion semaphores for efficient buffer queue

management in software

• Transmit DMA support for separate descriptors for MAC

header and payload fields to eliminate buffer copy

operations

• Convenient frame alignment modes

• 47 MAC management statistics counters with selectable

clear on read behavior and programmable interrupts on

half maximum value

• Advanced power management

• Magic packet detection and wakeup frame filtering

• Support for 802.3Q tagged VLAN frames

• Programmable MDC clock rate and preamble suppression

Audio Video Bridging (AVB) Support

(10/100/1000 EMAC Only)

The 10/100/1000 EMAC supports the following audio video

(AVB) features:

• Separate channels or queues for AV data transfer in

100 Mbps and 1000 Mbps modes

• IEEE 802.1-Qav specified credit-based shaper (CBS) algo-

rithm for the additional transmit channels

• Configuring up to two additional channels (Channel 1 and

Channel 2) on the transmit and receive paths for AV traffic.

Channel 0 is available by default and carries the legacy best

effort Ethernet traffic on the transmit side.

• Separate DMA, transmit and receive FIFO for AVB latency

class

• Programmable control to route received VLAN tagged

non AV packets to channels or queues

Precision Time Protocol (PTP) IEEE 1588 Support

The IEEE 1588 standard is a precision clock synchronization

protocol for networked measurement and control systems. The

processors include hardware support for IEEE 1588 with an

integrated precision time protocol synchronization engine

(PTP_TSYNC).

This engine provides hardware assisted time stamping to

improve the accuracy of clock synchronization between PTP

nodes. The main features of the engine are as follows:

• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-

tocol standards

• Hardware assisted time stamping capable of up to 12.5 ns

resolution

• Lock adjustment

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• Automatic detection of IPv4 and IPv6 packets, as well as

PTP messages

• Multiple input clock sources (SCLK0, RGMII, RMII, RMII

clock, and external clock)

• Programmable pulse per second (PPS) output

• Auxiliary snapshot to time stamp external events

Controller Area Network (CAN)

There are two controller area network (CAN) modules. A CAN

controller implements the CAN 2.0B (active) protocol. This

protocol is an asynchronous communications protocol used in

both industrial and automotive control systems. The CAN pro-

tocol is well suited for control applications due to the capability

to communicate reliably over a network. This is because the

protocol incorporates CRC checking, message error tracking,

and fault node confinement.

The CAN controller offers the following features:

• 32 mailboxes (8 receive only, 8 transmit only, 16 configu-

rable for receive or transmit)

• Dedicated acceptance masks for each mailbox

• Additional data filtering on the first two bytes

• Support for both the standard (11-bit) and extended (29-

bit) identifier (ID) message formats

• Support for remote frames

• Active or passive network support

• Interrupts, including transmit and receive complete, error,

and global

An additional crystal is not required to supply the CAN clock

because it is derived from a system clock through a programma-

ble divider.

Timers

The processors include several timers that are described in the

following sections.

General-Purpose (GP) Timers (TIMER)

There is one general-purpose (GP) timer unit, providing eight

general-purpose programmable timers. Each timer has an exter-

nal pin that can be configured either as PWM or timer output,

as an input to clock the timer, or as a mechanism for measuring

pulse widths and periods of external events. These timers can be

synchronized to an external clock input on the TM_TMR[n]

pins, an external TM_CLK input pin, or to the internal SCLK0.

These timer units can be used in conjunction with the UARTs

and the CAN controller to measure the width of the pulses in

the data stream to provide a software autobaud detect function

for the respective serial channels.

The GP timers can generate interrupts to the processor core,

providing periodic events for synchronization to either the sys-

tem clock or to external signals. Timer events can also trigger

other peripherals via the TRU (for instance, to signal a fault).

Each timer can also be started and/or stopped by any TRU mas-

ter without core intervention.

Watchdog Timer (WDT)

Two on-chip software watchdog timers (WDT) can be used by

the ARM Cortex-A5 and/or SHARC+ cores. A software watch-

dog can improve system availability by forcing the processors to

a known state, via a general-purpose interrupt, or a fault, if the

timer expires before being reset by software.

The programmer initializes the count value of the timer, enables

the appropriate interrupt, then enables the timer. Thereafter,

the software must reload the counter before it counts down to

zero from the programmed value, protecting the system from

remaining in an unknown state where software that normally

resets the timer stops running due to an external noise condi-

tion or software error.

General-Purpose Counters (CNT)

A 32-bit counter (CNT) is provided that can operate in general-

purpose up/down count modes and can sense 2-bit quadrature

or binary codes as typically emitted by industrial drives or man-

ual thumbwheels. Count direction is either controlled by a level-

sensitive input pin or by two edge detectors.

A third counter input can provide flexible zero marker support

and can input the push button signal of thumbwheel devices. All

three CNT0 pins have a programmable debouncing circuit.

Internal signals forwarded to a GP timer enable this timer to

measure the intervals between count events. Boundary registers

enable auto-zero operation or simple system warning by inter-

rupts when programmed count values are exceeded.

PCI Express (PCIe)

A PCI express interface (PCIe) is available on some product

variants (see Table 2 and Table 3). This single, bidirectional lane

can be configured to be either a root complex (RC) or end point

(EP) system. The PCIe interface has the following features:

• Designed to be compliant with the PCI Express Base

Specification 3.0

• Support for transfers at either 2.5 Gbps (Gen 1) or 5.0 Gbps

(Gen 2) in each direction

• Support for 8b/10b encode and decode

• Lane reversal and lane polarity inversion

• Flow control of data in both the transmit and receive

directions

• Support for removal of corrupted packets for error detec-

tion and recovery

• Maximum transaction payload of 256 bytes

Housekeeping Analog-to-Digital Converter (HADC)

The housekeeping analog-to-digital converter (HADC) pro-

vides a general-purpose, multichannel successive

approximation ADC. It supports the following set of features:

• 12-bit ADC core (10-bit accuracy) with built in sample and

hold.

• Eight single-ended input channels that can be extended to

15 channels by adding an external channel multiplexer.

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• Throughput rates up to 1 MSPS.

• Single external reference with analog inputs between

0 V and 3.3 V.

• Selectable ADC clock frequency including the ability to

program a prescaler.

• Adaptable conversion type; allows single or continuous

conversion with option of autoscan.

• Auto sequencing capability with up to 15 autoconversions

in a single session. Each conversion can be programmed to

select 1 to 15 input channels.

• 16 data registers (individually addressable) to store conver-

sion values.

USB 2.0 On the Go (OTG) Dual-Role Device Controller

There are two USB modules + PHY. USB0 supports HS/FS/LS

USB 2.0 on the go (OTG) and USB1 supports HS/FS USB 2.0

only and can be programmed to be a host or device.

The USB 2.0 OTG dual-role device controller provides a low

cost connectivity solution in industrial applications, as well as

consumer mobile devices such as cell phones, digital still cam-

eras, and MP3 players. The USB 2.0 controller allows these

devices to transfer data using a point to point USB connection

without the need for a PC host. The module can operate in a tra-

ditional USB peripheral only mode as well as the host mode

presented in the OTG supplement to the USB 2.0 specification.

The USB clock is provided through a dedicated external crystal

or crystal oscillator.

The USB OTG dual-role device controller includes a PLL with

programmable multipliers to generate the necessary internal

clocking frequency for the USB.

Media Local Bus (MediaLB)

The automotive model has a MediaLB (MLB) slave interface

that allows the processors to function as a media local bus

device. It includes support for both 3-pin and 6-pin media local

bus protocols. The MLB 3-pin configuration supports speeds up

to 1024 × FS. The MLB 6-pin configuration supports speed of

4096 × FS. The MLB also supports up to 63 logical channels

with up to 468 bytes of data per MLB frame.

The MLB interface supports MOST25, MOST50, and MOST150

data rates and operates in slave mode only.

2-Wire Controller Interface (TWI)

The processors include three 2-wire interface (TWI) modules

that provide a simple exchange method of control data between

multiple devices. The TWI module is compatible with the

widely used I

C bus standard. The TWI module offers the

capabilities of simultaneous master and slave operation and

support for both 7-bit addressing and multimedia data arbitra-

tion. The TWI interface utilizes two pins for transferring clock

(TWI_SCL) and data (TWI_SDA) and supports the protocol at

speeds up to 400 kb/sec. The TWI interface pins are compatible

with 5 V logic levels.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

General-Purpose I/O (GPIO)

Each general-purpose port pin can be individually controlled by

manipulating the port control, status, and interrupt registers:

• GPIO direction control register specifies the direction of

each individual GPIO pin as input or output.

• GPIO control and status registers have a write one to mod-

ify mechanism that allows any combination of individual

GPIO pins to be modified in a single instruction, without

affecting the level of any other GPIO pins.

• GPIO interrupt mask registers allow each individual GPIO

pin to function as an interrupt to the processors. GPIO pins

defined as inputs can be configured to generate hardware

interrupts, while output pins can be triggered by software

interrupts.

• GPIO interrupt sensitivity registers specify whether indi-

vidual pins are level or edge sensitive and specify, if edge

sensitive, whether the rising edge or both the rising and

falling edges of the signal are significant.

Pin Interrupts

Every port pin on the processors can request interrupts in either

an edge sensitive or a level sensitive manner with programmable

polarity. Interrupt functionality is decoupled from GPIO opera-

tion. Six system-level interrupt channels (PINT0–PINT5) are

reserved for this purpose. Each of these interrupt channels can

manage up to 32 interrupt pins. The assignment from pin to

interrupt is not performed on a pin by pin basis. Rather, groups

of eight pins (half ports) can be flexibly assigned to interrupt

channels.

Every pin interrupt channel features a special set of 32-bit mem-

ory-mapped registers that enable half-port assignment and

interrupt management. This includes masking, identification,

and clearing of requests. These registers also enable access to the

respective pin states and use of the interrupt latches, regardless

of whether the interrupt is masked or not. Most control registers

feature multiple MMR address entries to write-one-to-set or

write-one-to-clear them individually.

Mobile Storage Interface (MSI)

The mobile storage interface (MSI) controller acts as the host

interface for multimedia cards (MMC), secure digital memory

cards (SD), and secure digital input/output cards (SDIO). The

MSI controller has the following features:

• Support for a single MMC, SD memory, and SDIO card

• Support for 1-bit and 4-bit SD modes

• Support for 1-bit, 4-bit, and 8-bit MMC modes

• Support for eMMC 4.3 embedded NAND flash devices

• An eleven-signal external interface with clock, command,

optional interrupt, and up to eight data lines

• Integrated DMA controller

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• Card interface clock generation in the clock distribution

unit (CDU)

• SDIO interrupt and read wait features

SYSTEM ACCELERATION

The following sections describe the system acceleration blocks

of the ADSP-SC58x/ADSP-2158x processors.

FFT/IFFT Accelerator

A high performance FFT/IFFT accelerator is available to

improve the overall floating-point computation power of the

ADSP-SC58x/ADSP-2158x processors.

The following features are available to improve the overall per-

formance of the FFT/IFFT accelerator:

• Support for the IEEE-754/854 single-precision floating-

point data format.

• Automatic twiddle factor generation to reduce system

bandwidth.

• Support for a vector complex multiply for windowing and

frequency domain filtering.

• Ability to pipeline the data flow. This allows the accelerator

to bring in a new data set while the current data set is pro-

cessed and the previous data set is sent out to memory. This

can provide a significant system level performance

improvement.

• Ability to output the result as the magnitude squared of the

complex samples.

• Dedicated, high speed DMA controller with 64-bit buses

that can read and write data from any memory space.

The FFT/IFFT accelerator can run concurrently with the other

accelerators on the processor.

Finite Impulse Response (FIR) Accelerator

The finite impulse response (FIR) accelerator consists of a

1024 word coefficient memory, a 1024 word deep delay line for

the data, and four MAC units. A controller manages the acceler-

ator. The FIR accelerator runs at the peripheral clock frequency.

The FIR accelerator can access all memory spaces and can run

concurrently with the other accelerators on the processor.

Infinite Impulse Response (IIR) Accelerator

The infinite impulse response (IIR) accelerator consists of a

1440 word coefficient memory for storage of biquad coeffi-

cients, a data memory for storing the intermediate data, and one

MAC unit. A controller manages the accelerator. The IIR accel-

erator runs at the peripheral clock frequency. The IIR

accelerator can access all memory spaces and run concurrently

with the other accelerators on the processor.

Harmonic Analysis Engine (HAE)

The harmonic analysis engine (HAE) block receives 8 kHz input

samples from two source signals whose frequencies are between

45 Hz and 65 Hz. The HAE processes the input samples and

produces output results. The output results consist of power

quality measurements of the fundamental and up to 12 addi-

tional harmonics.

Sinus Cardinalis (SINC) Filter

The sinus cardinalis (SINC) filter module processes four bit

streams using a pair of configurable SINC filters for each bit

stream. The purpose of the primary SINC filter of each pair is to

produce the filtered and decimated output for the pair. The out-

put can decimate any integer rate between 8 and 256 times

lower than the input rate. Greater decimation allows greater

removal of noise, and, therefore, greater effective number of bits

(ENOB).

Optional additional filtering outside the SINC module can fur-

ther increase ENOB. The primary SINC filter output is

accessible through transfer to processor memory, or to another

peripheral, via DMA.

Each of the four channels is also provided with a low latency

secondary filter with programmable positive and negative over-

range detection comparators. These limit detection events can

interrupt the core, generate a trigger, or signal a system fault.

Digital Transmission Content Protection (DTCP)

Contact Analog Devices for more information on DTCP.

SYSTEM DESIGN

The following sections provide an introduction to system design

features and power supply issues.

Clock Management

The processors provide three operating modes, each with a dif-

ferent performance and power profile. Control of clocking to

each of the processor peripherals reduces power consumption.

The processors do not support any low power operation modes.

Control of clocking to each of the processor peripherals can

reduce the power consumption.

Reset Control Unit (RCU)

Reset is the initial state of the whole processor, or the core, and

is the result of a hardware or software triggered event. In this

state, all control registers are set to default values and functional

units are idle. Exiting a full system reset starts with the core

ready to boot.

The reset control unit (RCU) controls how all the functional

units enter and exit reset. Differences in functional require-

ments and clocking constraints define how reset signals are

generated. Programs must guarantee that none of the reset

functions put the system into an undefined state or causes

resources to stall. This is particularly important when the core

resets (programs must ensure that there is no pending system

activity involving the core when it is reset).

From a system perspective, reset is defined by both the reset tar-

get and the reset source.

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The reset target is defined as the following:

• System reset—all functional units except the RCU are set to

default states.

• Hardware reset—all functional units are set to default states

without exception. History is lost.

• Core only reset— affects the core only. When in reset state,

the core is not accessed by any bus master.

The reset source is defined as the following:

• System reset—can be triggered by software (writing to the

RCU_CTL register) or by another functional unit such as

the dynamic power management (DPM) unit or any of the

SEC, TRU, or emulator inputs.

• Hardware reset—the SYS_HWRST input signal asserts

active (pulled down).

• Core only reset—affects only the core. The core is not

accessed by any bus master when in reset state.

• Trigger request (peripheral).

Real-Time Clock (RTC)

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the processor.

Connect the RTC0_CLKIN and RTC0_XTAL pins with external

components as shown in Figure 6.

The RTC peripheral has dedicated power supply pins so it can

remain powered up and clocked even when the remainder of the

processor is in a low power state. The RTC provides several

programmable interrupt options, including interrupt per

second, minute, hour, or day clock ticks; interrupt on program-

mable stopwatch countdown; or interrupt at a programmed

alarm time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60 second counter, a 60 minute counter, a

24 hour counter, and a 32,768 day counter. When the alarm

interrupt is enabled, the alarm function generates an interrupt

when the output of the timer matches the programmed value in

the alarm control register (RTC_ALARM). There are two

alarms: a time of day and a day and time of that day.

The stopwatch function counts down from a programmed

value, with 1 sec resolution. When the stopwatch interrupt is

enabled and the counter underflows, an interrupt is generated.

Clock Generation Unit (CGU)

The ADSP-SC58x/ADSP-2158x processors support two inde-

pendent PLLs. Each PLL is part of a clock generation unit

(CGU); see Figure 8. Each CGU can be either driven externally

by the same clock source or each can be driven by separate

sources. This provides flexibility in determining the internal

clocking frequencies for each clock domain.

Frequencies generated by each CGU are derived from a com-

mon multiplier with different divider values available for each

output.

The CGU generates all on-chip clocks and synchronization sig-

nals. Multiplication factors are programmed to define the

PLLCLK frequency.

Programmable values divide the PLLCLK frequency to generate

the core clock (CCLK), the system clocks, the DDR1/DDR2/

DDR3 clock (DCLK), and the output clock (OCLK). For more

information on clocking, see the ADSP-SC58x/ADSP-2158x

SHARC+ Processor Hardware Reference.

Writing to the CGU control registers does not affect the behav-

ior of the PLL immediately. Registers are first programmed with

a new value and the PLL logic executes the changes so it transi-

tions smoothly from the current conditions to the new

conditions.

System Crystal Oscillator and USB Crystal Oscillator

The processor can be clocked by an external crystal (see

Figure 7), a sine wave input, or a buffered, shaped clock derived

from an external clock oscillator. If using an external clock, it

should be a TTL-compatible signal and must not be halted,

changed, or operated below the specified frequency during nor-

mal operation. This signal is connected to the SYS_CLKINx pin

and the USB_CLKIN pin of the processor. When using an

external clock, the SYS_XTALx pin and the USB_XTAL pin

must be left unconnected. Alternatively, because the processor

includes an on-chip oscillator circuit, an external crystal can be

used.

For fundamental frequency operation, use the circuit shown in

Figure 7. A parallel resonant, fundamental frequency, micro-

processor grade crystal is connected across the SYS_CLKINx

pin and the SYS_XTALx pin. The on-chip resistance between

the SYS_CLKINx pin and the SYS_XTALx pin is in the 500 kΩ

range. Further parallel resistors are typically not recommended.

The two capacitors and the series resistor, shown in Figure 7,

fine tune phase and amplitude of the sine frequency. The capac-

itor and resistor values shown in Figure 7 are typical values

only. The capacitor values are dependent upon the load capaci-

tance recommendations of the crystal manufacturer and the

physical layout of the printed circuit board (PCB). The resistor

value depends on the drive level specified by the crystal manu-

facturer. The user must verify the customized values based on

careful investigations on multiple devices over the required

temperature range.

Figure 6. External Components for RTC

C1 C2

RTC0_CLKIN

RTC0_XTAL

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS.

Rev. A | Page 23 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

A third overtone crystal can be used for frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone by adding a tuned inductor circuit,

shown in Figure 7. A design procedure for the third overtone

operation is discussed in detail in “Using Third Overtone Crys-

tals with the ADSP-218x DSP” (EE-168). The same

recommendations can be used for the USB crystal oscillator.

Clock Distribution Unit (CDU)

The two CGUs each provide outputs which feed a clock distri-

bution unit (CDU). The clock outputs CLKO0–CLKO9 are

connected to various targets. For more information, refer to the

ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware

Reference.

Power-Up

SYS_XTALx oscillations (SYS_CLKINx) start when power is

applied to the VDD_EXT pins. The rising edge of SYS_HWRST

starts on-chip PLL locking (PLL lock counter). The deassertion

must apply only if all voltage supplies and SYS_CLKINx oscilla-

tions are valid (refer to the Power-Up Reset Timing section).

Clock Out/External Clock

The SYS_CLKOUT output pin has programmable options to

output divided-down versions of the on-chip clocks. By default,

the SYS_CLKOUT pin drives a buffered version of the

SYS_ CLKIN0 input. Refer to the ADSP-SC58x/ADSP-2158x

SHARC+ Processor Hardware Reference to change the default

mapping of clocks.

Booting

The processors have several mechanisms for automatically load-

ing internal and external memory after a reset. The boot mode is

defined by the SYS_BMODE[n] input pins. There are two cate-

gories of boot modes. In master boot mode, the processors

actively load data from serial memories. In slave boot modes,

the processors receive data from external host devices.

The boot modes are shown in Table 9. These modes are imple-

mented by the SYS_BMODE[n] bits of the reset configuration

initiated resets.

In the ADSP-SC58x processors, the ARM Cortex-A5 (Core 0)

controls the boot process, including loading all internal and

external memory. Likewise, in the ADSP-2158x processors, the

SHARC+ (Core 1) controls the boot function. The option for

secure boot is available on all models.

Thermal Monitoring Unit (TMU)

The thermal monitoring unit (TMU) provides on-chip tem-

perature measurement which is important in applications that

require substantial power consumption. The TMU is integrated

into the processor die and digital infrastructure using an MMR-

based system access to measure the die temperature variations

in real-time.

TMU features include the following:

• On-chip temperature sensing

• Programmable over temperature and under temperature

limits

• Programmable conversion rate

• Averaging feature available

Power Supplies

The processors have separate power supply connections for:

• Internal (VDD_INT)

• External (VDD_EXT)

• USB (VDD_USB)

• HADC/TMU (VDD_HADC)

• RTC (VDD_RTC)

Figure 7. External Crystal Connection

SYS_CLKINx

TO PLL

CIRCUITRY

FOR OVERTONE

OPERATION ONLY:

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. FOR

FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE

OF 18 pF MUST BE TREATED AS A MAXIMUM.

18 pF* 18 pF*

SHARC PROCESSOR

ȍ

SYS_XTALx

Nȍ

Table 9. Boot Modes

SYS_BMODE[n] Setting Boot Mode

000 No boot

001 SPI2 master

010 SPI2 slave

011 Reserved

100 Reserved

101 Reserved

110 Link0 slave

111 UART0 slave

Rev. A | Page 24 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

• DMC (VDD_DMC)

• PCIe (VDD_PCIE, VDD_PCIE_TX and VDD_PCIE_RX)

All power supplies must meet the specifications provided in the

Operating Conditions section. All external supply pins must be

connected to the same power supply.

Power Management

As shown in Table 10, the processors support four different

power domains, which maximizes flexibility while maintaining

compliance with industry standards and conventions. There are

no sequencing requirements for the various power domains, but

all domains must be powered according to the appropriate spec-

ifications (see the Specifications section for processor operating

conditions). If the feature or the peripheral is not used, refer to

Table 27.)

The power dissipated by the processors is largely a function of

the clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation.

Target Board JTAG Emulator Connector

The Analog Devices DSP tools product line of JTAG emulators

uses the IEEE 1149.1 JTAG test access port of the processors to

monitor and control the target board processor during emula-

tion. The Analog Devices DSP tools product line of JTAG

emulators provides emulation at full processor speed, allowing

inspection and modification of memory, registers, and proces-

sor stacks. The processor JTAG interface ensures the emulator

does not affect target system loading or timing.

For information on JTAG emulator operation, see the appropri-

ate emulator hardware user’s guide at SHARC Processors

Software and Tools.

SYSTEM DEBUG

The processors include various features that allow easy system

debug. These are described in the following sections.

System Watchpoint Unit (SWU)

The system watchpoint unit (SWU) is a single module that con-

nects to a single system bus and provides transaction

monitoring. One SWU is attached to the bus going to each

system slave. The SWU provides ports for all system bus address

channel signals. Each SWU contains four match groups of

registers with associated hardware. These four SWU match

groups operate independently but share common event (for

example, interrupt and trigger) outputs.

Debug Access Port (DAP)

Debug access port (DAP) provides IEEE 1149.1 JTAG interface

support through the JTAG debug. The DAP provides an

optional instrumentation trace for both the core and system. It

provides a trace stream that conforms to MIPI System Trace

Protocol version 2 (STPv2).

DEVELOPMENT TOOLS

Analog Devices supports its processors with a complete line of

software and hardware development tools, including an inte-

grated development environment (CrossCore

Embedded

Studio), evaluation products, emulators, and a variety of soft-

ware add-ins.

Integrated Development Environments (IDEs)

For C/C++ software writing and editing, code generation, and

debug support, Analog Devices offers the CrossCore Embedded

Studio integrated development environment (IDE).

CrossCore Embedded Studio is based on the Eclipse framework.

Supporting most Analog Devices processor families, it is the

IDE of choice for processors, including multicore devices.

CrossCore Embedded Studio seamlessly integrates available

software add-ins to support real-time operating systems, file

systems, TCP/IP stacks, USB stacks, algorithmic software mod-

ules, and evaluation hardware board support packages. For

more information, visit www.analog.com/cces.

EZ-KIT Lite Evaluation Board

For processor evaluation, Analog Devices provides a wide range

of EZ-KIT Lite

evaluation boards. Including the processor and

key peripherals, the evaluation board also supports on-chip

emulation capabilities and other evaluation and development

features. Various EZ-Extenders

are also available, which are

daughter cards that deliver additional specialized functionality,

including audio and video processing. For more information

visit www.analog.com.

EZ-KIT Lite Evaluation Kits

For a cost-effective way to learn more about developing with

Analog Devices processors, Analog Devices offer a range of EZ-

KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT

Lite evaluation board, directions for downloading an evaluation

version of the available IDE(s), a USB cable, and a power supply.

The USB controller on the EZ-KIT Lite board connects to the

USB port of the user PC, enabling the chosen IDE evaluation

suite to emulate the on-board processor in-circuit.

Table 10. Power Domains

Power Domain V

Range

All internal logic V

DD_INT

DDR3/DDR2/LPDDR V

DD_DMC

USB V

DD_USB

HADC/TMU V

DD_HADC

RTC V

DD_RTC

PCIe_TX V

DD_PCIE_TX

PCIe_RX V

DD_PCIE_RX

PCIe V

DD_PCIE

All other I/O (includes SYS, JTAG, and

port pins)

DD_EXT

Rev. A | Page 25 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

This permits the customer to download, execute, and debug

programs for the EZ-KIT Lite system. It also supports in circuit

programming of the on-board Flash device to store user specific

boot code, enabling standalone operation. With the full version

of CrossCore Embedded Studio installed (sold separately), engi-

neers can develop software for supported EZ-KITs or any

custom system utilizing supported Analog Devices processors.

Software Add-Ins for CrossCore Embedded Studio

Analog Devices offers software add-ins which seamlessly inte-

grate with CrossCore Embedded Studio to extend the

capabilities and reduce development time. Add-ins include

board support packages for evaluation hardware, various mid-

dleware packages, and algorithmic modules. Documentation,

help, configuration dialogs, and coding examples present in

these add-ins are viewable through the CrossCore Embedded

Studio IDE once the add-in is installed.

Board Support Packages for Evaluation Hardware

Software support for the EZ-KIT Lite evaluation boards and EZ-

Extender daughter cards is provided by software add-ins called

board support packages (BSPs). The BSPs contain the required

drivers, pertinent release notes, and select example code for the

given evaluation hardware. A download link for a specific BSP is

located on the web page for the associated EZ-KIT or EZ-

Extender product.

Middleware Packages

Analog Devices offers middleware add-ins such as real-time

operating systems, file systems, USB stacks, and TCP/IP stacks.

For more information, see the following web pages:

•www.analog.com/ucos2

•www.analog.com/ucos3

•www.analog.com/ucfs

•www.analog.com/ucusbd

•www.analog.com/ucusbh

•www.analog.com/lwip

Algorithmic Modules

To speed development, Analog Devices offers add-ins that per-

form popular audio and video processing algorithms. These are

available for use with CrossCore Embedded Studio. For more

information visit www.analog.com.

Designing an Emulator-Compatible DSP Board (Target)

For embedded system test and debug, Analog Devices provides

a family of emulators. On each JTAG DSP, Analog Devices sup-

plies an IEEE 1149.1 JTAG test access port (TAP). In-circuit

emulation is facilitated by use of this JTAG interface. The

emulator accesses the internal features of the processor via the

TAP, allowing the developer to load code, set breakpoints, and

view variables, memory, and registers.

The processor must be halted to send data and commands, but

once an operation is completed by the emulator, the DSP system

is set to run at full speed with no impact on system timing. The

emulators require the target board to include a header that sup-

ports connection of the JTAG port of the DSP to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see “Analog Devices JTAG

Emulation Technical Reference” (EE-68).

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-

SC58x/ADSP-2158x architecture and functionality. For detailed

information on the core architecture and instruction set, refer to

the SHARC+ Core Programming Reference.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The application signal chains page in the Circuits from the Lab

site (www.analog.com\circuits) provides the following:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

SECURITY FEATURES DISCLAIMER

To our knowledge, the Security Features, when used in accor-

dance with the data sheet and hardware reference manual

specifications, provide a secure method of implementing code

and data safeguards. However, Analog Devices does not guaran-

tee that this technology provides absolute security.

ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS

ANY AND ALL EXPRESS AND IMPLIED WARRANTIES

THAT THE SECURITY FEATURES CANNOT BE

BREACHED, COMPROMISED, OR OTHERWISE CIRCUM-

VENTED AND IN NO EVENT SHALL ANALOG DEVICES

BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR

RELEASE OF DATA, INFORMATION, PHYSICAL PROP-

ERTY, OR INTELLECTUAL PROPERTY.

Rev. A | Page 26 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

ADSP-SC58x/ADSP-2158x DETAILED SIGNAL DESCRIPTIONS

Table 11 provides a detailed description of each pin.

Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions

Signal Name Direction Description

ACM_A[n] Output ADC Control Signals. Function varies by mode.

ACM_T[n] Input External Trigger n. Input for external trigger events.

C1_FLG[n] InOut SHARC+ Core 1 Flag Pin.

C2_FLG[n] InOut SHARC+ Core 2 Flag Pin.

CAN_RX Input Receive. Typically an external CAN transceiver RX output.

CAN_TX Output Transmit. Typically an external CAN transceiver TX input.

CNT_DG Input Count Down and Gate. Depending on the mode of operation, this input acts either as a count down

signal or a gate signal.

Count down—this input causes the GP counter to decrement.

Gate—stops the GP counter from incrementing or decrementing.

CNT_UD Input Count Up and Direction. Depending on the mode of operation, this input acts either as a count up

signal or a direction signal.

Count up—this input causes the GP counter to increment.

Direction—selects whether the GP counter is incrementing or decrementing.

CNT_ZM Input Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects the

pressing of a pushbutton.

DAI_PIN[nn] InOut Pin n. The digital applications interfaces (DAI0 and DAI1) connect various peripherals to any of the

DAI0_PINxx and DAI1_PINxx pins. Programs make these connections using the signal routing unit

(SRU). Both DAI units are symmetric. The shared DAIx__PIN03 and DAIx_PIN04 pins allow routing

between both DAI units.

DMC_A[nn] Output Address n. Address bus.

DMC_BA[n] Output Bank Address n. Defines which internal bank an activate, read, write or precharge command is

applied to on the dynamic memory. Bank Address n also defines which mode registers (MR, EMR,

EMR2, and/or EMR3) load during the load mode register command.

DMC_CAS Output Column Address Strobe. Defines the operation for external dynamic memory to perform in

conjunction with other DMC command signals. Connect to the CAS input of dynamic memory.

DMC_CK Output Clock. Outputs DCLK to external dynamic memory.

DMC_CKE Output Clock Enable. Active high clock enables. Connects to the dynamic memory’s CKE input.

DMC_CK Output Clock (Complement). Complement of DMC_CK.

DMC_CS[n] Output Chip Select n. Commands are recognized by the memory only when this signal is asserted.

DMC_DQ[nn] InOut Data n. Bidirectional data bus.

DMC_LDM Output Data Mask for Lower Byte. Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled

on both edges of the data strobe by the dynamic memory.

DMC_LDQS InOut Data Strobe for Lower Byte. DMC_DQ07:DMC_DQ00 data strobe. Output with write data. Input with

read data. Can be single-ended or differential depending on register settings.

DMC_LDQS InOut Data Strobe for Lower Byte (Complement). Complement of LDQS. Not used in single-ended mode.

DMC_ODT Output On-Die Termination. Enables dynamic memory termination resistances when driven high (assuming

the memory is properly configured).

DMC_RAS Output Row Address Strobe. Defines the operation for external dynamic memory to perform in conjunction

with other DMC command signals. Connect to the RAS input of dynamic memory.

DMC_RESET Output Reset (DDR3 Only).

DMC_RZQ InOut External Calibration Resistor Connection.

DMC_UDM Output Data Mask for Upper Byte. Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled

on both edges of the data strobe by the dynamic memory.

DMC_UDQS InOut Data Strobe for Upper Byte. DMC_DQ15:DMC_DQ08 data strobe. Output with write data. Input with

read data. Not used in single-ended mode.

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DMC_UDQS InOut Data Strobe for Upper Byte (Complement). Complement of UDQS. Not used in single-ended mode.

DMC_VREF Input Voltage Reference. Externally driven to VDD_DMC/2. Applies to DMC0_VREF and DMC1_VREF pins.

DMC_WE Output Write Enable. Defines the operation for external dynamic memory to perform in conjunction with

other DMC command signals. Connect to the WE input of dynamic memory.

ETH_CRS Input Carrier Sense/RMII Receive Data Valid. Multiplexed on alternate clock cycles.

CRS— asserted by the PHY when either the transmit or receive medium is not idle. Deasserted when

both are idle.

RXDV—asserted by the PHY when the data on RXDn is valid.

ETH_MDC Output Management Channel Clock. Clocks the MDC input of the PHY.

ETH_MDIO InOut Management Channel Serial Data. Bidirectional data bus for PHY control.

ETH_PTPAUXIN[n] Input PTP Auxiliary Trigger Input. Assert this signal to take an auxiliary snapshot of the time and store it

in the auxiliary time stamp FIFO.

ETH_PTPCLKIN[n] Input PTP Clock Input. Optional external PTP clock input.

ETH_PTPPPS[n] Output PTP Pulse Per Second Output. When the advanced time stamp feature enables, this signal is asserted

based on the PPS mode selected. Otherwise, PTPPPS is asserted every time the seconds counter is

incremented.

ETH_REFCLK Input Reference Clock. Externally supplied Ethernet clock.

ETH_RXCLK_REFCLK Input RXCLK (GigE) or REFCLK (10/100).

ETH_RXCTL_CRS Input RXCTL (GigE) or CRS (10/100).

ETH_RXD[n] Input Receive Data n. Receive data bus.

ETH_TXCLK Output Transmit Clock.

ETH_TXCTL_TXEN Output TXCTL (GigE) or TXEN (10/100).

ETH_TXD[n] Output Transmit Data n. Transmits data bus.

ETH_TXEN Output Transmit Enable. When asserted, signal indicates the data on TXDn is valid.

HADC_EOC_DOUT Output End of Conversion/Serial Data Out. Transitions high for one cycle of the HADC internal clock at the

end of every conversion. Alternatively, HADC serial data out can be seen by setting the appropriate

bit in HADC_CTL.

HADC_MUX[n] Input Controls to External Multiplexer. Allows additional input channels when connected to an external

multiplexer.

HADC_VIN[n] Input Analog Input at Channel n. Analog voltage inputs for digital conversion.

HADC_VREFN Input Ground Reference for ADC. Connect to an external voltage reference that meets data sheet

specifications.

HADC_VREFP Input External Reference for ADC. Connect to an external voltage reference that meets data sheet

specifications.

JTG_TCK Input JTAG Clock. JTAG test access port clock.

JTG_TDI Input JTAG Serial Data In. JTAG test access port data input.

JTG_TDO Output JTAG Serial Data Out. JTAG test access port data output.

JTG_TMS Input JTAG Mode Select. JTAG test access port mode select.

JTG_TRST Input JTAG Reset. JTAG test access port reset.

LP_ACK InOut Acknowledge. Provides handshaking. When the link port is configured as a receiver, ACK is an output.

When the link port is configured as a transmitter, ACK is an input.

LP_CLK InOut Clock. When the link port is configured as a receiver, CLK is an input. When the link port is configured

as a transmitter, CLK is an output.

LP_D[n] InOut Data n. Data bus. Input when receiving, output when transmitting.

MLB_CLKN Input Differential Clock (–).

MLB_CLKP Input Differential Clock (+).

MLB_DATN InOut Differential Data (–).

MLB_DATP InOut Differential Data (+).

MLB_SIGN InOut Differential Signal (–).

Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued)

Signal Name Direction Description

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MLB_SIGP InOut Differential Signal (+).

MLB_CLK Input Single-Ended Clock.

MLB_DAT InOut Single-Ended Data.

MLB_SIG InOut Single-Ended Signal.

MLB_CLKOUT Output Single-Ended Clock Out.

MSI_CD Input Card Detect. Connects to a pull-up resistor and to the card detect output of an SD socket.

MSI_CLK Output Clock. The clock signal applied to the connected device from the MSI.

MSI_CMD InOut Command. Sends commands to and receives responses from the connected device.

MSI_D[n] InOut Data n. Bidirectional data bus.

MSI_INT Input eSDIO Interrupt Input. Used only for eSDIO. Connects to an eSDIO card interrupt output. An interrupt

may be sampled even when the MSI clock to the card is switched off.

PCIE_CLKM Input CLK –.

PCIE_CLKP Input CLK +.

PCIE_REF InOut Reference Resistor. Attach a 200 Ω, 1%, 100-ppm/C precision resistor to ground on the board.

PCIE_RXM Input RX –.

PCIE_RXP Input RX +.

PCIE_TXM Output TX –.

PCIE_TXP Output TX +.

PPI_CLK InOut Clock. Input in external clock mode, output in internal clock mode.

PPI_D[nn] InOut Data n. Bidirectional data bus.

PPI_FS1 InOut Frame Sync 1 (HSYNC). Behavior depends on EPPI mode. See the EPPI chapter of the ADSP-

SC58x/ADSP-2158x SHARC+ Processor Hardware Reference for more details.

PPI_FS2 InOut Frame Sync 2 (VSYNC). Behavior depends on EPPI mode. See the EPPI chapter of the ADSP-

SC58x/ADSP-2158x SHARC+ Processor Hardware Reference for more details.

PPI_FS3 InOut Frame Sync 3 (FIELD). Behavior depends on EPPI mode. See the EPPI chapter of the ADSP-

SC58x/ADSP-2158x SHARC+ Processor Hardware Reference for more details.

PWM_AH Output Channel A High Side. High side drive signal.

PWM_AL Output Channel A Low Side. Low side drive signal.

PWM_BH Output Channel B High Side. High side drive signal.

PWM_BL Output Channel B Low Side. Low side drive signal.

PWM_CH Output Channel C High Side. High side drive signal.

PWM_CL Output Channel C Low Side. Low side drive signal.

PWM_DH Output Channel D High Side. High side drive signal.

PWM_DL Output Channel D Low Side. Low side drive signal.

PWM_SYNC Input PWMTMR Grouped. This input is for an externally generated sync signal. If the sync signal is internally

generated, no connection is necessary.

PWM_TRIP[n] Input Shutdown Input n. When asserted, the selected PWM channel outputs are shut down immediately.

P_[nn] InOut Position n. General-purpose input/output. See the GP Ports chapter of the ADSP-SC58x/ADSP-2158x

SHARC+ Processor Hardware Reference for more details.

RTC_CLKIN Input Crystal Input/External Oscillator Connection. Connect to an external clock source or crystal.

RTC_XTAL Output Crystal Output. Drives an external crystal. Must be left unconnected if an external clock is driving

RTC_CLKIN.

SINC_CLK0 Output Clock 0.

SINC_D0 Input Data 0.

SINC_D1 Input Data 1.

SINC_D2 Input Data 2.

SINC_D3 Input Data 3.

Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued)

Signal Name Direction Description

Rev. A | Page 29 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

SMC_ABE[n] Output Byte Enable n. Indicates whether the lower or upper byte of a memory is being accessed. When an

asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1 = 0 and

SMC_ABE0 = 1. When an asynchronous write is made to the lower byte of a 16-bit memory,

SMC_ABE1 = 1 and SMC_ABE0 = 0.

SMC_AMS[n] Output Memory Select n. Typically connects to the chip select of a memory device.

SMC_AOE Output Output Enable. Asserts at the beginning of the setup period of a read access.

SMC_ARDY Input Asynchronous Ready. Flow control signal used by memory devices to indicate to the SMC when

further transactions may proceed.

SMC_ARE Output Read Enable. Asserts at the beginning of a read access.

SMC_AWE Output Write Enable. Asserts for the duration of a write access period.

SMC_A[nn] Output Address n. Address bus.

SMC_D[nn] InOut Data n. Bidirectional data bus.

SPI_CLK InOut Clock. Input in slave mode, output in master mode.

SPI_D2 InOut Data 2. Transfers serial data in quad mode. Open-drain when ODM mode is enabled.

SPI_D3 InOut Data 3. Transfers serial data in quad mode. Open-drain when ODM mode is enabled.

SPI_MISO InOut Master In, Slave Out. Transfers serial data. Operates in the same direction as SPI_MOSI in dual and

quad modes. Open-drain when ODM mode is enabled.

SPI_MOSI InOut Master Out, Slave In. Transfers serial data. Operates in the same direction as SPI_MISO in dual and

quad modes. Open-drain when ODM mode is enabled.

SPI_RDY InOut Ready. Optional flow signal. Output in slave mode, input in master mode.

SPI_SEL[n] Output Slave Select Output n. Used in master mode to enable the desired slave.

SPI_SS Input Slave Select Input.

Slave mode—acts as the slave select input.

Master mode—optionally serves as an error detection input for the SPI when there are multiple

masters.

SPT_ACLK InOut Channel A Clock. Data and frame sync are driven/sampled with respect to this clock. This signal can

be either internally or externally generated.

SPT_AD0 InOut Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to

transmit serial data or as an input to receive serial data.

SPT_AD1 InOut Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to

transmit serial data or as an input to receive serial data.

SPT_AFS InOut Channel A Frame Sync. The frame sync pulse initiates shifting of the serial data. This signal is either

generated internally or externally.

SPT_ATDV Output Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in

multichannel transmit mode. It is asserted during enabled slots.

SPT_BCLK InOut Channel B Clock. Data and frame sync are driven/sampled with respect to this clock. This signal can

be either internally or externally generated.

SPT_BD0 InOut Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to

transmit serial data or as an input to receive serial data.

SPT_BD1 InOut Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to

transmit serial data or as an input to receive serial data.

SPT_BFS InOut Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either

generated internally or externally.

SPT_BTDV Output Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in

multichannel transmit mode. It is asserted during enabled slots.

SYS_BMODE[n] Input Boot Mode Control n. Selects the boot mode of the processor.

SYS_CLKIN0 Input Clock/Crystal Input.

SYS_CLKIN1 Input Clock/Crystal Input.

SYS_CLKOUT Output Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter

of the ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference for more details.

Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued)

Signal Name Direction Description

Rev. A | Page 30 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

SYS_FAULT InOut Active-High Fault Output. Indicates internal faults or senses external faults depending on the

operating mode.

SYS_FAULT InOut Active-Low Fault Output. Indicates internal faults or senses external faults depending on the

operating mode.

SYS_HWRST Input Processor Hardware Reset Control. Resets the device when asserted.

SYS_RESOUT Output Reset Output. Indicates the device is in the reset state.

SYS_XTAL0 Output Crystal Output.

SYS_XTAL1 Output Crystal Output.

TM_ACI[n] Input Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.

TM_ACLK[n] Input Alternate Clock n. Provides an additional time base for an individual timer.

TM_CLK Input Clock. Provides an additional global time base for all GP timers.

TM_TMR[n] InOut Timer n. The main input/output signal for each timer.

TRACE_CLK Output Trace Clock. Clock output.

TRACE_D[nn] Output Trace Data n. Unidirectional data bus.

TWI_SCL InOut Serial Clock. Clock output when master, clock input when slave.

TWI_SDA InOut Serial Data. Receives or transmits data.

UART_CTS Input Clear to Send. Flow control signal.

UART_RTS Output Request to Send. Flow control signal.

UART_RX Input Receive. Receives input. Typically connects to a transceiver that meets the electrical requirements of

the device being communicated with.

UART_TX Output Transmit. Transmits output. Typically connects to a transceiver that meets the electrical requirements

of the device being communicated with.

USB_CLKIN Input Clock/Crystal Input. This clock input is multiplied by a PLL to form the USB clock. See data sheet

specifications for frequency/tolerance information.

USB_DM InOut Data –. Bidirectional differential data line.

USB_DP InOut Data +. Bidirectional differential data line.

USB_ID Input OTG ID. Senses whether the controller is a host or device. This signal is pulled low when an A-type

plug is sensed (signifying that the USB controller is the A device).The input is high when a B-type plug

is sensed (signifying that the USB controller is the B device).

USB_VBC Output VBUS Control. Controls an external voltage source to supply VBUS when in host mode. Can be

configured as open-drain. Polarity is configurable as well.

USB_VBUS InOut Bus Voltage. Connects to bus voltage in host and device modes.

USB_XTAL Output Crystal. Drives an external crystal. Must be left unconnected if an external clock is driving USB_CLKIN.

Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued)

Signal Name Direction Description

Rev. A | Page 31 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

349-BALL CSP_BGA SIGNAL DESCRIPTIONS

The processor pin definitions are shown in Table 12 for the

349-ball CSP_BGA package. The columns in this table provide

the following information:

• The signal name column includes the signal name for every

pin and the GPIO multiplexed pin function, where

applicable.

• The description column provides a descriptive name for

each signal.

• The port column shows whether or not a signal is multi-

plexed with other signals on a general-purpose I/O port

pin.

• The pin name column identifies the name of the package

pin (at power on reset) on which the signal is located (if a

single function pin) or is multiplexed (if a general-purpose

I/O pin).

• The DAI pins and their associated signal routing units

(SRUs) connect inputs and outputs of the DAI peripherals

(SPORT, ASRC, S/PDIF, and PCG). See the Digital Audio

Interface (DAI) chapter of the ADSP-SC58x/ADSP-2158x

SHARC+ Processor Hardware Reference for complete

information on the use of the DAI and SRUs.

Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions

Signal Name Description Port Pin Name

ACM0_A0 ACM0 ADC Control Signals C PC_13

ACM0_A1 ACM0 ADC Control Signals C PC_14

ACM0_A2 ACM0 ADC Control Signals C PC_15

ACM0_A3 ACM0 ADC Control Signals D PD_00

ACM0_A4 ACM0 ADC Control Signals D PD_01

ACM0_T0 ACM0 External Trigger n C PC_12

C1_FLG0 SHARC Core 1 Flag Pin E PE_01

C1_FLG1 SHARC Core 1 Flag Pin E PE_03

C1_FLG2 SHARC Core 1 Flag Pin E PE_05

C1_FLG3 SHARC Core 1 Flag Pin E PE_07

C2_FLG0 SHARC Core 2 Flag Pin E PE_02

C2_FLG1 SHARC Core 2 Flag Pin E PE_04

C2_FLG2 SHARC Core 2 Flag Pin E PE_06

C2_FLG3 SHARC Core 2 Flag Pin E PE_08

CAN0_RX CAN0 Receive C PC_07

CAN0_TX CAN0 Transmit C PC_08

CAN1_RX CAN1 Receive B PB_10

CAN1_TX CAN1 Transmit B PB_09

CNT0_DG CNT0 Count Down and Gate B PB_14

CNT0_UD CNT0 Count Up and Direction B PB_12

CNT0_ZM CNT0 Count Zero Marker B PB_11

DAI0_PIN01 DAI0 Pin 1 Not Muxed DAI0_PIN01

DAI0_PIN02 DAI0 Pin 2 Not Muxed DAI0_PIN02

DAI0_PIN03 DAI0 Pin 3 Not Muxed DAI0_PIN03

DAI0_PIN04 DAI0 Pin 4 Not Muxed DAI0_PIN04

DAI0_PIN05 DAI0 Pin 5 Not Muxed DAI0_PIN05

DAI0_PIN06 DAI0 Pin 6 Not Muxed DAI0_PIN06

DAI0_PIN07 DAI0 Pin 7 Not Muxed DAI0_PIN07

DAI0_PIN08 DAI0 Pin 8 Not Muxed DAI0_PIN08

DAI0_PIN09 DAI0 Pin 9 Not Muxed DAI0_PIN09

DAI0_PIN10 DAI0 Pin 10 Not Muxed DAI0_PIN10

DAI0_PIN11 DAI0 Pin 11 Not Muxed DAI0_PIN11

DAI0_PIN12 DAI0 Pin 12 Not Muxed DAI0_PIN12

DAI0_PIN19 DAI0 Pin 19 Not Muxed DAI0_PIN19

DAI0_PIN20 DAI0 Pin 20 Not Muxed DAI0_PIN20

Rev. A | Page 32 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

DAI1_PIN01 DAI1 Pin 1 Not Muxed DAI1_PIN01

DAI1_PIN02 DAI1 Pin 2 Not Muxed DAI1_PIN02

DAI1_PIN03 DAI1 Pin 3 Not Muxed DAI1_PIN03

DAI1_PIN04 DAI1 Pin 4 Not Muxed DAI1_PIN04

DAI1_PIN05 DAI1 Pin 5 Not Muxed DAI1_PIN05

DAI1_PIN06 DAI1 Pin 6 Not Muxed DAI1_PIN06

DAI1_PIN07 DAI1 Pin 7 Not Muxed DAI1_PIN07

DAI1_PIN08 DAI1 Pin 8 Not Muxed DAI1_PIN08

DAI1_PIN09 DAI1 Pin 9 Not Muxed DAI1_PIN09

DAI1_PIN10 DAI1 Pin 10 Not Muxed DAI1_PIN10

DAI1_PIN11 DAI1 Pin 11 Not Muxed DAI1_PIN11

DAI1_PIN12 DAI1 Pin 12 Not Muxed DAI1_PIN12

DAI1_PIN19 DAI1 Pin 19 Not Muxed DAI1_PIN19

DAI1_PIN20 DAI1 Pin 20 Not Muxed DAI1_PIN20

DMC0_A00 DMC0 Address 0 Not Muxed DMC0_A00

DMC0_A01 DMC0 Address 1 Not Muxed DMC0_A01

DMC0_A02 DMC0 Address 2 Not Muxed DMC0_A02

DMC0_A03 DMC0 Address 3 Not Muxed DMC0_A03

DMC0_A04 DMC0 Address 4 Not Muxed DMC0_A04

DMC0_A05 DMC0 Address 5 Not Muxed DMC0_A05

DMC0_A06 DMC0 Address 6 Not Muxed DMC0_A06

DMC0_A07 DMC0 Address 7 Not Muxed DMC0_A07

DMC0_A08 DMC0 Address 8 Not Muxed DMC0_A08

DMC0_A09 DMC0 Address 9 Not Muxed DMC0_A09

DMC0_A10 DMC0 Address 10 Not Muxed DMC0_A10

DMC0_A11 DMC0 Address 11 Not Muxed DMC0_A11

DMC0_A12 DMC0 Address 12 Not Muxed DMC0_A12

DMC0_A13 DMC0 Address 13 Not Muxed DMC0_A13

DMC0_A14 DMC0 Address 14 Not Muxed DMC0_A14

DMC0_A15 DMC0 Address 15 Not Muxed DMC0_A15

DMC0_BA0 DMC0 Bank Address 0 Not Muxed DMC0_BA0

DMC0_BA1 DMC0 Bank Address 1 Not Muxed DMC0_BA1

DMC0_BA2 DMC0 Bank Address 2 Not Muxed DMC0_BA2

DMC0_CAS DMC0 Column Address Strobe Not Muxed DMC0_CAS

DMC0_CK DMC0 Clock Not Muxed DMC0_CK

DMC0_CKE DMC0 Clock enable Not Muxed DMC0_CKE

DMC0_CK DMC0 Clock (complement) Not Muxed DMC0_CK

DMC0_CS0 DMC0 Chip Select 0 Not Muxed DMC0_CS0

DMC0_DQ00 DMC0 Data 0 Not Muxed DMC0_DQ00

DMC0_DQ01 DMC0 Data 1 Not Muxed DMC0_DQ01

DMC0_DQ02 DMC0 Data 2 Not Muxed DMC0_DQ02

DMC0_DQ03 DMC0 Data 3 Not Muxed DMC0_DQ03

DMC0_DQ04 DMC0 Data 4 Not Muxed DMC0_DQ04

DMC0_DQ05 DMC0 Data 5 Not Muxed DMC0_DQ05

DMC0_DQ06 DMC0 Data 6 Not Muxed DMC0_DQ06

DMC0_DQ07 DMC0 Data 7 Not Muxed DMC0_DQ07

DMC0_DQ08 DMC0 Data 8 Not Muxed DMC0_DQ08

DMC0_DQ09 DMC0 Data 9 Not Muxed DMC0_DQ09

Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name Description Port Pin Name

Rev. A | Page 33 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

DMC0_DQ10 DMC0 Data 10 Not Muxed DMC0_DQ10

DMC0_DQ11 DMC0 Data 11 Not Muxed DMC0_DQ11

DMC0_DQ12 DMC0 Data 12 Not Muxed DMC0_DQ12

DMC0_DQ13 DMC0 Data 13 Not Muxed DMC0_DQ13

DMC0_DQ14 DMC0 Data 14 Not Muxed DMC0_DQ14

DMC0_DQ15 DMC0 Data 15 Not Muxed DMC0_DQ15

DMC0_LDM DMC0 Data Mask for Lower Byte Not Muxed DMC0_LDM

DMC0_LDQS DMC0 Data Strobe for Lower Byte Not Muxed DMC0_LDQS

DMC0_LDQS DMC0 Data Strobe for Lower Byte (complement) Not Muxed DMC0_LDQS

DMC0_ODT DMC0 On-die termination Not Muxed DMC0_ODT

DMC0_RAS DMC0 Row Address Strobe Not Muxed DMC0_RAS

DMC0_RESET DMC0 Reset (DDR3 only) Not Muxed DMC0_RESET

DMC0_RZQ DMC0 External calibration resistor connection Not Muxed DMC0_RZQ

DMC0_UDM DMC0 Data Mask for Upper Byte Not Muxed DMC0_UDM

DMC0_UDQS DMC0 Data Strobe for Upper Byte Not Muxed DMC0_UDQS

DMC0_UDQS DMC0 Data Strobe for Upper Byte (complement) Not Muxed DMC0_UDQS

DMC0_VREF DMC0 Voltage Reference Not Muxed DMC0_VREF

DMC0_WE DMC0 Write Enable Not Muxed DMC0_WE

ETH0_CRS ETH0 Carrier Sense/RMII Receive Data Valid A PA_07

ETH0_MDC ETH0 Management Channel Clock A PA_02

ETH0_MDIO ETH0 Management Channel Serial Data A PA_03

ETH0_PTPAUXIN0 ETH0 PTP Auxiliary Trigger Input 0 B PB_03

ETH0_PTPAUXIN1 ETH0 PTP Auxiliary Trigger Input 1 B PB_04

ETH0_PTPAUXIN2 ETH0 PTP Auxiliary Trigger Input 2 B PB_05

ETH0_PTPAUXIN3 ETH0 PTP Auxiliary Trigger Input 3 B PB_06

ETH0_PTPCLKIN0 ETH0 PTP Clock Input 0 B PB_02

ETH0_PTPPPS0 ETH0 PTP Pulse Per Second Output 0 B PB_01

ETH0_PTPPPS1 ETH0 PTP Pulse Per Second Output 1 B PB_00

ETH0_PTPPPS2 ETH0 PTP Pulse Per Second Output 2 A PA_15

ETH0_PTPPPS3 ETH0 PTP Pulse Per Second Output 3 A PA_14

ETH0_RXCLK_REFCLK ETH0 RXCLK (GigE) or REFCLK (10/100) A PA_06

ETH0_RXCTL_CRS ETH0 RXCTL (GigE) or CRS (10/100) A PA_07

ETH0_RXD0 ETH0 Receive Data 0 A PA_04

ETH0_RXD1 ETH0 Receive Data 1 A PA_05

ETH0_RXD2 ETH0 Receive Data 2 A PA_08

ETH0_RXD3 ETH0 Receive Data 3 A PA_09

ETH0_TXCLK ETH0 Transmit Clock A PA_11

ETH0_TXCTL_TXEN ETH0 TXCTL (GigE) or TXEN (10/100) A PA_10

ETH0_TXD0 ETH0 Transmit Data 0 A PA_00

ETH0_TXD1 ETH0 Transmit Data 1 A PA_01

ETH0_TXD2 ETH0 Transmit Data 2 A PA_12

ETH0_TXD3 ETH0 Transmit Data 3 A PA_13

ETH0_TXEN ETH0 Transmit Enable A PA_10

HADC0_VIN0 HADC0 Analog Input at channel 0 Not Muxed HADC0_VIN0

HADC0_VIN1 HADC0 Analog Input at channel 1 Not Muxed HADC0_VIN1

HADC0_VIN2 HADC0 Analog Input at channel 2 Not Muxed HADC0_VIN2

HADC0_VIN3 HADC0 Analog Input at channel 3 Not Muxed HADC0_VIN3

HADC0_VIN4 HADC0 Analog Input at channel 4 Not Muxed HADC0_VIN4

Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name Description Port Pin Name

Rev. A | Page 34 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

HADC0_VIN5 HADC0 Analog Input at channel 5 Not Muxed HADC0_VIN5

HADC0_VIN6 HADC0 Analog Input at channel 6 Not Muxed HADC0_VIN6

HADC0_VIN7 HADC0 Analog Input at channel 7 Not Muxed HADC0_VIN7

HADC0_VREFN HADC0 Ground Reference for ADC Not Muxed HADC0_VREFN

HADC0_VREFP HADC0 External Reference for ADC Not Muxed HADC0_VREFP

JTG_TCK TAPC JTAG Clock Not Muxed JTG_TCK

JTG_TDI TAPC JTAG Serial Data In Not Muxed JTG_TDI

JTG_TDO TAPC JTAG Serial Data Out Not Muxed JTG_TDO

JTG_TMS TAPC JTAG Mode Select Not Muxed JTG_TMS

JTG_TRST TAPC JTAG Reset Not Muxed JTG_TRST

LP0_ACK LP0 Acknowledge D PD_11

LP0_CLK LP0 Clock D PD_10

LP0_D0 LP0 Data 0 D PD_02

LP0_D1 LP0 Data 1 D PD_03

LP0_D2 LP0 Data 2 D PD_04

LP0_D3 LP0 Data 3 D PD_05

LP0_D4 LP0 Data 4 D PD_06

LP0_D5 LP0 Data 5 D PD_07

LP0_D6 LP0 Data 6 D PD_08

LP0_D7 LP0 Data 7 D PD_09

LP1_ACK LP1 Acknowledge B PB_15

LP1_CLK LP1 Clock C PC_00

LP1_D0 LP1 Data 0 B PB_07

LP1_D1 LP1 Data 1 B PB_08

LP1_D2 LP1 Data 2 B PB_09

LP1_D3 LP1 Data 3 B PB_10

LP1_D4 LP1 Data 4 B PB_11

LP1_D5 LP1 Data 5 B PB_12

LP1_D6 LP1 Data 6 B PB_13

LP1_D7 LP1 Data 7 B PB_14

MLB0_CLKN MLB0 Negative Differential Clock (–) Not Muxed MLB0_CLKN

MLB0_CLKP MLB0 Positive Differential Clock (+) Not Muxed MLB0_CLKP

MLB0_DATN MLB0 Negative Differential Data (–) Not Muxed MLB0_DATN

MLB0_DATP MLB0 Positive Differential Data (+) Not Muxed MLB0_DATP

MLB0_SIGN MLB0 Negative Differential Signal (–) Not Muxed MLB0_SIGN

MLB0_SIGP MLB0 Positive Differential Signal (+) Not Muxed MLB0_SIGP

MLB0_CLK MLB0 Single-Ended Clock B PB_04

MLB0_DAT MLB0 Single-Ended Data B PB_06

MLB0_SIG MLB0 Single-Ended Signal B PB_05

MLB0_CLKOUT MLB0 Single-Ended Clock Out D PD_14

PA_00-15 PORTA Position 00 through Position 15 A PA_00-15

PB_00-15 PORTB Position 00 through Position 15 B PB_00-15

PC_00-15 PORTC Position 00 through Position 15 C PC_00-15

PD_00-15 PORTD Position 00 through Position 15 D PD_00-15

PE_00-15 PORTE Position 00 through Position 15 E PE_00-15

PPI0_CLK EPPI0 Clock E PE_03

PPI0_D00 EPPI0 Data 0 E PE_12

PPI0_D01 EPPI0 Data 1 E PE_11

Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name Description Port Pin Name

Rev. A | Page 35 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

PPI0_D02 EPPI0 Data 2 E PE_10

PPI0_D03 EPPI0 Data 3 E PE_09

PPI0_D04 EPPI0 Data 4 E PE_08

PPI0_D05 EPPI0 Data 5 E PE_07

PPI0_D06 EPPI0 Data 6 E PE_06

PPI0_D07 EPPI0 Data 7 E PE_05

PPI0_D08 EPPI0 Data 8 E PE_04

PPI0_D09 EPPI0 Data 9 E PE_00

PPI0_D10 EPPI0 Data 10 D PD_15

PPI0_D11 EPPI0 Data 11 D PD_14

PPI0_D12 EPPI0 Data 12 B PB_04

PPI0_D13 EPPI0 Data 13 B PB_05

PPI0_D14 EPPI0 Data 14 B PB_00

PPI0_D15 EPPI0 Data 15 B PB_01

PPI0_D16 EPPI0 Data 16 B PB_02

PPI0_D17 EPPI0 Data 17 B PB_03

PPI0_D18 EPPI0 Data 18 D PD_13

PPI0_D19 EPPI0 Data 19 D PD_12

PPI0_D20 EPPI0 Data 20 E PE_13

PPI0_D21 EPPI0 Data 21 E PE_14

PPI0_D22 EPPI0 Data 22 E PE_15

PPI0_D23 EPPI0 Data 23 D PD_00

PPI0_FS1 EPPI0 Frame Sync 1 (HSYNC) E PE_02

PPI0_FS2 EPPI0 Frame Sync 2 (VSYNC) E PE_01

PPI0_FS3 EPPI0 Frame Sync 3 (FIELD) C PC_15

PWM0_AH PWM0 Channel A High Side B PB_07

PWM0_AL PWM0 Channel A Low Side B PB_08

PWM0_BH PWM0 Channel B High Side B PB_06

PWM0_BL PWM0 Channel B Low Side C PC_00

PWM0_CH PWM0 Channel C High Side B PB_13

PWM0_CL PWM0 Channel C Low Side B PB_14

PWM0_DH PWM0 Channel D High Side B PB_11

PWM0_DL PWM0 Channel D Low Side B PB_12

PWM0_SYNC PWM0 PWMTMR Grouped E PE_09

PWM0_TRIP0 PWM0 Shutdown Input 0 B PB_15

PWM1_AH PWM1 Channel A High Side D PD_03

PWM1_AL PWM1 Channel A Low Side D PD_04

PWM1_BH PWM1 Channel B High Side D PD_05

PWM1_BL PWM1 Channel B Low Side D PD_06

PWM1_CH PWM1 Channel C High Side D PD_07

PWM1_CL PWM1 Channel C Low Side D PD_08

PWM1_DH PWM1 Channel D High Side D PD_09

PWM1_DL PWM1 Channel D Low Side D PD_10

PWM1_SYNC PWM1 PWMTMR Grouped D PD_11

PWM1_TRIP0 PWM1 Shutdown Input 0 D PD_02

PWM2_CH PWM2 Channel C High Side D PD_15

PWM2_CL PWM2 Channel C Low Side E PE_00

PWM2_DH PWM2 Channel D High Side E PE_04

Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name Description Port Pin Name

Rev. A | Page 36 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

PWM2_DL PWM2 Channel D Low Side E PE_10

PWM2_SYNC PWM2 PWMTMR Grouped E PE_05

PWM2_TRIP0 PWM2 Shutdown Input 0 D PD_14

GND Ground Not Muxed GND

VDD_EXT External Voltage Domain Not Muxed VDD_EXT

VDD_INT Internal Voltage Domain Not Muxed VDD_INT

SINC0_CLK0 SINC0 Clock 0 B PB_01

SINC0_D0 SINC0 Data 0 A PA_14

SINC0_D1 SINC0 Data 1 A PA_15

SINC0_D2 SINC0 Data 2 B PB_00

SINC0_D3 SINC0 Data 3 B PB_04

SMC0_A01 SMC0 Address 1 B PB_05

SMC0_A02 SMC0 Address 2 B PB_06

SMC0_A03 SMC0 Address 3 B PB_03

SMC0_A04 SMC0 Address 4 B PB_02

SMC0_A05 SMC0 Address 5 D PD_13

SMC0_A06 SMC0 Address 6 D PD_12

SMC0_A07 SMC0 Address 7 B PB_01

SMC0_A08 SMC0 Address 8 B PB_00

SMC0_A09 SMC0 Address 9 A PA_15

SMC0_A10 SMC0 Address 10 A PA_14

SMC0_A11 SMC0 Address 11 A PA_09

SMC0_A12 SMC0 Address 12 A PA_08

SMC0_A13 SMC0 Address 13 A PA_13

SMC0_A14 SMC0 Address 14 A PA_12

SMC0_A15 SMC0 Address 15 A PA_11

SMC0_A16 SMC0 Address 16 A PA_07

SMC0_A17 SMC0 Address 17 A PA_06

SMC0_A18 SMC0 Address 18 A PA_05

SMC0_A19 SMC0 Address 19 A PA_04

SMC0_A20 SMC0 Address 20 A PA_01

SMC0_A21 SMC0 Address 21 A PA_00

SMC0_A22 SMC0 Address 22 A PA_10

SMC0_A23 SMC0 Address 23 A PA_03

SMC0_A24 SMC0 Address 24 A PA_02

SMC0_A25 SMC0 Address 25 C PC_12

SMC0_ABE0 SMC0 Byte Enable 0 E PE_14

SMC0_ABE1 SMC0 Byte Enable 1 E PE_15

SMC0_AMS0 SMC0 Memory Select 0 C PC_15

SMC0_AMS1 SMC0 Memory Select 1 E PE_13

SMC0_AMS2 SMC0 Memory Select 2 C PC_07

SMC0_AMS3 SMC0 Memory Select 3 C PC_08

SMC0_AOE SMC0 Output Enable D PD_01

SMC0_ARDY SMC0 Asynchronous Ready B PB_04

SMC0_ARE SMC0 Read Enable C PC_00

SMC0_AWE SMC0 Write Enable B PB_15

SMC0_D00 SMC0 Data 0 E PE_12

SMC0_D01 SMC0 Data 1 E PE_11

Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name Description Port Pin Name

Rev. A | Page 37 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

SMC0_D02 SMC0 Data 2 E PE_10

SMC0_D03 SMC0 Data 3 E PE_09

SMC0_D04 SMC0 Data 4 E PE_00

SMC0_D05 SMC0 Data 5 D PD_15

SMC0_D06 SMC0 Data 6 D PD_14

SMC0_D07 SMC0 Data 7 D PD_00

SMC0_D08 SMC0 Data 8 B PB_14

SMC0_D09 SMC0 Data 9 B PB_13

SMC0_D10 SMC0 Data 10 B PB_12

SMC0_D11 SMC0 Data 11 B PB_11

SMC0_D12 SMC0 Data 12 B PB_10

SMC0_D13 SMC0 Data 13 B PB_09

SMC0_D14 SMC0 Data 14 B PB_08

SMC0_D15 SMC0 Data 15 B PB_07

SPI0_CLK SPI0 Clock C PC_09

SPI0_MISO SPI0 Master In, Slave Out C PC_10

SPI0_MOSI SPI0 Master Out, Slave In C PC_11

SPI0_RDY SPI0 Ready C PC_12

SPI0_SEL1 SPI0 Slave Select Output 1 C PC_07

SPI0_SEL2 SPI0 Slave Select Output 2 D PD_01

SPI0_SEL3 SPI0 Slave Select Output 3 C PC_12

SPI0_SEL4 SPI0 Slave Select Output 4 C PC_00

SPI0_SEL5 SPI0 Slave Select Output 5 E PE_01

SPI0_SEL6 SPI0 Slave Select Output 6 E PE_02

SPI0_SEL7 SPI0 Slave Select Output 7 E PE_03

SPI0_SS SPI0 Slave Select Input D PD_01

SPI1_CLK SPI1 Clock E PE_13

SPI1_MISO SPI1 Master In, Slave Out E PE_14

SPI1_MOSI SPI1 Master Out, Slave In E PE_15

SPI1_RDY SPI1 Ready E PE_08

SPI1_SEL1 SPI1 Slave Select Output 1 C PC_13

SPI1_SEL2 SPI1 Slave Select Output 2 E PE_07

SPI1_SEL3 SPI1 Slave Select Output 3 E PE_11

SPI1_SEL4 SPI1 Slave Select Output 4 E PE_12

SPI1_SEL5 SPI1 Slave Select Output 5 E PE_08

SPI1_SS SPI1 Slave Select Input E PE_11

SPI2_CLK SPI2 Clock C PC_01

SPI2_D2 SPI2 Data 2 C PC_04

SPI2_D3 SPI2 Data 3 C PC_05

SPI2_MISO SPI2 Master In, Slave Out C PC_02

SPI2_MOSI SPI2 Master Out, Slave In C PC_03

SPI2_RDY SPI2 Ready E PE_12

SPI2_SEL1 SPI2 Slave Select Output 1 C PC_06

SPI2_SEL2 SPI2 Slave Select Output 2 E PE_03

SPI2_SEL3 SPI2 Slave Select Output 3 E PE_04

SPI2_SEL4 SPI2 Slave Select Output 4 E PE_05

SPI2_SEL5 SPI2 Slave Select Output 5 E PE_06

SPI2_SS SPI2 Slave Select Input C PC_06

Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name Description Port Pin Name

Rev. A | Page 38 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

SYS_BMODE0 Boot Mode Control n Not Muxed SYS_BMODE0

SYS_BMODE1 Boot Mode Control n Not Muxed SYS_BMODE1

SYS_BMODE2 Boot Mode Control n Not Muxed SYS_BMODE2

SYS_CLKIN0 Clock/Crystal Input Not Muxed SYS_CLKIN0

SYS_CLKIN1 Clock/Crystal Input Not Muxed SYS_CLKIN1

SYS_CLKOUT Processor Clock Output Not Muxed SYS_CLKOUT

SYS_FAULT Active High Fault Output Not Muxed SYS_FAULT

SYS_FAULT Active Low Fault Output Not Muxed SYS_FAULT

SYS_HWRST Processor Hardware Reset Control Not Muxed SYS_HWRST

SYS_RESOUT Reset Output Not Muxed SYS_RESOUT

SYS_XTAL0 Crystal Output Not Muxed SYS_XTAL0

SYS_XTAL1 Crystal Output Not Muxed SYS_XTAL1

TM0_ACI0 TIMER0 Alternate Capture Input 0 C PC_14

TM0_ACI1 TIMER0 Alternate Capture Input 1 B PB_03

TM0_ACI2 TIMER0 Alternate Capture Input 2 D PD_13

TM0_ACI3 TIMER0 Alternate Capture Input 3 C PC_07

TM0_ACI4 TIMER0 Alternate Capture Input 4 B PB_10

TM0_ACLK1 TIMER0 Alternate Clock 1 D PD_08

TM0_ACLK2 TIMER0 Alternate Clock 2 D PD_09

TM0_ACLK3 TIMER0 Alternate Clock 3 B PB_00

TM0_ACLK4 TIMER0 Alternate Clock 4 B PB_01

TM0_CLK TIMER0 Clock C PC_11

TM0_TMR0 TIMER0 Timer 0 E PE_09

TM0_TMR1 TIMER0 Timer 1 B PB_15

TM0_TMR2 TIMER0 Timer 2 B PB_10

TM0_TMR3 TIMER0 Timer 3 B PB_07

TM0_TMR4 TIMER0 Timer 4 B PB_08

TM0_TMR5 TIMER0 Timer 5 B PB_14

TRACE0_CLK TRACE0 Trace Clock D PD_10

TRACE0_D00 TRACE0 Trace Data 0 D PD_02

TRACE0_D01 TRACE0 Trace Data 1 D PD_03

TRACE0_D02 TRACE0 Trace Data 2 D PD_04

TRACE0_D03 TRACE0 Trace Data 3 D PD_05

TRACE0_D04 TRACE0 Trace Data 4 D PD_06

TRACE0_D05 TRACE0 Trace Data 5 D PD_07

TRACE0_D06 TRACE0 Trace Data 6 D PD_08

TRACE0_D07 TRACE0 Trace Data 7 D PD_09

TWI0_SCL TWI0 Serial Clock Not Muxed TWI0_SCL

TWI0_SDA TWI0 Serial Data Not Muxed TWI0_SDA

TWI1_SCL TWI1 Serial Clock Not Muxed TWI1_SCL

TWI1_SDA TWI1 Serial Data Not Muxed TWI1_SDA

TWI2_SCL TWI2 Serial Clock Not Muxed TWI2_SCL

TWI2_SDA TWI2 Serial Data Not Muxed TWI2_SDA

UART0_CTS UART0 Clear to Send D PD_00

UART0_RTS UART0 Request to Send C PC_15

UART0_RX UART0 Receive C PC_14

UART0_TX UART0 Transmit C PC_13

UART1_CTS UART1 Clear to Send E PE_01

Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name Description Port Pin Name

Rev. A | Page 39 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

UART1_RTS UART1 Request to Send E PE_02

UART1_RX UART1 Receive B PB_03

UART1_TX UART1 Transmit B PB_02

UART2_CTS UART2 Clear to Send E PE_11

UART2_RTS UART2 Request to Send E PE_10

UART2_RX UART2 Receive D PD_13

UART2_TX UART2 Transmit D PD_12

USB0_CLKIN USB0 Clock/Crystal Input Not Muxed USB_CLKIN

USB0_DM USB0 Negative Data (–) Not Muxed USB0_DM

USB0_DP USB0 Positive Data (+) Not Muxed USB0_DP

USB0_ID USB0 OTG ID Not Muxed USB0_ID

USB0_VBC USB0 VBUS Control Not Muxed USB0_VBC

USB0_VBUS USB0 Bus Voltage Not Muxed USB0_VBUS

USB0_XTAL USB0 Crystal Not Muxed USB_XTAL

VDD_DMC DMC VDD Not Muxed VDD_DMC

VDD_HADC HADC/TMU VDD Not Muxed VDD_HADC

VDD_USB USB VDD Not Muxed VDD_USB

Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name Description Port Pin Name

Rev. A | Page 40 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

GPIO MULTIPLEXING FOR THE 349-BALL CSP_BGA PACKAGE

Table 13 through Table 17 identify the pin functions that are

multiplexed on the general-purpose I/O pins of the 349-ball

CSP_BGA package.

Table 13. Signal Multiplexing for Port A

Signal Name

Multiplexed

Function 0

Multiplexed

Function 1

Multiplexed

Function 2

Multiplexed

Function 3

Multiplexed

Function Input Tap

PA_00 ETH0_TXD0 SMC0_A21

PA_01 ETH0_TXD1 SMC0_A20

PA_02 ETH0_MDC SMC0_A24

PA_03 ETH0_MDIO SMC0_A23

PA_04 ETH0_RXD0 SMC0_A19

PA_05 ETH0_RXD1 SMC0_A18

PA_06 ETH0_RXCLK_REFCLK SMC0_A17

PA_07 ETH0_CRS SMC0_A16

PA_08 ETH0_RXD2 SMC0_A12

PA_09 ETH0_RXD3 SMC0_A11

PA_10 ETH0_TXEN SMC0_A22

PA_11 ETH0_TXCLK SMC0_A15

PA_12 ETH0_TXD2 SMC0_A14

PA_13 ETH0_TXD3 SMC0_A13

PA_14 ETH0_PTPPPS3 SINC0_D0 SMC0_A10

PA_15 ETH0_PTPPPS2 SINC0_D1 SMC0_A09

Table 14. Signal Multiplexing for Port B

Signal Name

Multiplexed

Function 0

Multiplexed

Function 1

Multiplexed

Function 2

Multiplexed

Function 3

Multiplexed

Function Input Tap

PB_00 ETH0_PTPPPS1 SINC0_D2 PPI0_D14 SMC0_A08 TM0_ACLK3

PB_01 ETH0_PTPPPS0 SINC0_CLK0 PPI0_D15 SMC0_A07 TM0_ACLK4

PB_02 ETH0_PTPCLKIN0 UART1_TX PPI0_D16 SMC0_A04

PB_03 ETH0_PTPAUXIN0 UART1_RX PPI0_D17 SMC0_A03 TM0_ACI1

PB_04 MLB0_CLK SINC0_D3 PPI0_D12 SMC0_ARDY ETH0_PTPAUXIN1

PB_05 MLB0_SIG PPI0_D13 SMC0_A01 ETH0_PTPAUXIN2

PB_06 MLB0_DAT PWM0_BH SMC0_A02 ETH0_PTPAUXIN3

PB_07 LP1_D0 PWM0_AH TM0_TMR3 SMC0_D15

PB_08 LP1_D1 PWM0_AL TM0_TMR4 SMC0_D14

PB_09 LP1_D2 CAN1_TX SMC0_D13

PB_10 LP1_D3 TM0_TMR2 CAN1_RX SMC0_D12 TM0_ACI4

PB_11 LP1_D4 PWM0_DH SMC0_D11 CNT0_ZM

PB_12 LP1_D5 PWM0_DL SMC0_D10 CNT0_UD

PB_13 LP1_D6 PWM0_CH SMC0_D09

PB_14 LP1_D7 TM0_TMR5 PWM0_CL SMC0_D08 CNT0_DG

PB_15 LP1_ACK PWM0_TRIP0 TM0_TMR1 SMC0_AWE

Rev. A | Page 41 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

Table 15. Signal Multiplexing for Port C

Signal Name

Multiplexed

Function 0

Multiplexed

Function 1

Multiplexed

Function 2

Multiplexed

Function 3

Multiplexed

Function Input Tap

PC_00 LP1_CLK PWM0_BL SPI0_SEL4 SMC0_ARE

PC_01 SPI2_CLK

PC_02 SPI2_MISO

PC_03 SPI2_MOSI

PC_04 SPI2_D2

PC_05 SPI2_D3

PC_06 SPI2_SEL1 SPI2_SS

PC_07 CAN0_RX SPI0_SEL1 SMC0_AMS2 TM0_ACI3

PC_08 CAN0_TX SMC0_AMS3

PC_09 SPI0_CLK

PC_10 SPI0_MISO

PC_11 SPI0_MOSI TM0_CLK

PC_12 SPI0_SEL3 SPI0_RDY ACM0_T0 SMC0_A25

PC_13 UART0_TX SPI1_SEL1 ACM0_A0

PC_14 UART0_RX ACM0_A1 TM0_ACI0

PC_15 UART0_RTS PPI0_FS3 ACM0_A2 SMC0_AMS0

Table 16. Signal Multiplexing for Port D

Signal Name

Multiplexed

Function 0

Multiplexed

Function 1

Multiplexed

Function 2

Multiplexed

Function 3

Multiplexed

Function Input Tap

PD_00 UART0_CTS PPI0_D23 ACM0_A3 SMC0_D07

PD_01 SPI0_SEL2 ACM0_A4 SMC0_AOE SPI0_SS

PD_02 LP0_D0 PWM1_TRIP0 TRACE0_D00

PD_03 LP0_D1 PWM1_AH TRACE0_D01

PD_04 LP0_D2 PWM1_AL TRACE0_D02

PD_05 LP0_D3 PWM1_BH TRACE0_D03

PD_06 LP0_D4 PWM1_BL TRACE0_D04

PD_07 LP0_D5 PWM1_CH TRACE0_D05

PD_08 LP0_D6 PWM1_CL TRACE0_D06 TM0_ACLK1

PD_09 LP0_D7 PWM1_DH TRACE0_D07 TM0_ACLK2

PD_10 LP0_CLK PWM1_DL TRACE0_CLK

PD_11 LP0_ACK PWM1_SYNC

PD_12 UART2_TX PPI0_D19 SMC0_A06

PD_13 UART2_RX PPI0_D18 SMC0_A05 TM0_ACI2

PD_14 PPI0_D11 PWM2_TRIP0 MLB0_CLKOUT SMC0_D06

PD_15 PPI0_D10 PWM2_CH SMC0_D05

Rev. A | Page 42 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

Table 18 shows the internal timer signal routing. This table

applies to both the 349-ball and 529-ball CSP_BGA packages.

Table 17. Signal Multiplexing for Port E

Signal Name

Multiplexed

Function 0

Multiplexed

Function 1

Multiplexed

Function 2

Multiplexed

Function 3

Multiplexed

Function Input Tap

PE_00 PPI0_D09 PWM2_CL SMC0_D04

PE_01 PPI0_FS2 SPI0_SEL5 UART1_CTS C1_FLG0

PE_02 PPI0_FS1 SPI0_SEL6 UART1_RTS C2_FLG0

PE_03 PPI0_CLK SPI0_SEL7 SPI2_SEL2 C1_FLG1

PE_04 PPI0_D08 PWM2_DH SPI2_SEL3 C2_FLG1

PE_05 PPI0_D07 PWM2_SYNC SPI2_SEL4 C1_FLG2

PE_06 PPI0_D06 SPI2_SEL5 C2_FLG2

PE_07 PPI0_D05 SPI1_SEL2 C1_FLG3

PE_08 PPI0_D04 SPI1_SEL5 SPI1_RDY C2_FLG3

PE_09 PPI0_D03 PWM0_SYNC TM0_TMR0 SMC0_D03

PE_10 PPI0_D02 PWM2_DL UART2_RTS SMC0_D02

PE_11 PPI0_D01 SPI1_SEL3 UART2_CTS SMC0_D01 SPI1_SS

PE_12 PPI0_D00 SPI1_SEL4 SPI2_RDY SMC0_D00

PE_13 SPI1_CLK PPI0_D20 SMC0_AMS1

PE_14 SPI1_MISO PPI0_D21 SMC0_ABE0

PE_15 SPI1_MOSI PPI0_D22 SMC0_ABE1

Table 18. Internal Timer Signal Routing

Timer Input Signal Internal Source

TM0_ACLK0 SYS_CLKIN1

TM0_ACI5 DAI0_CRS_PB04_O

TM0_ACLK5 DAI0_CRS_PB03_O

TM0_ACI6 DAI1_CRS_PB04_O

TM0_ACLK6 DAI1_CRS_PB03_O

TM0_ACI7 CNT0_TO

TM0_ACLK7 SYS_CLKIN0

Rev. A | Page 43 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

529-BALL CSP_BGA SIGNAL DESCRIPTIONS

The processor pin definitions are shown Table 19 for the

529-ball CSP_BGA package. The columns in this table provide

the following information:

• The signal name column includes the signal name for every

pin and the GPIO multiplexed pin function, where

applicable.

• The description column provides a descriptive name for

each signal.

• The port column shows whether or not a signal is multi-

plexed with other signals on a general-purpose I/O port

pin.

• The pin name column identifies the name of the package

pin (at power on reset) on which the signal is located (if a

single function pin) or is multiplexed (if a general-purpose

I/O pin).

• The DAI pins and their associated signal routing units

(SRUs) connect inputs and outputs of the DAI peripherals

(SPORT, ASRC, S/PDIF, and PCG). See the Digital Audio

Interface (DAI) chapter of the ADSP-SC58x/ADSP-2158x

SHARC+ Processor Hardware Reference for complete

information on the use of the DAIs and SRUs.

Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions

Signal Name Description Port Pin Name

ACM0_A0 ACM0 ADC Control Signals C PC_13

ACM0_A1 ACM0 ADC Control Signals C PC_14

ACM0_A2 ACM0 ADC Control Signals C PC_15

ACM0_A3 ACM0 ADC Control Signals D PD_00

ACM0_A4 ACM0 ADC Control Signals D PD_01

ACM0_T0 ACM0 External Trigger n C PC_12

C1_FLG0 SHARC Core 1 Flag Pin E PE_01

C1_FLG1 SHARC Core 1 Flag Pin E PE_03

C1_FLG2 SHARC Core 1 Flag Pin E PE_05

C1_FLG3 SHARC Core 1 Flag Pin E PE_07

C2_FLG0 SHARC Core 2 Flag Pin E PE_02

C2_FLG1 SHARC Core 2 Flag Pin E PE_04

C2_FLG2 SHARC Core 2 Flag Pin E PE_06

C2_FLG3 SHARC Core 2 Flag Pin E PE_08

CAN0_RX CAN0 Receive C PC_07

CAN0_TX CAN0 Transmit C PC_08

CAN1_RX CAN1 Receive B PB_10

CAN1_TX CAN1 Transmit B PB_09

CNT0_DG CNT0 Count Down and Gate B PB_14

CNT0_UD CNT0 Count Up and Direction B PB_12

CNT0_ZM CNT0 Count Zero Marker B PB_11

DAI0_PIN01 DAI0 Pin 1 Not Muxed DAI0_PIN01

DAI0_PIN02 DAI0 Pin 2 Not Muxed DAI0_PIN02

DAI0_PIN03 DAI0 Pin 3 Not Muxed DAI0_PIN03

DAI0_PIN04 DAI0 Pin 4 Not Muxed DAI0_PIN04

DAI0_PIN05 DAI0 Pin 5 Not Muxed DAI0_PIN05

DAI0_PIN06 DAI0 Pin 6 Not Muxed DAI0_PIN06

DAI0_PIN07 DAI0 Pin 7 Not Muxed DAI0_PIN07

DAI0_PIN08 DAI0 Pin 8 Not Muxed DAI0_PIN08

DAI0_PIN09 DAI0 Pin 9 Not Muxed DAI0_PIN09

DAI0_PIN10 DAI0 Pin 10 Not Muxed DAI0_PIN10

DAI0_PIN11 DAI0 Pin 11 Not Muxed DAI0_PIN11

DAI0_PIN12 DAI0 Pin 12 Not Muxed DAI0_PIN12

DAI0_PIN13 DAI0 Pin 13 Not Muxed DAI0_PIN13

DAI0_PIN14 DAI0 Pin 14 Not Muxed DAI0_PIN14

Rev. A | Page 44 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

DAI0_PIN15 DAI0 Pin 15 Not Muxed DAI0_PIN15

DAI0_PIN16 DAI0 Pin 16 Not Muxed DAI0_PIN16

DAI0_PIN17 DAI0 Pin 17 Not Muxed DAI0_PIN17

DAI0_PIN18 DAI0 Pin 18 Not Muxed DAI0_PIN18

DAI0_PIN19 DAI0 Pin 19 Not Muxed DAI0_PIN19

DAI0_PIN20 DAI0 Pin 20 Not Muxed DAI0_PIN20

DAI1_PIN01 DAI1 Pin 1 Not Muxed DAI1_PIN01

DAI1_PIN02 DAI1 Pin 2 Not Muxed DAI1_PIN02

DAI1_PIN03 DAI1 Pin 3 Not Muxed DAI1_PIN03

DAI1_PIN04 DAI1 Pin 4 Not Muxed DAI1_PIN04

DAI1_PIN05 DAI1 Pin 5 Not Muxed DAI1_PIN05

DAI1_PIN06 DAI1 Pin 6 Not Muxed DAI1_PIN06

DAI1_PIN07 DAI1 Pin 7 Not Muxed DAI1_PIN07

DAI1_PIN08 DAI1 Pin 8 Not Muxed DAI1_PIN08

DAI1_PIN09 DAI1 Pin 9 Not Muxed DAI1_PIN09

DAI1_PIN10 DAI1 Pin 10 Not Muxed DAI1_PIN10

DAI1_PIN11 DAI1 Pin 11 Not Muxed DAI1_PIN11

DAI1_PIN12 DAI1 Pin 12 Not Muxed DAI1_PIN12

DAI1_PIN13 DAI1 Pin 13 Not Muxed DAI1_PIN13

DAI1_PIN14 DAI1 Pin 14 Not Muxed DAI1_PIN14

DAI1_PIN15 DAI1 Pin 15 Not Muxed DAI1_PIN15

DAI1_PIN16 DAI1 Pin 16 Not Muxed DAI1_PIN16

DAI1_PIN17 DAI1 Pin 17 Not Muxed DAI1_PIN17

DAI1_PIN18 DAI1 Pin 18 Not Muxed DAI1_PIN18

DAI1_PIN19 DAI1 Pin 19 Not Muxed DAI1_PIN19

DAI1_PIN20 DAI1 Pin 20 Not Muxed DAI1_PIN20

DMC0_A00 DMC0 Address 0 Not Muxed DMC0_A00

DMC0_A01 DMC0 Address 1 Not Muxed DMC0_A01

DMC0_A02 DMC0 Address 2 Not Muxed DMC0_A02

DMC0_A03 DMC0 Address 3 Not Muxed DMC0_A03

DMC0_A04 DMC0 Address 4 Not Muxed DMC0_A04

DMC0_A05 DMC0 Address 5 Not Muxed DMC0_A05

DMC0_A06 DMC0 Address 6 Not Muxed DMC0_A06

DMC0_A07 DMC0 Address 7 Not Muxed DMC0_A07

DMC0_A08 DMC0 Address 8 Not Muxed DMC0_A08

DMC0_A09 DMC0 Address 9 Not Muxed DMC0_A09

DMC0_A10 DMC0 Address 10 Not Muxed DMC0_A10

DMC0_A11 DMC0 Address 11 Not Muxed DMC0_A11

DMC0_A12 DMC0 Address 12 Not Muxed DMC0_A12

DMC0_A13 DMC0 Address 13 Not Muxed DMC0_A13

DMC0_A14 DMC0 Address 14 Not Muxed DMC0_A14

DMC0_A15 DMC0 Address 15 Not Muxed DMC0_A15

DMC0_BA0 DMC0 Bank Address 0 Not Muxed DMC0_BA0

DMC0_BA1 DMC0 Bank Address 1 Not Muxed DMC0_BA1

DMC0_BA2 DMC0 Bank Address 2 Not Muxed DMC0_BA2

DMC0_CAS DMC0 Column Address Strobe Not Muxed DMC0_CAS

DMC0_CK DMC0 Clock Not Muxed DMC0_CK

DMC0_CKE DMC0 Clock enable Not Muxed DMC0_CKE

Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name Description Port Pin Name

Rev. A | Page 45 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

DMC0_CK DMC0 Clock (complement) Not Muxed DMC0_CK

DMC0_CS0 DMC0 Chip Select 0 Not Muxed DMC0_CS0

DMC0_DQ00 DMC0 Data 0 Not Muxed DMC0_DQ00

DMC0_DQ01 DMC0 Data 1 Not Muxed DMC0_DQ01

DMC0_DQ02 DMC0 Data 2 Not Muxed DMC0_DQ02

DMC0_DQ03 DMC0 Data 3 Not Muxed DMC0_DQ03

DMC0_DQ04 DMC0 Data 4 Not Muxed DMC0_DQ04

DMC0_DQ05 DMC0 Data 5 Not Muxed DMC0_DQ05

DMC0_DQ06 DMC0 Data 6 Not Muxed DMC0_DQ06

DMC0_DQ07 DMC0 Data 7 Not Muxed DMC0_DQ07

DMC0_DQ08 DMC0 Data 8 Not Muxed DMC0_DQ08

DMC0_DQ09 DMC0 Data 9 Not Muxed DMC0_DQ09

DMC0_DQ10 DMC0 Data 10 Not Muxed DMC0_DQ10

DMC0_DQ11 DMC0 Data 11 Not Muxed DMC0_DQ11

DMC0_DQ12 DMC0 Data 12 Not Muxed DMC0_DQ12

DMC0_DQ13 DMC0 Data 13 Not Muxed DMC0_DQ13

DMC0_DQ14 DMC0 Data 14 Not Muxed DMC0_DQ14

DMC0_DQ15 DMC0 Data 15 Not Muxed DMC0_DQ15

DMC0_LDM DMC0 Data Mask for Lower Byte Not Muxed DMC0_LDM

DMC0_LDQS DMC0 Data Strobe for Lower Byte Not Muxed DMC0_LDQS

DMC0_LDQS DMC0 Data Strobe for Lower Byte (complement) Not Muxed DMC0_LDQS

DMC0_ODT DMC0 On-die termination Not Muxed DMC0_ODT

DMC0_RAS DMC0 Row Address Strobe Not Muxed DMC0_RAS

DMC0_RESET DMC0 Reset (DDR3 only) Not Muxed DMC0_RESET

DMC0_RZQ DMC0 External calibration resistor connection Not Muxed DMC0_RZQ

DMC0_UDM DMC0 Data Mask for Upper Byte Not Muxed DMC0_UDM

DMC0_UDQS DMC0 Data Strobe for Upper Byte Not Muxed DMC0_UDQS

DMC0_UDQS DMC0 Data Strobe for Upper Byte (complement) Not Muxed DMC0_UDQS

DMC0_VREF DMC0 Voltage Reference Not Muxed DMC0_VREF

DMC0_WE DMC0 Write Enable Not Muxed DMC0_WE

DMC1_A00 DMC1 Address 0 Not Muxed DMC1_A00

DMC1_A01 DMC1 Address 1 Not Muxed DMC1_A01

DMC1_A02 DMC1 Address 2 Not Muxed DMC1_A02

DMC1_A03 DMC1 Address 3 Not Muxed DMC1_A03

DMC1_A04 DMC1 Address 4 Not Muxed DMC1_A04

DMC1_A05 DMC1 Address 5 Not Muxed DMC1_A05

DMC1_A06 DMC1 Address 6 Not Muxed DMC1_A06

DMC1_A07 DMC1 Address 7 Not Muxed DMC1_A07

DMC1_A08 DMC1 Address 8 Not Muxed DMC1_A08

DMC1_A09 DMC1 Address 9 Not Muxed DMC1_A09

DMC1_A10 DMC1 Address 10 Not Muxed DMC1_A10

DMC1_A11 DMC1 Address 11 Not Muxed DMC1_A11

DMC1_A12 DMC1 Address 12 Not Muxed DMC1_A12

DMC1_A13 DMC1 Address 13 Not Muxed DMC1_A13

DMC1_A14 DMC1 Address 14 Not Muxed DMC1_A14

DMC1_A15 DMC1 Address 15 Not Muxed DMC1_A15

DMC1_BA0 DMC1 Bank Address 0 Not Muxed DMC1_BA0

DMC1_BA1 DMC1 Bank Address 1 Not Muxed DMC1_BA1

Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name Description Port Pin Name

Rev. A | Page 46 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

DMC1_BA2 DMC1 Bank Address 2 Not Muxed DMC1_BA2

DMC1_CAS DMC1 Column Address Strobe Not Muxed DMC1_CAS

DMC1_CK DMC1 Clock Not Muxed DMC1_CK

DMC1_CKE DMC1 Clock enable Not Muxed DMC1_CKE

DMC1_CK DMC1 Clock (complement) Not Muxed DMC1_CK

DMC1_CS0 DMC1 Chip Select 0 Not Muxed DMC1_CS0

DMC1_DQ00 DMC1 Data 0 Not Muxed DMC1_DQ00

DMC1_DQ01 DMC1 Data 1 Not Muxed DMC1_DQ01

DMC1_DQ02 DMC1 Data 2 Not Muxed DMC1_DQ02

DMC1_DQ03 DMC1 Data 3 Not Muxed DMC1_DQ03

DMC1_DQ04 DMC1 Data 4 Not Muxed DMC1_DQ04

DMC1_DQ05 DMC1 Data 5 Not Muxed DMC1_DQ05

DMC1_DQ06 DMC1 Data 6 Not Muxed DMC1_DQ06

DMC1_DQ07 DMC1 Data 7 Not Muxed DMC1_DQ07

DMC1_DQ08 DMC1 Data 8 Not Muxed DMC1_DQ08

DMC1_DQ09 DMC1 Data 9 Not Muxed DMC1_DQ09

DMC1_DQ10 DMC1 Data 10 Not Muxed DMC1_DQ10

DMC1_DQ11 DMC1 Data 11 Not Muxed DMC1_DQ11

DMC1_DQ12 DMC1 Data 12 Not Muxed DMC1_DQ12

DMC1_DQ13 DMC1 Data 13 Not Muxed DMC1_DQ13

DMC1_DQ14 DMC1 Data 14 Not Muxed DMC1_DQ14

DMC1_DQ15 DMC1 Data 15 Not Muxed DMC1_DQ15

DMC1_LDM DMC1 Data Mask for Lower Byte Not Muxed DMC1_LDM

DMC1_LDQS DMC1 Data Strobe for Lower Byte Not Muxed DMC1_LDQS

DMC1_LDQS DMC1 Data Strobe for Lower Byte (complement) Not Muxed DMC1_LDQS

DMC1_ODT DMC1 On-die termination Not Muxed DMC1_ODT

DMC1_RAS DMC1 Row Address Strobe Not Muxed DMC1_RAS

DMC1_RESET DMC1 Reset (DDR3 only) Not Muxed DMC1_RESET

DMC1_RZQ DMC1 External calibration resistor connection Not Muxed DMC1_RZQ

DMC1_UDM DMC1 Data Mask for Upper Byte Not Muxed DMC1_UDM

DMC1_UDQS DMC1 Data Strobe for Upper Byte Not Muxed DMC1_UDQS

DMC1_UDQS DMC1 Data Strobe for Upper Byte (complement) Not Muxed DMC1_UDQS

DMC1_VREF DMC1 Voltage Reference Not Muxed DMC1_VREF

DMC1_WE DMC1 Write Enable Not Muxed DMC1_WE

ETH0_CRS ETH0 Carrier Sense/RMII Receive Data Valid A PA_07

ETH0_MDC ETH0 Management Channel Clock A PA_02

ETH0_MDIO ETH0 Management Channel Serial Data A PA_03

ETH0_PTPAUXIN0 ETH0 PTP Auxiliary Trigger Input 0 B PB_03

ETH0_PTPAUXIN1 ETH0 PTP Auxiliary Trigger Input 1 B PB_04

ETH0_PTPAUXIN2 ETH0 PTP Auxiliary Trigger Input 2 B PB_05

ETH0_PTPAUXIN3 ETH0 PTP Auxiliary Trigger Input 3 B PB_06

ETH0_PTPCLKIN0 ETH0 PTP Clock Input 0 B PB_02

ETH0_PTPPPS0 ETH0 PTP Pulse-Per-Second Output 0 B PB_01

ETH0_PTPPPS1 ETH0 PTP Pulse-Per-Second Output 1 B PB_00

ETH0_PTPPPS2 ETH0 PTP Pulse-Per-Second Output 2 A PA_15

ETH0_PTPPPS3 ETH0 PTP Pulse-Per-Second Output 3 A PA_14

ETH0_RXCLK_REFCLK ETH0 RXCLK (GigE) or REFCLK (10/100) A PA_06

ETH0_RXCTL_CRS ETH0 RXCTL (GigE) or CRS (10/100) A PA_07

Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)

Signal Name Description Port Pin Name

Rev. A | Page 47 of 174 | July 2017

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

ETH0_RXD0 ETH0 Receive Data 0 A PA_04

ETH0_RXD1 ETH0 Receive Data 1 A PA_05

ETH0_RXD2 ETH0 Receive Data 2 A PA_08

ETH0_RXD3 ETH0 Receive Data 3 A PA_09

ETH0_TXCLK ETH0 Transmit Clock A PA_11

ETH0_TXCTL_TXEN ETH0 TXCTL (GigE) or TXEN (10/100) A PA_10

ETH0_TXD0 ETH0 Transmit Data 0 A PA_00

ETH0_TXD1 ETH0 Transmit Data 1 A PA_01

ETH0_TXD2 ETH0 Transmit Data 2 A PA_12

ETH0_TXD3 ETH0 Transmit Data 3 A PA_13

ETH0_TXEN ETH0 Transmit Enable A PA_10

ETH1_CRS ETH1 Carrier Sense/RMII Receive Data Valid F PF_13

ETH1_MDC ETH1 Management Channel Clock F PF_14

ETH1_MDIO ETH1 Management Channel Serial Data F PF_15

ETH1_REFCLK ETH1 Reference Clock G PG_00

ETH1_RXD0 ETH1 Receive Data 0 G PG_04

ETH1_RXD1 ETH1 Receive Data 1 G PG_05

ETH1_TXD0 ETH1 Transmit Data 0 G PG_02

ETH1_TXD1 ETH1 Transmit Data 1 G PG_03

ETH1_TXEN ETH1 Transmit Enable G PG_01

HADC0_EOC_DOUT HADC0 End of Conversion / Serial Data Out F PF_02

HADC0_MUX0 HADC0 Controls to external multiplexer F PF_05

HADC0_MUX1 HADC0 Controls to external multiplexer F PF_04

HADC0_MUX2 HADC0 Controls to external multiplexer F PF_03