ee FAIRCHILD ee SEMICONDUCTOR 100344 General Description The 100344 contains eight D-type latches, individual inputs (D,), outputs (Q,), a common enable pin (E), latch enable (LE), and output_enable pin (OEN). A Q output follows its D input when both E and LE are LOW. When either E or LE (or both) are HIGH, a latch stores the last valid data present on its D input prior to EorLE going HIGH. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is -2.0V, presenting a high impedance to the data bus. This high impedance re- duces termination power and prevents loss of low state noise margin when several loads share the bus. March 1998 Low Power 8-Bit Latch with Cut-Off Drivers The 100344 outputs are designed to drive a doubly termi- nated 50Q transmission line (25Q load impedance). All in- puts have 50 kQ pull-down resistors. Features Cut-off drivers Drives 25Q load Low power operation 2000V ESD protection Voltage compensated operating range = -4.2V to -5.7V Available to MIL-STD-883 Ordering Code: Logic Symbol Do Dy Dy Dz Dy Ds Dg Dz LE E OEN Qy Q Oy Oz Q Os Og Oy DS009883-4 bod Pin Names Description Do-Dz Data Inputs E Enable Input LE Latch Enable Input OEN Output Enable Input Q,-Qz Data Outputs 1998 Fairchild Semiconductor Corporation Dsoogss3 www fairchildsemi.com SIBALG HO-IND YUM Ydje] HG-8 49MOd MO] PrEOOLConnection Diagrams 24-Pin DIP 24-Pin Quad Cerpak NA Do E LE Vee Yoca Q% yo! 240-03 {jf ft Ds] 2 23-D, 24 23 22 21 20 19 De3 22,Dy D1 18F Q, Dy-4 21FDy Do 42 17 Q oEN-45 20--E D375 16 Q3 Voom] 6 19F-LE Dy4 15 Qy Voca7] 7 18F- Veg 05 . " 05 Voca 8 17 Voc, Dg Og ae iso 7-8 9 10 11 12 7 TrTrire ag] 0 15a D7 OEN Vc Veca Yoca Q7 agli 14 RQ, Ds009883-2 Q4-412 13-03 DS0098s3-1 28-Pin PCC Q; 23 93 Vics Q4 95 Og a) Dy Dg Ds Vers Dy Ds Dg DSo0sss3-3 www fairchildsemi.com 2Logic Diagram Do Dy Da Ds Dg Ds D6 Ele % EE OD EE OD E OD E OD E OD E OD E OD E D rT PF TT Pe DS009883-5 Truth Table Inputs Outputs D, E LE OEN Q, L L L L L H L L L H x H x L Latched (Note 1) x x H L Latched (Note 1) 4 4 x H Cutoff H = HIGH Voltage level L = LOW Voltage level Cutoff = lower-than-LOW state X = Don't Care Note 1: Retains data present before either LE or E go HIGH. www fairchildsemi.comAbsolute Maximum Ratings (note 2) Above which the useful life may be impaired Storage Temperature (Teta) -65C to +150C Maximum Junction Temperature (TJ) Ceramic H175C Plastic +150C Vee Pin Potential to Ground Pin -7.0V to +0.5V Input Voltage (DC) Vee to +0.5V Output Current (DC Output HIGH) -100 mA ESD (Note 3) 22000V Commercial Version DC Electrical Characteristics (note 4) Vee = -4.2V to -5.7V, Voo = Veca = GND, To = 0C to +85C Recommended Operating Conditions Case Temperature (Tg) Commercial 0C to +85C Industrial -40C to +85 Military -55C to +125C Supply Voltage (Vee) -5.7V to -4.2V Note 2: Absolute maximum ratings are those values beyond which the de- vice may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Symbol Parameter Min Typ Max Units Conditions Vou Output HIGH Voltage -1025 -955 -870 mV Vin = Vin (Max) Loading with VoL Output LOW Voltage -1830 -1705 -1620 mV or ViL (Min) 25 to -2.0V Vouc Output HIGH Voltage -1035 mV Vin = Vin (Min) Loading with Voto Output LOW Voltage -1610 mV or Vi_ (Max) 25Q to -2.0V Voiz Cutoff LOW Voltage -1950 mV Vin = Vin (Min) OEN = HIGH or Vi_ (Max) Vin Input HIGH Voltage -1165 -870 mV Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage -1830 -1475 mV Guaranteed LOW Signal for All Inputs lit Input LOW Current 0.50 HA Vin = Vit (Min) lia Input HIGH Current 240 HA Vin = Vin (Max) lee Power Supply Current Inputs Open -178 -85 mA Vee = -4.2V to -4.8V -185 -85 Vee = -4.2V to -5.7V Note 4: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. DIP AC Electrical Characteristics Vee = -4.2V to -5.7V, Veo = Veca = GND Symbol Parameter Toe =oC To = +25C To = +85C Units Conditions Min Max Min Max Min Max teLy Propagation Delay 0.90 2.10 0.90 2.10 1.00 2.30 ns Figures 1, 2 TeHL D, to Output (Note 5) teLy Propagation Delay 1.60 3.10 1.60 3.10 1.80 3.40 ns Figures 1, 4 teu LE, E to Output (Note 5) tpzH Propagation Delay 1.60 4.20 1.60 4.20 1.60 4.20 ns Figures 1, 2 tpuz OEN to Output 1.00 2.70 1.00 2.70 1.00 2.70 (Note 5) tty Transition Time 0.45 2.00 0.45 2.00 0.45 2.00 ns Figures 1, 3 tra 20% to 80%, 80% to 20% ts Setup Time ns Dpo-Dz 1.00 1.00 1.10 Figures 1, 3 ty Hold Time ns Dpo-Dz 0.10 0.10 0.10 Figures 1, 3 tow(H) Pulse Width HIGH ns LE, E 2.00 2.00 2.00 Figures 1, 3 Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. www fairchildsemi.comPCC and Cerpak AC Electrical Characteristics Vee = 4.2V to -5.7V, Voo = Voca = GND Symbol Parameter Te = 0C To = +25C To = +85C Units | Conditions Min Max Min Max Min Max teLy Propagation Delay 0.90 1.90 0.90 1.90 1.00 2.10 ns Figures 1, 2 TeHL D, to Output (Note 7) teLy Propagation Delay 1.60 2.90 1.60 2.90 1.80 3.20 ns Figures 1, 4 tout LE, E to Output (Note 7) tpzH Propagation Delay 1.60 4.00 1.60 4.00 1.60 4.00 ns Figures 1, 2 tpuz OEN to Output 1.00 2.50 1.00 2.50 1.00 2.50 (Note 7) tty Transition Time 0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1, 3 tH 20% to 80%, 80% to 20% ts Setup Time ns Dp-Dz | 0.90 0.90 1.00 Figures 1, 3 ty Hold Time ns Dp-D; | 0.00 0.00 0.00 Figures 1, 3 tow(H) Pulse Width HIGH ns LE, E 2.00 2.00 2.00 Figures 1, 3 tosHL Maximum Skew Common Edge PCC Only Output-to-Output Variation 330 330 330 ps (Note 6) Data to Output Path tosLH Maximum Skew Common Edge PCC Only Output-to-Output Variation 330 330 330 ps (Note 6) Data to Output Path tost Maximum Skew Opposite Edge PCC Only Output-to-Output Variation 330 330 330 ps (Note 6) Data to Output Path tos Maximum Skew PCC Only Pin (Signal) Transition Variation 230 230 230 ps (Note 6) Data to Output Path Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tggy), or LOW to HIGH (tog_y), or in opposite directions both HL and LH (tggq). Parameters togy and tp, guaranteed by design. Note 7: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. www fairchildsemi.comMilitary Version DC Electrical Characteristics Vee = -4.2V to -5.7V, Veo = Veca = GND, Te = -55C to +125C Symbol Parameter Min Max Units Te Conditions Notes Vou Output HIGH Voltage -1025 | -870 mV 0C to +125C 1085 -870 mV -55C Vin = Vin (Max) Loading with (Notes 8, 9, VoL Output LOW Voltage -1830 | -1620 mV 0C to or V,_ (Min) 25Q to -2.0V | 10) +125C -1830 | -1555 mV -55C Vouc Output HIGH Voltage -1035 mV 0C to +125C -1085 mV -55C Vin = Vin (Min) Loading with (Notes 8, 9, Vote | Output LOW Voltage -1610 mV 0C to or Vi_ (Max) 25Q to -2.0V | 10) +125C -1555 mV -55C Voiz Cutoff LOW Voltage -1950 0C to Vin = Vin (MIN) (Notes 8, 9 mV +125C or Vi, (Max) EN = HIGH 10) -1850 -55C Vin Input HIGH Voltage -1165 -870 mV 55C to Guaranteed HIGH Signal (Notes 8, 9, +125C | for All Inputs 10, 11) Vit Input LOW Voltage -1830 | -1475 mV -58C to Guaranteed LOW Signal (Notes 8, 9, +125C | for All Inputs 10, 11) lit Input LOW Current 0.50 HA 55C to Vee = -4.2V (Notes 8, 9, +125C Vin = Vit (Min) 10, 11) lia Input HIGH Current 240 HA 0C to Vee = -5.7V (Notes 8, 9 +125C Vin = Vin (Max) 10) 340 HA -55C lee Power Supply Current -58C to Inputs Open (Notes 8, 9 -195 -65 mA +125C Vee = -4.2V to -4.8V 10) om -205 -65 Vee = -4.2V to -5.7V condition at cold temperatures. AC Electrical Characteristics Vee = -4.2V to -5.7V, Veo = Veca = GND Note 9: Screen tested 100% on each device at -55C, +25C, and +125C, Subgroups 1, 2, 3, 7, and 8. Note 10: Sample tested (Method 5005, Table |) on each manufactured lot at -55C, +25C, and +125C, Subgroups A1, 2, 3, 7, and 8. Note 11: Guaranteed by applying specified input condition and testing Vou/VoL- Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides cold start specs which can be considered a worst case Symbol Parameter To = -55C To = +25C Te = +125C | Units Conditions Notes Min Max Min Max Min Max TeLH Propagation Delay 0.50 2.60 0.70 2.60 0.70 3.10 ns Figures 1, 2 (Notes 12, teu D, to Output 13, 14, 16) teLy Propagation Delay 0.80 3.30 1.00 3.30 1.10 3.80 ns Figures 1, 4 (Notes 12, teu LE, E to Output 13, 14, 16) tezH Propagation Delay 1.00 4.60 1.10 4.20 1.20 4.40 ns Figures 1, 2 (Notes 12, teuz OEN to Output 0.70 3.00 | 0.70 280] 0.70 3.20 13, 14, 16) tH Transition Time 0.40 2.50 0.40 2.40 0.40 2.70 ns Figures 1, 3 trot 20% to 80%, 80% to (Note 15) 20% www fairchildsemi.comAC Electrical Characteristics (Continue Vee = -4.2V to -5.7V, Veo = Veca = GND Symbol Parameter To = -55C To = +25C To = +125C | Units Conditions Notes Min Max Min Max Min Max ts Setup Time . (Note 15) Dp-Dz | 1.50 1.50 1.70 ns Figures 1, 3 th Hold Time . (Note 15) Dp-D; | 0.60 0.60 0.60 ns Figures 1, 3 tow(H Pulse Width HIGH ell) - ; (Note 15) LE,E 2.40 2.40 2.40 ns Figures 1, 3 Note 12: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals 55C), then testing immedi- ately after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Screen tested 100% on each device at +25C temperature only, Subgroup AQ. Sample tested (Method 5005, Table |) on each manufactured lot at +25C, Subgroup AQ, and at +125C and -55C temperatures, Subgroups A10 and A11. Not tested at +25C, +125C, and -55C temperature (design charactenzation data). The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Note 13: Note 14: Note 15: Note 16: Test Circuitry Notes: Voc. Veca = +2V, Veg = -2.5V i" ts L2 SCOPE ti Voc i . PULSE CHAN A wt 1 vt GENERATOR | DF 0.1 uF | 500 PULSE Oh : OEN GENERATOR wt uM . Cie SCOPE D Q rw CHAN B TL 500 = 0.1 uF Vee _ 1 iL PULSE rari = = = Tt GENERATOR wt DSo09883-6 L1 and L2 = equal length 50Q impedance lines Ry = 50Q terminator internal to scope Decoupling 0.1 WF from GND to Voc and Vee All unused outputs are loaded with 250 to GND C, = Fixture and stray capacitance < 3 pF FIGURE 1. AC Test Circuit 7 www fairchildsemi.comSwitching Waveforms DATA x x x i ' i Hl <! agp! 1g pe! tep tpuz tpzy DS008883-7 FIGURE 2. Propagation Delay and Cutoff Times ( \ | 1 I I DS009883-8 FIGURE 3. Setup, Hold and Pulse Width Times OEN Low OUTPUT \ Dso09sEs-9 FIGURE 4. Propagation Delay LE, E to Q www fairchildsemi.com 8Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: Device Type (Basic) Package Code 100344 D GCG QB = Special Variation QB = Military grade device with D = Ceramic DIP F = Quad Cerpak P = Plastic DIP Q = Plastic Leaded Chip Carrier (PCC) Temperature Range CG = Commercial (0C to + 85C) M = Military (~55C to + 125C) DS609883-10 Physical DimeNnSiONS inches (millimeters) unless otherwise noted 1.215 (30.86) 0,025 MAX 0.030 0.055 (0.64) 24 13 (0.76 1.40) FT PLL IP ri iri irl RAD TYP 0.390 (9.91) MAX / Lihat ht Gel he bel Get Get GA hal hel Ol 0.0320.042 5 0.81 1.07) 0.005 GLASS 0.050 0.060 ( 0.4000.430 0.180 2.005 L< 8.050 0.066 <_ [e_.0:400 = 0.430 0.180 (0.13) SEALANT (1271.52) YP 9.015 0.0555, (10.16 10.92) (4.57) MIN TYP (0.38 1.40) Y MAX t : X ) 0.225 f Troy 8 fl __. MAX TYP and f ' 90100 0.008 0.012 TYP (0.20 0.30) 0.425 TYP 0.055 0.090-0.110 | 0.015-0.021 (3.18) 0.435 -0.535 (40) (2.29 2.79) (0.380.53) MIN (11.0513.59) MAX TYP TYP TYP TYP BOTH ENDS 424 (REV J) environmental and burn-in processing 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) Package Number J24E www fairchildsemi.com9.035-0.045 R To.a9-1.14] IN 1.194-1.214 [30.33-30.84] 0.202 24 [5.13] 13 DOO ooo 5 b) 0.337-0.347 [8.56-8.81] u OUOUOUOIOI OU u 12 o 0.125 24-Lead Plastic Dual-In-Line Package (P) PIN NO. 1 IDENT [3.18] 0.125-0.135 4 0.060 0.039 [3.18-3.43] TYP |e 4X | [1.52] [0.99] 0.065 [1.65] 0.145-0.200_| | } [3.68-5.08] 6-44 9.020 iy L__ 0.125-0.140 1, noo Ip [0.51] [3.18-3.56] ! | |___0.047-0.057 0.050 typ [1.19-1.45] [1.27] 0.090-0.110 0.015-0.021 [0.38-0.53] |? [2.29-2.79] TYP Package Number N24E Physical DimensiON$ inches (millimeters) unless otherwise noted (Continued) 0.390-0.410 [9.91-10.41] 90-100 0.380 yin [9.65] +0.040 0.428 10-040 +1.02] 0.009-0.015 [10.87 5 35] [0.23-0.38] N24E (REV A) www fairchildsemi.comPhysical DimMeNnSiONS inches (millimeters) unless otherwise noted (Continued) +0.006 0.450 "hoo +0.15 ee IDENT 450 x 7 04e [1.14] 0.017#0.004 TYP 4 1 26 9.02940.003 ryp [0.43+0.10] a} [0.7440.08] | -| _ []25 a n f + H 0.4100.020 L [10.410.51] L] L] L]19 12 18 SEATING PLANE 1 0.050 typ | ne ja [1.27] | fa 9-020 in Typ 0.300 yyp [0.51] [7.62] 0.10540.015 ago y 0-045 [2.6740.38] [1.14] 0.165-0.180 TYP [4.19-4.57] a 0.490#0.005 [12.4540.13] TYP V2BA (REV K) 28-Lead Plastic Chip Carrier (Q) Package Number V28A aml www fairchildsemi.com100344 Low Power 8-Bit Latch with Cut-Off Drivers Physical DimensiON$ inches (millimeters) unless otherwise noted (Continued) 0.360 ~ 9.250 TYP > PIN ND. 1 N (MOLDED BODY) 0.370 MIN 0.360 TYP 9959 TYP {24 19 111 18 fz __ | 1 _ J 6 3> 7 12 0.018 | 0.075 MAX o.o1g TYP 8 PLCS 0.050 + 0.005 , TYP LIFE SUPPORT POLICY 0.400 MAX ___,,. | TYP GLASS 0.007 * I~ o.o04 TYP 0.050 Pl 01035 -~t 0.085 MAX W248 (REV Di 24-Lead Quad Cerpak (F) Package Number W24B FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, failure to perform when properly used and (c) whose in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. to the user. Fairchild Semiconductor Fairchild Corporation Europe Semiconductor Americas Fax: +49 (0) 1 80-530 85 86 Customer Response Center Tel: 1-888-522-5372 Deutsch English Italy www fairchildsemi.com Email: europe.support@nsc.com Tel: +49 (0) 8 141-35-0 Tel: +44 (0) 1 793-85-68-56 Tel: +39 (0) 2 57 5631 Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, & Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: +852 2737-7200 Fax: +852 2314-0061 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.