1
LTC1694-1
16941fa
SMBus/I
2
C Accelerator*
■
Improves SMBus/I
2
C
TM
Rise Time Transition
■
Ensures Data Integrity with Multiple Devices
on the SMBus/I
2
C
■
Improves Low State Noise Margin
■
Wide Supply Voltage Range: 2.7V to 6V
■
Parallel Multiple LTC1694-1 Devices
for Increased Drive
■
Low Profile (1mm) SOT-23 (ThinSOT
TM
) Package
The LTC
®
1694-1 is a dual SMBus active pull-up designed
to enhance data transmission speed and reliability under
all specified SMBus loading conditions. The LTC1694-1 is
also compatible with the Philips I
2
C Bus.
The LTC1694-1 allows multiple device connections or a
longer, more capacitive interconnect, without compro-
mising slew rates or bus performance, by supplying a high
pull-up current of 2.2mA to slew the SMBus or I
2
C lines
during positive bus transitions
During negative transitions or steady DC levels, the
LTC1694-1 sources zero current. External resistors, one
on each bus line, trigger the LTC1694-1 during positive
bus transitions and set the pull-down current level. These
resistors determine the slew rate during negative bus
transitions and the logic low DC level.
The LTC1694-1 is available in a 5-pin SOT-23 package.
■
Notebook and Palmtop Computers
■
Portable Instruments
■
Battery Chargers
■
Industrial Control Application
■
TV/Video Products
■
ACPI SMBus Interface
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
I
2
C is a trademark of Philips Electronics N.V.
*U.S. Patent No. 6,650,174
VCC = 5V 1µs/DIV 1694-1 TA02
CLD = 200pF
fSMBus = 100kHz
Comparison of SMBus Waveforms for
the LTC1694-1 vs Resistor Pull-Up
LTC1694-1
1V/DIV RPULL-UP
= 15.8k
LTC1694-1
V
CC
GND
V
CC
5V
C1
0.1µF
SMBus1
SMBus2
SCL
SDA
DEVICE 1
CLK
IN
CLK
OUT
SMBus
V
CC
5V
DATA
IN
DATA
OUT
DEVICE N
1694-1 TA01
CLK
IN
R
P2
CLK
OUT
DATA
IN
DATA
OUT
R
P1
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LTC1694-1
16941fa
ABSOLUTE MAXIMUM RATINGS
W
WW
U
PACKAGE/ORDER INFORMATION
W
UU
ORDER PART
NUMBER
LTC1694-1CS5
LTC1694-1IS5
(Note 1)
Supply Voltage (V
CC
) ................................................. 7V
SMBus1, SMBus2 Inputs ............ –0.3V to (V
CC
+ 0.3V)
Operating Ambient Temperature Range
LTC1694-1C ........................................... 0°C to 70°C
LTC1694-1I ....................................... –40°C to 85°C
Junction Temperature........................................... 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.).................300°C
V
CC
1
GND 2
NC 3
5 SMBus1
4 SMBus2
TOP VIEW
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
T
JMAX
= 125°C, θ
JA
= 256°C/W LTHE
LTA9
S5 PART MARKING
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 6V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Supply Voltage Range 2.7 6 V
I
CC
Supply Current SMBus1 = SMBus2 = V
CC
●15 45 80 µA
I
PULL-UP
Pull-Up Current Positive Transition on SMBus ( Figure 1) ●1.0 2.2 mA
Slew Rate = 0.5V/µs, SMBus > V
THRES
V
THRES
Input Threshold Voltage Slew Rate = 0.5V/µs (Figure 1) ●0.4 0.65 0.9 V
SR
THRES
Slew Rate Detector Threshold SMBus > V
THRES
●0.2 0.5 V/µs
t
r
SMBus Rise Time Bus Capacitance = 200pF (Note 2) ●0.32 1.0 µs
Standard Mode I
2
C Bus Rise Time Bus Capacitance = 400pF (Note 3) ●0.30 1.0 µs
f
MAX
SMBus Maximum Operating Frequency (Note 4) ●100 kHz
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The rise time of an SMBus line is calculated from (V
IL(MAX)
–
0.15V) to (V
IH(MIN)
+ 0.15V) or 0.65V to 2.25V. This parameter is
guaranteed by design and not tested. With a minimum initial slew rate of
0.5V/µs, a minimum pull-up current of 1mA and a maximum input
threshold voltage of 0.9V:
Rise Time = [(0.9V – 0.65V)/0.5V/µs] + [(2.25V – 0.9V) • 200pF/1mA]
= 0.77µs
Note 3: The rise time of an I
2
C bus line is calculated from V
IL(MAX)
to
V
IH(MIN)
or 1.5V to 3V (with V
CC
= 5V). This parameter is guaranteed by
design and not tested. With a minimum boosted pull-up current of 1mA:
Rise Time = (3V – 1.5V) • 400pF/1mA = 0.6µs
Note 4: This parameter is guaranteed by design and not tested.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
3
LTC1694-1
16941fa
TYPICAL PERFORMANCE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50
PULL-UP CURRENT (mA)
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00 050 75
1694-1 G01
–25 25 100 125
V
CC
= 6V
V
CC
= 5V
V
CC
= 2.7V
Pull-Up Current
vs SMBus Voltage
TEMPERATURE (°C)
–50
INPUT THRESHOLD VOLTAGE (V)
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40 050 75
1694 G03
–25 25 100 125
V
CC
= 6V
V
CC
= 2.7V
V
CC
= 5V
TEMPERATURE (°C)
–50
SLEW RATE DETECTOR THRESHOLD (V/µs)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0050 75
1694 G04
–25 25 100 125
V
CC
= 6V
V
CC
= 2.7V
V
CC
= 5V
Slew Rate Detector Threshold Standby Mode Supply Current
TEMPERATURE (°C)
–50
SUPPLY CURRENT (µA)
100
1694-1 G05
050
80
70
60
50
40
30
20
10 –25 25 75 125
V
CC
= 6V
V
CC
= 2.7V
V
CC
= 5V
Pull-Up Current
SMBus VOLTAGE (V)
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
035
LT1694 G02
12 467
PULL-UP CURRENT (mA)
V
CC
= 6V
V
CC
= 5V
V
CC
= 2.7V
Input Threshold Voltage
4
LTC1694-1
16941fa
PIN FUNCTIONS
UUU
V
CC
(Pin 1): Power Supply Input. V
CC
can range from 2.7V
to 6V and requires a 0.1µF bypass capacitor to GND.
Supply current is typically 45µA when the SMBus or I
2
C
lines are inactive (SCL and SDA are a logic high level).
GND (Pin 2): Ground.
NC (Pin 3): No Connection.
SMBus2 (Pin 4): Active Pull-Up for SMBus.
SMBus1 (Pin 5): Active Pull-Up for SMBus.
BLOCK DIAGRAM
W
–
+
SLEW RATE
DETECTOR
CONTROL
LOGIC
0.65V
V
REF
VOLTAGE
COMP
2.2mA
CHANNEL ONE
CHANNEL TWO
(DUPLICATE OF CHANNEL ONE)
1694-1 BD
1
V
CC
5
SMBus1
SMBus2
2
GND
4
TEST CIRCUITS
Figure 1
LTC1694-1
V
CC
GND
V
CC
5V
C1
0.1µF
SMBus1
SMBus2
5
4
HP5082-2080
TEST RAMP VOLTAGE
BSS284
V
R
1k
–10V
1694-1 F01a
–
+
LT
®
1360
V
CC
5V
200µA
PULL-UP =
2.2mA (TYP)
200µA
(TYP)
TEST RAMP
VOLTAGE
0µA
VCC
1694-1 F01b
0.5V/µs
0V
VTHRES
IPULL-UP = VR
1kΩ
5
LTC1694-1
16941fa
APPLICATIONS INFORMATION
WUUU
SMBus Overview
SMBus communication protocol employs open-drain
drives with resistive or current source pull-ups. This pro-
tocol allows multiple devices to drive and monitor the bus
without bus contention. The simplicity of resistive or fixed
current source pull-ups is offset by the slow rise times
resulting when bus capacitance is high. Rise times can be
improved by using lower pull-up resistor values or higher
fixed current source values, but the additional current
increases the low state bus voltage, decreasing noise
margins. Slow rise times can seriously impact data reli-
ability, enforcing a maximum practical bus speed well
below the established SMBus maximum transmission rate.
Theory of Operation
The LTC1694-1 overcomes these limitations by providing
a 2.2mA pull-up current only during positive bus transi-
tions to quickly slew any bus capacitance. Therefore, rise
time is dramatically improved, especially with maximum
SMBus loading conditions.
The LTC1694-1 has separate but identical circuitry for
each SMBus output pin. The circuitry consists of a positive
edge slew rate detector and a voltage comparator.
The 2.2mA pull-up current is only turned on if the voltage
on the SMBus line voltage is greater than the 0.65V
comparator threshold voltage and the positive slew rate of
the SMBus line is greater than the 0.2V/µs threshold of the
slew rate detector. The pull-up current remains on until the
voltage on the SMBus line is within 0.5V of V
CC
and/or the
slew rate drops below 0.2V/µs.
Selecting the Values of R
S
and R
P
An external pull-up resistor R
P
is required in each SMBus
line to supply a steady state pull-up current if the SMBus
is at logic zero. This pull-up current is used for slewing the
SMBus line during the initial portion of the positive transi-
tion in order to activate the LTC1694-1 2.2mA pull-up
current.
Using an external R
P
to supply the steady state pull-up
current permits the user the freedom to adjust rise time
versus fall time as well as defining the low state logic level
(V
OL
).
For I/O stage protection from ESD and high voltage spikes
on the SMBus, a series resistor R
S
(Figure 2) is sometimes
added to the open-drain driver of the bus agents. This is
especially common in SMBus-controlled smart batteries.
Both the values of R
P
and R
S
must be chosen carefully to
meet the low state noise margin and all timing require-
ments of the SMBus.
A discussion of the electrical parameters affected by the
values of R
S
and R
P
, as well as a general procedure for
selecting the values of R
S
and R
P
follows.
Figure 2
V
CC
R
S
C
BUS
SMBus
R
ON
1694-1 F02
DATA
IN
DATA
OUT
R
P
Low State Noise Margin
A low value of V
OL
, the low state logic level, is desired for
good noise margin. V
OL
is calculated as follows:
V
OL
= (R
L
• V
CC
)/(R
L
+ R
P
) (1)
R
L
is the series sum of R
S
and R
ON
, the on-resistance of
the open-drain driver.
Increasing the value of R
P
decreases the value of V
OL
.
Increasing R
L
increases the value of V
OL
.
Initial Slew Rate
The initial slew rate, SR, of the Bus is determined by:
SR = (V
CC
– V
OL
)/(R
P
• C
BUS
) (2)
SR must be greater than SR
THRES
, the LTC1694-1 slew
rate detector threshold (0.5/µs max) in order to activate
the 2.2mA pull-up current.
6
LTC1694-1
16941fa
APPLICATIONS INFORMATION
WUUU
SMBus Rise Time
Rise time of an SMBus line is derived using equations 3,
4 and 5.
t
r
= t
1
+ t
2
(3)
t
1
= –R
P
• C
BUS
• ln[(V
THRES
– V
CC
)/
(V
ILMAX
– 0.15 – V
CC
)] (4)
if (V
ILMAX
– 0.15) > V
THRES
, then t
1
= 0µs.
t
2
= –R
P
• C
BUS
• ln{[V
IHMIN
+ 0.15 – V
CC
–
(R
P
• I
PULL-UP
)]/[V
THRES
– V
CC
– (R
P
• I
PULL-UP
)]} (5)
By ignoring the current through R
P
, a simplified version
of equation 3 is obtained:
t
2
= (V
IHMIN
+ 0.15 – V
THRES
) • C
BUS
/I
PULL-UP
(6)
For an SMBus system, V
ILMAX
= 0.8V and V
IHMIN
= 2.1V.
For the LTC1694-1, typically V
THRES
= 0.65V and I
PULL-UP
= 2.2mA.
C
BUS
is the total capacitance of the SMBus line.
Increasing the value of R
P
increases the rise time.
SMBus Fall Time
Fall time of an SMBus line is derived using equation 7:
t
f
= R
T
• C
BUS
• ln{[0.9 • (R
P
+ R
L
) – R
L
]/
[(V
ILMAX
– 0.15) • (R
P
+ R
L
)/V
CC
– R
L
]} (7)
where R
T
is the parallel equivalent of R
P
and R
L
.
The rise and fall time calculation for an I
2
C system is as
follows.
I
2
C Bus Rise and Fall Time
Rise time of an I
2
C line is derived using equation 8.
t
r
= –R
P
• C
BUS
• ln{[V
IHMIN
– V
CC
– (R
P
• I
PULL-UP
)]/
[V
ILMAX
– V
CC
– (R
P
• I
PULL-UP
)]} (8)
Fall time of an I
2
C line is derived using equation 9:
t
f
= R
T
• C
BUS
• ln{[(V
IHMIN
/V
CC
) • (R
P
+ R
L
) – R
L
]/
[(V
ILMAX
/V
CC
) • (R
P
+ R
L
) – R
L
]} (9)
For an I
2
C system with fixed input levels, V
ILMAX
= 1.5V
and V
IHMIN
= 3V.
For an I
2
C system with V
CC
related input levels, V
ILMAX
=
0.3V
CC
and V
IHMIN
= 0.7V
CC
.
C
BUS
is the total capacitance of the I
2
C line.
A general procedure for selecting R
P
and R
L
is as follows:
1. R
L
is first selected based on the I/O protection require-
ment. Generally, an R
S
of 100Ω is sufficient for high
voltage spike and ESD protection. R
ON
is determined by
the size of the open-drain driver, a large driver will have
a lower R
ON
.
2. Next, the value of R
P
is determined based on the rise and
fall time requirements using equations 3 to 7 (for an
SMBus system) or 8 and 9 (for an I
2
C system). The
value chosen for R
P
must ensure that both the rise and
fall time specifications are met simultaneously.
3. After R
P
and R
L
are selected, use equations 1 and 2 to
check if the V
OL
and SR requirements are fulfilled.
If SR is too low, decrease the value of R
P
. If V
OL
is too high,
increase the value of R
P
.
SMBus Design Example
Given the following conditions and requirements:
V
CC
= 3.3V nom
V
OL
= 0.4V max
C
BUS
= 200pF max
V
ILMAX
= 0.8V, V
IHMIN
= 2.1V
t
r
= 0.8µs max, t
f
= 0.3µs max
If an R
S
of 500Ω is used and the max R
ON
of the driver
is 200Ω, then R
L
= 500 + 200 = 700Ω. Using the max
V
THRES
of 0.9V and a min I
PULL-UP
of 1mA.
Using equation 6 to calculate the approximate value of t
2
:
t
2
= (2.1 + 0.15 – 0.9) • [(200 • 10
–12
)/(1 • 10
–3
)]
= 0.27µs
t
1
= 0.8 – 0.27 = 0.53µs
Using equation 4 to find the required R
P
to meet t
r
:
R
P
= –t
1
/{C
BUS
• ln[(V
THRES
– V
CC
)/
(V
ILMAX
– 0.15 – V
CC
)]} = 27k
R
T
= (R
P
• R
L
)/(R
P
+ R
L
)
7
LTC1694-1
16941fa
APPLICATIONS INFORMATION
WUUU
LTC1694-1
V
CC
GND
V
CC
5V
C1
0.1µF
SMBus1
SMBus2
1
2
5
4
LTC1694-1
V
CC
GND
SMBus1
SMBus2
5
4
1
2
SCL
SDA
DEVICE 1
CLK
IN
CLK
OUT
SMBus
DATA
IN
DATA
OUT
DEVICE N
1694-1 f03
CLK
IN
R
P2
CLK
OUT
DATA
IN
DATA
OUT
R
P1
Figure 3. Paralleling Two LTC1694-1 to Provide 4.4mA of Pull-Up Current
Using equations 4 and 5 to check exact value of t
r
:
t
r
= 0.535µs + 0.254µs = 0.79µs
Using equation 7 to check t
f
:
t
f
= 0.222µs
which is less than 0.3µs.
Using equation 1 to check V
OL
:
V
OL
= (3.3 • 700)/[700 + (27 • 10
3
)] = 83mV
which is less than 0.4V.
And using equation 2 to check the initial slew rate:
SR = 3.3/[(27 • 10
3
) • (200 • 10
–12
)] = 0.61V/µs
which is greater than 0.5V/µs.
Therefore, the value of R
P
chosen is 27k.
ACK Data Setup Time
Care must be taken in selecting the value of R
S
(in series
with the pull-down driver) to ensure that the data setup
time requirement for ACK (acknowledge) is fulfilled. An
acknowledge is accomplished by the SMBus host releas-
ing the SDA line (pulling high) at the end of the last bit sent
and the SMBus slave device pulling the SDA line low
before the rising edge of the ACK clock pulse.
The LTC1694-1 2.2mA pull-up current is activated when
the SMBus host releases the SDA line, allowing the
voltage to rise above the LTC1694-1’s comparator thresh-
old of 0.65V. If an SMBus slave device has a high value
of R
S
, a longer time is required for this SMBus slave
device to pull SDA low before the rising edge of the ACK
clock pulse.
To ensure sufficient data setup time for ACK, SMBus slave
devices with high values of R
S
, should pull the SDA low
earlier. Typically, a minimum setup time of 1.5µs is needed
for an SMBus device with an R
S
of 700Ω and a bus
capacitance of 200pF.
An alternative is that the SMBus slave device can hold SCL
line low until the SDA line reaches a stable state. Then, SCL
can be released to generate the ACK clock pulse.
Connecting Multiple LTC1694-1 in Parallel
The LTC1694-1 is designed to guarantee a maximum
SMBus rise time of 1µs with a bus capacitance of 200pF.
In some cases where the bus capacitance is higher than
200pF, multiple LTC1694-1s can be connected in parallel
to provide a higher pull-up current to meet the rise time
requirement. Figure 3 shows a typical application with two
LTC1694-1s connected in parallel to supply a pull-up
current of 4.4mA.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
8
LTC1694-1
16941fa
LT/TP 0304 REV A 1K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1999
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
APPLICATIONS INFORMATION
WUUU
VCC = 5V 1µs/DIV
CLD = 200pF
fSMBus = 100kHz 1694 TA03
VCC = 3.3V 1µs/DIV
CLD = 200pF
fSMBus = 100kHz 1694 TA04
Comparison of SMBus Waveforms for the LTC1694-1 vs Resistor Pull-Up
RPULL-UP
= 15.8k
LTC1694-1
1V/DIV LTC1694-1
1V/DIV RPULL-UP
= 10.5k
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1380/LTC1393 8-Channel/4-Channel Analog Multiplexer with SMBus interface Low R
ON
and Low Charge Injection
LTC1427 10-Bit Current DAC with SMBus Interface 50µA Full-Scale Current
LTC1623 Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16 Channel Capability
LTC1663 SMBus Interface 10-Bit Rail-to-Rail Micropower DAC DNL < 0.75LSB Max, 5-Lead SOT-23 Package
LTC1694 SMBus Accelerator Includes DC and AC Pull-Up Current
LT1786F SMBus-Controlled CCFL Switching Regulator 1.25A, 200kHz, Floating or Grounded Lamp Configurations
LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffers Provides Capacitance Buffering, SDA and SCL Hot
Swapping, Level Shifting
PACKAGE DESCRIPTION
U
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S5 TSOT-23 0302
PIN ONE
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
3.85 MAX
0.62
MAX 0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
