This is information on a product in full production.
January 2015 DocID025099 Rev 2 1/25
STEF033
Electronic fuse for 3.3 V line
Datasheet
-
production data
Features
•Continuous current typ.: 3.6 A (DFN), 2.5 A
(Flip Chip)
•N-channel on resistance (typ): 40 m (DFN),
25 m (Flip Chip)
•Enable/Fault functions
•Output clamp voltage (typ): 4.5 V
•Undervoltage lockout
•Short-circuit limit
•Overload current limit
•Controlled output voltage ramp
•Thermal latch (typ): 160 °C
•Uses tiny capacitors
•Latching and auto-retry versions
•Operative junction temp. - 40 °C to 125 °C
•Available in DFN10 3x3 and Flip Chip 9 bumps
Applications
•Hard disk driv es
•Solid state drives (SSD)
•Hard disk and SSD arrays
•Computer
•DVD and Blu-Ray disc drivers
Description
The STEF033 is an integrated electronic fuse
optimized for monitoring output current and the
input voltage. Connected in series to the 3.3 V
rail, it is able to protect the electronic circuitry on
its output from overcurrent and overvoltage. The
STEF033 has controlled delay and turn-on time.
When an overload condition occurs, the device
limits the output current to a predefined safe
valu e. If the anomalous overl oad co ndi tio n
persists, it goes into an open state, disconnecting
the load from the power supply. If a continuous
short-circuit is present on the board, when the
power is re-applied the E-fuse initially limits the
output current to a safe value and then goes
again into the open state. The voltage clamping
circuit prevents the output voltage from exceeding
a fixed value, if the input voltage goes beyond this
threshold. The device is equipped with a thermal
protection circuit. Intervention of thermal
protection is signaled to the board-monitoring
circuits through an appropriate signal on the Fault
pin. Unlike mechanical fuses, which must be
physically replaced after a single event, the E-
fuse does not degrade in its performances
following short-circuit/thermal protecti on
intervention and is reset either by re-cycling the
supply voltage or using the appropriate Enable
pin. The STEF033 is also available in an auto-
retry version; in case of thermal fault it
automatically attempts to re-apply power to the
load when the die temperature returns to a safe
value.
DFN10 (3 x 3 mm) Flip Chip 9
www.st.com
Contents STEF033
2/25 DocID025099 Rev 2
Contents
1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Operat ing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.1 Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.2 Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.3 Output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.4 Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.5 Thermal shutdown and Auto-retry function . . . . . . . . . . . . . . . . . . . . . . 10
5.2 R
Limit
calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 C
dv/dt
calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.4 Enable-Fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 DFN10 (3 x 3 mm) pa ckage informati on . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2 QFNxx/DFNxx (3x3 mm) packing information . . . . . . . . . . . . . . . . . . . . . 20
7.3 Flip Chip 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DocID025099 Rev 2 3/25
STEF033 Device block diagram
25
1 Device block diagram
Figure 1. STEF033 block diagram
Pin configuration STEF033
4/25 DocID025099 Rev 2
2 Pin configuration
Figure 2. Pin configuration (top view)
Table 1. Pin description
Pin n°
(DFN) Pin n°
(Flip Chip) Symbol Note
1,2,3,4,5 C1,C2,C3 V
OUT
/Source Connected to the source of the internal power MOSFET and to the
output terminal of the fuse
6 N.C. I-lim - A resistor between these two pins sets the overload and short-circuit
current limit levels. On the Flip Chip the resistor must be connected
between the I-Lim+ and Source pins
7A1I-lim +
8A2En/Fault
The Enable/F ault pin is a tri-st ate, bi -direct ional in terf ace. Durin g normal
operation the pin must be left floating, or it can be used to disable the
output of the device by pulling it to ground using an open drain or open
collector device. If a thermal fault occurs, the voltage on this pin goes
into an intermediate state to signal a monitor circuit that the device is in
therma l shutd own. It can be conn ected to anot her devi ce of this fami ly to
cause a simultaneous shutdown during thermal events.
9N.C.dv/dt
The internal dv/dt circuit controls the slew rate of the output voltage at
turn-on. The internal capacitor allows a ramp-up time of around 1.4 ms.
An external c apaci tor can be add ed to this pin to increase the ramp time .
If an additional capacitor is not required, this pin should be left open.
This feature is not available on the Flip Chip version.
10 A3 GND Ground pin
Exposed
pad B1,B2,B3 V
CC
Exposed pad. Positive input voltage must be connected to V
CC
.
DocID025099 Rev 2 5/25
STEF033 Maximum ratings
25
3 Maximum ratings
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
Positive power supply voltage - 0.3 to 10 V
V
OUT
/source V
OUT
pin voltage - 0.3 to 7 V
V
OUT
pin voltage (100 ms) - 0.3 to Vcc+0.3
I-Lim+/I-Lim- Current limit pin voltage -0.3 to 7 V
Current limit pin voltage (100 ms) - 0.3 to V
CC
+0.3
En/Faul t Enable/ Fault pi n voltage - 0.3 to 4.6 V
dv/dt dv/dt pin voltage - 0.3 to 4.6 V
T
OP
Operating junction temperature range
(1)
1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at
temperatures greater than the maximum ratings for extended periods of time.
- 40 to 125 °C
T
STG
Storage temperature range - 65 to 150 °C
T
LEAD
Lead temperature (soldering) 10 sec 260 °C
Table 3. Recommended operating condition
Symbol Parameter Value Unit
V
CC
Positive power supply voltage 3.1 to 8 V
R-limit Current limitation resistor range, STEF033, STEF033A 10 to 120 Ω
Current limitation resistor range, STEF033J, STEF033JA 15 to 120
C
dv/dt
Soft-start capacitor range 0 to 1 nF
V
EN
Enable/ Fault pi n voltage 0 to 3.6 V
Table 4. Thermal data
Symbol Parameter Value Unit
R
thJA
Thermal resistance jun cti on -ambie nt, DF N10 70
°C/WThermal resistance jun cti on -ambie nt, Flip Chip 90
R
thJC
Thermal resistance junction-case, DFN10 34
Maximum ratings STEF033
6/25 DocID025099 Rev 2
Table 5. ESD performance
Symbol Parameter Test conditions Value Unit
ESD ESD protection
HBM 4 kV
MM 400 V
CDM (DFN10) 500 V
CDM (Flip Chip) 250 V
DocID025099 Rev 2 7/25
STEF033 Electrical Characteristics
25
4 Electrical Characteristics
V
CC
= 3.3 V, C
I
= 10 µF, C
O
=10 µF, T
J
= 25°C (unless otherwise specified)
Table 6. Electrical characteristics for STEF033
Symbol Parameter Test conditions Min. Typ. Max. Unit
Under/Over Voltage Protection
V
Clamp
Output clamping voltage V
CC
= 8 V 4 4.5 5 V
V
UVLO
Under voltage Lockout Turn-on, voltage increasing 2.15 2.35 2.5 V
V
Hyst
UVLO hysteresis 0.1 V
Power MOSFET
t
dly
Delay time Enabling of chip to V
OUT
=10%
of nominal value. 500 µs
R
DSon
ON resistance (DFN package)
(1)
I
OUT
= 500 mA, T
J
= 25°C 40 60 mΩ
I
OUT
= 500 mA,
-40°C<T
J
<125°C 70
ON resistanc e
(Flip Chip package)
(1)
I
OUT
= 500 mA, T
J
= 25°C 30 50 mΩ
I
OUT
= 500 mA,
-40°C<T
J
<125°C 70
V
OFF
Off State output voltage V
EN
=GND, R
L
=infinite 100 mV
I
D
Continuous current DFN package 3.6 A
Flip Chip pa ckage 2.5
Current limit
I
Short
Short-circuit current limit R
Limit
= 24 Ω11.351.75A
I
Lim
Overload current limit R
Limit
= 24 Ω
(2)
2.5 A
dv/d t circu it
dv/dt Output voltage ramp time V
OUT
= 10% to 90 % of nominal
voltage, No C
dv/dt
0.8 1.4 2.5 ms
Enable/Fault
V
IL
Low level input voltage Output disabled,
(2)
0.5 V
V
I(INT)
Intermedi ate lev el input vol tage Thermal fa ult , outp ut di sa bled
(2)
0.8 1.4 2 V
V
IH
High level input voltage Output enabled 2.5 V
V
I(MAX)
High state maximum voltage 3.25 V
I
IL
Low level input current (sink) V
Enable
= GND -28 -50 µ A
Maximum fan-out for fault signal Total number of chips that can
be connected to this pin for
simultaneous shutdown
(2)
3Units
Electrical Characteristics STEF033
8/25 DocID025099 Rev 2
Total device
I
Bias
Bias current
Device operational 0.6 2
mA
Thermal shutdown (only on
latching versions)
(2)
0.5
Device disabled (V
EN
= GND) 0.35
Thermal latch
TSD Shutdown temperature
(2)
160 °C
Hysteresis Only on auto-retry versions
(2)
25
1. Pulse test
2. Guaranteed by design, but not tested in production
Table 6. Electrical characteristics for STEF033 (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DocID025099 Rev 2 9/25
STEF033 Typical application
25
5 Typical application
Figure 3. Application circuit, STEF033 and STEF033A (DFN10 package)
Figure 4. Application circuit with Kelvin current sensing, STEF033J and STEF033JA
(Flip Chip 9 bump package)
5.1 Operating modes
5.1.1 Turn-on
When the input voltage is applied, the Enable/Fault pin goes up to the high state, enabling
the internal control circuitry.
After an initial delay time of typically 500 ms, the output voltage is supplied with a slope
defined by the internal dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the
total time from the Enable signal going high and the output voltage reaching the nominal
value is around 1.6 ms (refer to Figure 5, and Figure 15).
Typical application STEF033
10/25 DocID025099 Rev 2
5.1.2 Normal operating condition
The STEF033 E-fuse behaves like a mechanical fuse, buffering the circuitry on its output
with the same voltage shown at its input, with a small voltage fall due to the N-channel
MOSFET R
DSOn
.
5.1.3 Output voltage clamp
This internal protection circuit clamps the output voltage to a maximum safe value, typically
4.5 V, if the input voltage exceeds this threshold.
5.1.4 Current limiting
When an overload event occurs, the current limiting circuit reduces the conductivity of the
power MOSFET, in order to clamp the output current at the value selected externally by
means of the limiting resistor R
Limit
(Figure 3).
5.1. 5 Thermal shutdown and Auto-r etry function
If the device temperature exceeds the thermal latch threshold, typically 160 °C, the thermal
shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault
pin of the device is automatically set to an intermediate voltage, in order to signal the
overtemperature event.
The STEF033 latch version can be reset from this condition either by cycling the supply
voltage or by pulling down the EN pin below the V
il
threshold and then releasing it.
On the STEF033A auto-retry version, the power MOSFET will remain in an OFF state until
the die temperature drops below the hysteresis value. Once this happens, the internal auto-
retry circuit attempts to reset the device, pulling up the EN/Fault pin to the operative value.
5.2 R
Limit
calculation
As shown in Figure 1 the device uses an internal N-channel Sense FET with a fixed ratio, to
monitor the output current and limit it at the level set by the user.
The R
Limit
value for achieving the requested current limitation can be estimated by using the
“Current limit vs R
Limit
”, graph in Figure 12.
The device has two levels of current limitation, depending on the load condition.
The short-circuit current limit (I
Short
) is the current level that is imposed when the output
voltage decreases sharply, as in the case of a short-circuit on the output.
The overload current limit (I
Lim
), also described as “Current limi t trip-point”, represents the
current level that is recognized by the device as an overload condition. Following this, the
current limit trip point is reached the device enters into current limitation, and the current to
the load is limited to the I
Short
value, which is generally lower than the trip-point value.
The ov er lo a d cur re n t li mi t ( I
Lim
) is dependent on the device reaction time, so it is influenced
by the load current slew-rate. The faster the current increase, the higher the current limit trip
point.
DocID025099 Rev 2 11/25
STEF033 Typical application
25
5.3 C
dv/dt
calculation
The device includes a rise-time control circuit, allowing the soft-start during turn-on and Hot-
plug of the equipment. The pre-programmed rise time, defined as the time interval during
which the output voltage goes from 10% to 90% of the nominal voltage, is typically 1.4 ms.
The STEF033 and STEF033A in DFN10 package feature a user-programmable output
voltage ramp-up time; by connecting a capacitor between the C
dv/dt
pin and GND,
modification of the output voltage ramp-up time is possible. The capacitance to be added on
the C
dv/dt
pin can be selected using the following table.
Figure 5. Delay time and V
OUT
rise time
5.4 Enable-Fault pin
The Enable/Fault pin has the dual function of controlling the output of the device and, at the
same time, of providing information about the device status to the application.
It can be connected to an external open-drain or open-collector device. In this case, when it
is pulled at low logic level, it will turn the output of the E-Fuse off.
If this pin is left floating, since it has internal pull-up circuitry, the output of the E-Fuse is kept
ON in normal operating conditions.
This pin should never be biased to a voltage higher than 3.6 V.
In case of thermal fault, the pin is pulled to an intermediate st ate (Figure 6). This signal can
be pr ovided to a monit or cir cuit, signal ing that a therm al shut dow n has occur red, or it can be
Table 7. Typical rise time values vs. dv/dt capacitor
C
dv/dt
none 100 pF 470 pF 1 nF
Rise Time
(1)
[ms]
1. V
CC
= 3.3 V, C
IN
= 10 µF, C
OUT
= 10 µF, R
LIMIT
= 24 Ω, I
OUT
= 1 A
1.4 2.8 8 16
10%
90%
rise
time
delay
time
Enable
V
OUT
Typical application STEF033
12/25 DocID025099 Rev 2
directly connected to the Enable/Fault pins of other STEFxx devices on the same
application, in order to achieve a simultaneous enable/disable feature.
When a thermal fault occurs, the device can be reset either by cycling the supply voltage or
by pulling down the Enable pin below the V
il
threshold and then releasing it.
Figure 6. Enable/Fault pin status
AM17209v1
EN/Fault voltage [V]
time
0
1
2
3
4
5
Normal operating condition
Thermal fault condition
Off/Reset
DocID025099 Rev 2 13/25
STEF033 Typical performance characteristics
25
6 Typical performance characteristics
The following plots are referred to the typical application circuit and, unless otherwise noted,
at T
A
= 25 °C.
Figure 7. Clamping voltage vs. temperature Figure 8. Short-circuit current vs. temperature
Figure 9. Bias current vs. temperature (device
operational) Figure 10. Bias current vs. temperature (device
disabled)
Figure 11. ON resistance vs. temperature Figure 12. Current limit vs. R
Limit
(
I
OUT
ramp
)
AM17210v1
0
1
2
3
4
5
6
7
8
-40 -25 0 25 55 85 125
Vclamp [V]
Temperature [ºC]
V
CC
= 6 V
AM17211v1
0
0.5
1
1.5
2
2.5
3
-40 -25 0 25 55 85 125
Ishort [A]
Temperature [°C]
V
CC
= 3.3 V, R-limit = 24 Ω
AM17212v1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-40 -25 0 25 55 85 125
Ibias [μA]
Temperature [°C]
Vcc = 3.3 V, V
EN
= floating
AM17213v1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-40 -25 0 25 55 85 125
Ibias [μA]
Temperature [°C]
Vcc = 3.3 V, V
EN
= G ND
AM17214v1
0
10
20
30
40
50
60
70
-40 -20 0 20 40 60 80 100 120 140
RDS -ON [mΩ]
Temperature (°C)
Iout 500 mA
Iout 1 A
Iout 2 A
Iout 4 A
Vcc = 3.3 V, R- limit = 5 Ω
AM17215v1
0
1
2
3
4
5
6
0 20 40 60 80 100 120 140
Limit & Short Current (A)
External Sensing Resistor (Ω)
ISHORT
ILIMIT
Typical performance characteristics STEF033
14/25 DocID025099 Rev 2
Figure 13. V
OUT
ramp-up vs. enable
V
CC
= 3,3 V, I
OUT
= 1 A, C
IN
= C
OUT
= 10 µF, R
Limit
= 24 ,
NO C
dv/dt
Figure 14. V
OUT
ramp-up vs. enable
V
CC
= 3.3 V, I
OUT
= 1 A, C
IN
= C
OUT
= 10 µF, R
Limit
= 24 ,
C
dv/dt
= 470 pF
Figure 15. V
OUT
turn-on vs. enable
V
CC
= 3.3 V, C
IN
= C
OUT
= 10 µF, R
Limit
= 24 , NO C
dv/dt
,
I
OUT
= 1 A, Enable from GND to Floating
Figure 16. V
OUT
turn-off vs. enable
V
CC
= 3.3 V, C
IN
= C
OUT
= 10 µF, R
Limit
= 24 , NO C
dv/dt
,
I
OUT
= 1 A, Enable from Floating to GND
Figure 17. Star tup (slow rising)
V
CC
= from 0 to 3.3 V, C
IN
= C
OUT
= 10 µF, R
Limit
= 24 , NO
C
dv/dt
, I
OUT
= 1 A
Figure 18. Startup and voltage clam
V
CC
= from 0 to 6 V, C
IN
= C
OUT
= 10 µF, R
Limit
= 24 , NO
C
dv/dt
, I
OUT
= 1 A
DocID025099 Rev 2 15/25
STEF033 Typical performance characteristics
25
Figure 19. Thermal latch from 2 A load to short-
circuit
V
CC
= from 0 to 3.3 V, C
IN
= C
OUT
= 10 µF, R
Limit
= 24 , NO
C
dv/dt
, I
OUT
= 1 A
Figure 20. Startup into output short-circuit
V
CC
= from 0 to 3.3 V, C
IN
= C
OUT
= 10 µF, R
Limit
= 24 ,
V
OUT
short to GND
Figure 21. Voltage clamp
V
CC
= from 3.3 to 6 V, C
IN
= C
OUT
=10 µF, R
Limit
= 24 ,
I
OUT
= 1 A
Figure 22. Trip and short current (I
OUT
ramp)
V
CC
= from 0 to 3.3 V, C
IN
= C
OUT
= 10 µF, R
Limit
= 24
Package information STEF033
16/25 DocID025099 Rev 2
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at:
www.st.com
.
ECOPACK
®
is an ST trademark.
DocID025099 Rev 2 17/25
STEF033 Package information
25
7.1 DFN10 (3 x 3 mm) package information
Figure 23. DFN10 (3 x 3 mm) outline
Package information STEF033
18/25 DocID025099 Rev 2
Table 8. DFN10 (3 x 3 mm) mechanical data
Dim. mm.
Typ Min. Max.
A 0.90 0.80 1.00
A1 0.02 00.5
A2 0.70
A3 0.20
b 0.23 0.18 0.30
D 3.00 2.85 3.15
D2 2.38 2.23 2.50
E 3.00 2.85 3.15
E2 1.64 1.49 1.75
E3 0.230
E4 0.365
e0.50
L 0.40 0.30 0.50
ddd 0.08
DocID025099 Rev 2 19/25
STEF033 Package information
25
Figure 24. DFN10 (3 x 3 mm) recommended footprint
Package information STEF033
20/25 DocID025099 Rev 2
7.2 QFNxx/DFNxx (3x3 mm) packing information
Figure 25. QFNxx/DFNxx (3x3 mm) tape and reel outline
Table 9. QFNxx/DFNxx (3x3 mm) tape and reel mechanical data
Dim. mm.
Min. Typ. Max.
A330
C12.8 13.2
D20.2
N60
T18.4
Ao 3.3
Bo 3.3
Ko 1.1
Po 4
P8
DocID025099 Rev 2 21/25
STEF033 Package information
25
7.3 Flip Chip 9 package information
Figure 26. Flip Chip 9 package outline
7504895_K
Package information STEF033
22/25 DocID025099 Rev 2
Figure 27. Flip Chip 9 recommended footprint (dimensions in mm.)
Table 10. Flip Chip 9 mechanical data
Dim. mm.
Min. Typ. Max.
A 0.50 0.55 0.60
A1 0.17 0.20 0.23
A2 0.33 0.35 0.37
b 0.23 0.25 0.29
D 1.16 1.19 1.22
D1 0.8
E 1.16 1.19 1.22
E1 0.8
e0.40
f0.195
ccc 0.075
DocID025099 Rev 2 23/25
STEF033 Order codes
25
8 Order codes
Table 11. Order codes
Tape and reel Package Version Marking
STEF033PUR DFN Latch EF03
STEF033JR
(1)
1. Available on request.
Flip Chip 9 Latch 33
STEF033APUR DFN Auto-retry EF03A
STEF033AJR
(1)
Flip Chip 9 Auto-retry 3A
Revision history STEF033
24/25 DocID025099 Rev 2
9 Revision history
Table 12. Document revision history
Date Revision Changes
06-Aug-2013 1 Initial release.
28-Jan-2015 2
Updated features in cover page, Figure 2: Pin configuration (top
view), Table 1: Pin descri pti on , Table 4: Thermal data, Table 5: ESD
performance, Table 6: Electrical characteristics for STEF033 and
Section 7: Package information.
Minor text chan ges .
DocID025099 Rev 2 25/25
STEF033
25
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