CS5342 105 dB, 192 kHz, Multi-bit Audio A/D Converter Features General Description Advanced Multi-bit Delta-Sigma Architecture The CS5342 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analogto-digital conversion and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 200 kHz per channel. 24-bit Conversion Supports All Audio Sample Rates Including 192 kHz The CS5342 uses a 5th-order, multi-bit Delta-Sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. 105 dB Dynamic Range at 5 V -98 dB THD+N 90 mW Power Consumption High-Pass Filter to Remove DC Offsets Analog/Digital Core Supplies from 3.3 V to 5 V Supports Logic Levels between 2.5 V and 5 V The CS5342 is available in a 16-pin TSSOP package in Commercial grade (-10 to 70 C). The CDB5342 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to "Ordering Information" on page 21 for complete ordering information. The CS5342 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as set-top boxes, DVD-karaoke players, DVD recorders, A/V receivers, and automotive applications. Low-Latency Digital Filter Auto-detect Mode Selection in Slave Mode Auto-Detect MCLK Divider Supports 384x MCLK/LRCK Ratios VA 3.3 V to 5 V Single-Ended Analog Input AINL VD 3.3 V to 5 V Switch-Cap ADC VL 2.5 V to 5 V Auto-detect MCLK Divider Low-Latency Digital Filters /1.5 Master Clock FILT+ Serial Port High-Pass Filter Internal Reference Voltages VQ SCLK Slave Mode Auto-detect LRCK SDOUT M0 M1 Single-Ended Analog Input AINR Switch-Cap ADC http://www.cirrus.com High-Pass Filter Low-Latency Digital Filters Copyright (c) Cirrus Logic, Inc. 2006 (All Rights Reserved) Mode Configuration Reset APRIL '06 DS608F1 CS5342 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4 SPECIFIED OPERATING CONDITIONS ............................................................................................... 4 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 4 ANALOG CHARACTERISTICS (CS5342-CZZ) ..................................................................................... 5 DIGITAL FILTER CHARACTERISTICS ................................................................................................. 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 9 DIGITAL CHARACTERISTICS ............................................................................................................... 9 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................... 10 2. PIN DESCRIPTION .............................................................................................................................. 12 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 13 4. APPLICATIONS ................................................................................................................................... 14 4.1 Single-, Double-, and Quad-Speed Modes ..................................................................................... 14 4.2 Operation as Either a Clock Master or Slave ................................................................................. 14 4.2.1 Operation as a Clock Master ................................................................................................. 15 4.2.2 Operation as a Clock Slave ................................................................................................... 15 4.2.3 Master Clock ......................................................................................................................... 16 4.3 Serial Audio Interface ..................................................................................................................... 16 4.4 Power-Up Sequence ...................................................................................................................... 17 4.5 Analog Connections ....................................................................................................................... 17 4.6 Grounding and Power Supply Decoupling ...................................................................................... 17 4.7 Synchronization of Multiple Devices ............................................................................................... 17 4.8 Capacitor Size on the Reference Pin (FILT+) ................................................................................ 17 5. PARAMETER DEFINITIONS ................................................................................................................ 19 6. PACKAGE DIMENSIONS ................................................................................................................... 20 THERMAL CHARACTERISTICS .......................................................................................................... 20 7. ORDERING INFORMATION ................................................................................................................ 21 8. REVISION HISTORY ............................................................................................................................ 21 LIST OF FIGURES Figure 1.Single-Speed Stopband Rejection ................................................................................................ 7 Figure 2.Single-Speed Stopband Rejection (detail) .................................................................................... 7 Figure 3.Single-Speed Transition Band (detail) .......................................................................................... 7 Figure 4.Single-Speed Passband Ripple .................................................................................................... 7 Figure 5.Double-Speed Stopband Rejection ............................................................................................... 7 Figure 6.Double-Speed Stopband Rejection (detail) ................................................................................... 7 Figure 7.Double-Speed Transition Band (detail) ......................................................................................... 8 Figure 8.Double-Speed Passband Ripple ................................................................................................... 8 Figure 9.Quad-Speed Stopband Rejection ................................................................................................. 8 Figure 10.Quad-Speed Stopband Rejection (detail) ................................................................................... 8 Figure 11.Quad-Speed Transition Band (detail) ......................................................................................... 8 Figure 12.Quad-Speed Passband Ripple ................................................................................................... 8 Figure 13.Master Mode, Left-Justified SAI ................................................................................................ 11 Figure 14.Slave Mode, Left-Justified SAI .................................................................................................. 11 Figure 15.Master Mode, IS SAI ................................................................................................................ 11 Figure 16.Slave Mode, IS SAI .................................................................................................................. 11 Figure 17.Typical Connection Diagram ..................................................................................................... 13 Figure 18.CS5342 Master Mode Clocking ................................................................................................ 15 Figure 19.Left-Justified Serial Audio Interface .......................................................................................... 16 Figure 20.IS Serial Audio Interface .......................................................................................................... 16 Figure 21.CS5342 Recommended Analog Input Buffer ............................................................................ 17 Figure 22.CS5342 THD+N versus Frequency .......................................................................................... 18 2 DS608F1 CS5342 LIST OF TABLES Table 1. Speed Modes and the Associated Output Sample Rates (Fs) .................................................... 14 Table 2. CS5342 Mode Control ................................................................................................................. 14 Table 3. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates ...................................... 16 DS608F1 3 CS5342 1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TA = 25C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to 0 V.) Parameter Symbol Min Typ Max Unit Analog Digital Logic VA VD VL 3.1 3.1 2.38 (Note 1) 3.3 3.3 5.25 5.25 5.25 V V V Commercial (-CZZ) TAC -10 - 70 C Power Supplies (Note 2, 3) Ambient Operating Temperature Notes: 1. This part is specified at typical analog voltages of 3.3 V and 5.0 V. See "Analog Characteristics (CS5342-CZZ)" on page 5 for details. 2. In Quad-Speed Slave Mode, the CS5342 is only specified for operation with VA and VD at 5 V, 5%. ABSOLUTE MAXIMUM RATINGS (GND = 0 V, All voltages with respect to ground.) (Note 3) Parameter Symbol Min Max Units Analog Logic Digital VA VL VD -0.3 -0.3 -0.3 +6.0 +6.0 +6.0 V V V Input Current (Note 4) Iin -10 +10 mA Analog Input Voltage (Note 5) VIN GND-0.7 VA+0.7 V Digital Input Voltage (Note 5) VIND -0.7 VL+0.7 V Ambient Operating Temperature (Power Applied) TA -50 +95 C Storage Temperature Tstg -65 +150 C DC Power Supplies: 3. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 4. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC latch-up. 5. The maximum over/under voltage is limited by the input current. 4 DS608F1 CS5342 ANALOG CHARACTERISTICS (CS5342-CZZ) Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Dynamic Performance for Commercial Grade Single-Speed Mode Fs = 48 kHz Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise Double-Speed Mode Dynamic Range (Note 6) -1 dB -20 dB -60 dB Fs = 96 kHz 40 kHz bandwidth Quad-Speed Mode (Note 6) -1 dB -20 dB -60 dB -1 dB Fs = 192 kHz Symbol 40 kHz bandwidth (Note 6) -1 dB -20 dB -60 dB -1 dB Min Typ Max Min Typ Max Unit 99 96 105 102 - 96 93 102 99 - dB dB - -98 -82 -42 -92 - - -95 -79 -39 -89 - dB dB dB Min Typ Max Min Typ Max Unit 99 96 - 105 102 99 - 96 93 - 102 99 96 - dB dB dB - -98 -82 -42 -95 -92 - - -95 -79 -39 -87 -89 - dB dB dB dB Min Typ Max Min Typ Max Unit 99 96 - 105 102 99 - 96 93 - 102 99 96 - dB dB dB - -98 -82 -42 -95 -92 - - -95 -79 -39 -87 -89 - dB dB dB dB THD+N Symbol A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise VA = 3.3 V THD+N A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise Dynamic Range Symbol VA = 5 V THD+N Min Typ Max Unit - 90 - dB Interchannel Gain Mismatch - 0.1 - dB Gain Error -3 - +3 % Gain Drift - 100 - ppm/C 0.54*VA 0.56*VA 0.58*VA Vpp 18 - - k Dynamic Performance All Modes Interchannel Isolation DC Accuracy Analog Input Characteristics Full-Scale Input Voltage Input Impedance 6. Referred to the typical full-scale input voltage. DS608F1 5 CS5342 DIGITAL FILTER CHARACTERISTICS Parameter (Note 7) Symbol Min Typ Max Unit 0 - 0.4896 Fs -0.1 - 0.035 dB 0.5688 - - Fs 70 - - dB - 12/Fs - s 0 - 0.4896 Fs -0.1 - 0.058 dB Single-Speed Mode Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd Double-Speed Mode Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd 0.5604 - - Fs 69 - - dB - 9/Fs - s 0 - 0.2604 Fs -0.1 - 0.058 dB Quad-Speed Mode (Note 2) Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd 0.5000 - - Fs 60 - - dB - 5/Fs - s - 1 20 - Hz Hz - 10 - Deg - 0 dB High-Pass Filter Characteristics Frequency Response Phase Deviation Passband Ripple Filter Settling Time -3.0 dB -0.13 dB (Note 7) @ 20 Hz (Note 7) - 105/Fs s 7. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 1 to 9) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 6 DS608F1 0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 Amplitude (dB) Amplitude (dB) CS5342 0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0 0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 0 .4 0 0 .4 2 Fr e q u e n cy (n o r m aliz e d to Fs ) 0 0 .10 -1 0 .0 8 -2 0 .0 6 Amplitude (dB) Amplitude (dB) 0 .4 8 0 .50 0 .52 0 .54 0 .56 0 .58 0 .6 0 Figure 2. Single-Speed Stopband Rejection (detail) -3 -4 -5 -6 -7 0 .0 4 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -0 .0 6 -8 -0 .0 8 -9 -10 0 .4 5 -0 .10 0 .4 6 0 .4 7 0 .4 8 0 .4 9 0 .5 0 .51 0 .52 0 .53 0 .54 0 0 .55 0 .0 5 Figure 3. Single-Speed Transition Band (detail) Amplitude (dB) -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .15 0 .2 0 .2 5 0 .3 0 .3 5 0 .4 0 .4 5 0 .5 Figure 4. Single-Speed Passband Ripple 0 -10 -2 0 -3 0 -4 0 0 .0 0 .1 Fr e q u e n cy (n o r m aliz e d to Fs ) Fr e que ncy (nor m alize d to Fs ) Amplitude (dB) 0 .4 6 Fr e q u e n cy (n o r m aliz e d to Fs ) Figure 1. Single-Speed Stopband Rejection 0 .9 Fr e q u e n cy (n o r m aliz e d to Fs ) Figure 5. Double-Speed Stopband Rejection DS608F1 0 .4 4 1.0 0 -10 -2 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 0 .4 0 0 .4 2 0 .4 4 0 .4 6 0 .4 8 0 .50 0 .52 0 .54 0 .56 0 .58 0 .6 0 Fr e q u e n cy (n o r m aliz e d to Fs ) Figure 6. Double-Speed Stopband Rejection (detail) 7 0 0 .10 -1 0 .0 8 -2 0 .0 6 Amplitude (dB) Amplitude (dB) CS5342 -3 -4 -5 -6 -7 0 .0 4 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -8 -0 .0 6 -9 -0 .0 8 -10 0 .4 6 0 .4 7 0 .4 8 0 .4 9 0 .50 0 .51 -0 .10 0 .0 0 0 .52 Fr e q u e n cy (n o r m aliz e d to Fs ) 0 .10 0 .15 0 .2 0 0 .2 5 0 .3 0 0 .3 5 0 .4 0 0 .4 5 0 .50 Fr e q u e n cy (n o r m aliz e d to Fs ) Figure 7. Double-Speed Transition Band (detail) Figure 8. Double-Speed Passband Ripple 0 0 -10 -2 0 -3 0 -4 0 -10 -2 0 Amplitude (dB) Amplitude (dB) 0 .0 5 -50 -6 0 -70 -8 0 -9 0 -10 0 -3 0 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 -110 -12 0 -13 0 -14 0 0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 1.0 Fr e q u e n cy (n o r m aliz e d to Fs ) Fr e q u e n cy (n o r m aliz e d to Fs ) Figure 9. Quad-Speed Stopband Rejection Figure 10. Quad-Speed Stopband Rejection (detail) 0 0 .10 -1 0 .0 8 0 .0 6 -3 Amplitude (dB) Amplitude (dB) -2 -4 -5 -6 -7 -8 0 .0 0 -0 .0 2 -0 .0 4 -0 .0 8 0 .15 0 .2 0 0 .2 5 0 .3 0 0 .3 5 0 .4 0 0 .4 5 0 .50 Fr e q u e n cy (n o r m aliz e d to Fs ) Figure 11. Quad-Speed Transition Band (detail) 8 0 .0 2 -0 .0 6 -9 -10 0 .10 0 .0 4 -0 .10 0 .0 0 0 .0 3 0 .0 5 0 .0 8 0 .10 0 .13 0 .15 0 .18 0 .2 0 0 .2 3 0 .2 5 0 .2 8 Fr e q u e n cy (n o r m aliz e d to Fs ) Figure 12. Quad-Speed Passband Ripple DS608F1 CS5342 DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to 0 V. MCLK=18.432 MHz; Master Mode; refer to Note 2) Parameter Symbol Min Typ Max Unit Positive Analog Positive Digital Positive Logic VA VD VL 3.14 3.14 2.38 - 5.25 5.25 5.25 V V V VA = 5 V VA = 3.3 V VL,VD = 5 V VL,VD = 3.3 V IA IA ID ID - 21 18.2 15 9 25.5 22.5 18.5 10 mA mA mA mA Power Supply Current (Power-down Mode) (Note 8) VA = 5 V VL,VD=5 V IA ID - 1.5 0.4 - mA mA Power Consumption (Normal Operation) (Normal Operation) (Power-Down Mode)(Note 8) VL, VD, VA = 5 V VL, VD, VA = 3.3 V - - 180 90 9.5 220 107.2 - mW mW mW PSRR - 65 - dB Output Impedance - VA/2 25 - V k Output Impedance Maximum allowable DC current source/sink - VA 36 0.01 - V k mA DC Power Supplies: Power Supply Current (Normal Operation) Power Supply Rejection Ratio (1 kHz) (Note 9) VQ Nominal Voltage Filt+ Nominal Voltage 8. Power-Down Mode is defined as RST = Low with all clocks and data lines held static. 9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the "Typical Connection Diagram". DIGITAL CHARACTERISTICS Symbol Min Typ Max Units High-level Input Voltage Parameter (% of VL) VIH 70% - - V Low-level Input Voltage (% of VL) VIL - - 30% V High-level Output Voltage at Io = 100 A (% of VL) VOH 70% - - V Low-level Output Voltage at Io =100 A (% of VL) VOL - - 15% V Iin -10 - 10 A Input Leakage Current DS608F1 9 CS5342 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF) Parameter Symbol Min Typ Max Unit tclkw 26 - 30 ns 52 - 1302 ns 40 - 60 % MCLK Specifications MCLK Period MCLK Pulse Duty Cycle Master Mode SCLK falling to LRCK tmslr -20 - 20 ns SCLK falling to SDOUT valid tsdo - - 32 ns - 50 50 33 - % % % 40 - 60 % 313 - - ns 45 - 55 % SCLK Duty Cycle Single-Speed Double-Speed Quad-Speed Slave Mode Single-Speed (Note 10) LRCK Duty Cycle SCLK Period tsclkw SCLK Duty Cycle SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5 - - ns SCLK falling to LRCK edge tslrd -20 - 20 ns 40 - 60 % 208 - - ns 45 - 55 % Double-Speed (Note 10) LRCK Duty Cycle SCLK Period (Note 11) tsclkw SCLK Duty Cycle SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5 - - ns SCLK falling to LRCK edge tslrd -20 - 20 ns 40 - 60 % tsclkw 104 - - ns 40 - 50 % tstp 10 - - ns Quad-Speed (Note 10) LRCK Duty Cycle SCLK Period (Note 11) SCLK Duty Cycle SDOUT valid before SCLK rising SDOUT valid after SCLK rising thld 5 - - ns SCLK falling to LRCK edge tslrd -8 - 8 ns 10. For a description of speed modes, please refer to Table 1 on page 14 11. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48. 10 DS608F1 CS5342 LRCK input LRCK output t sclkw t slrd tmslr SCLK input SCLK output t stp thld tsdo SDOUT MSB-1 MSB Figure 13. Master Mode, Left-Justified SAI SDOUT MSB MSB-1 Figure 14. Slave Mode, Left-Justified SAI LRCK input LRCK output t slrd tmslr tsclkw SCLK input SCLK output t stp thld t sdo SDOUT MSB Figure 15. Master Mode, IS SAI DS608F1 MSB-1 SDOUT MSB Figure 16. Slave Mode, IS SAI 11 CS5342 2. PIN DESCRIPTION M0 MCLK VL SDOUT GND VD SCLK LRCK Pin Name # M0 M1 MCLK VL SDOUT GND VD SCLK 1 16 2 3 4 5 6 7 LRCK 8 RST AINL AINR VQ VA REFGND 9 10 12 11 13 14 FILT+ 15 12 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 M1 FILT+ REFGND VA AINR VQ AINL RST Pin Description Mode Selection (Input) - Determines the operational mode of the device. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Logic Power (Input) - Positive power for the digital input/output. Serial Audio Data Output (Output) - Output for two's complement serial audio data. Ground (Input) - Ground reference. Must be connected to analog ground. Digital Power (Input) - Positive power supply for the digital section. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Reset (Input) - The device enters a low-power mode when low. Analog Input (Input) - The full-scale analog input level is specified in the Analog Characteristics specification table. Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Analog Power (Input) - Positive power supply for the analog section. Reference Ground (Output) - Ground reference for the internal sampling circuits. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. DS608F1 CS5342 3. TYPICAL CONNECTION DIAGRAM 4 3.3V to 5V + 1 F 0.1 F 0.1 F + 2.5V to 5V 1 F 2 4 3.3V to 5V + 1 F 0.1 F 5.1 VA 0.1 F VD VL FILT+ 3 1 F + 0.1 F REFGND + 1 F 0.1 F VQ CS5342 RST M0 M1 Power Down and Mode Settings 1 VL or GND A/D CONVERTER 10 k A INL Audio Data Processor SDOUT Analog Input Buffer Figure 15 AI NR MCLK Timing Logic and Clock LRCK SCLK 1 Pull-up to VL for I2S Pull-down to GND for LJ GND 2 Resistor may only be used if VD is derived from VA. If used, do not drive any other logic from VD 3 Capacitor value affects low frequency distortion performance as described in Section 4.8 4 See Note 2 on page 4 Figure 17. Typical Connection Diagram DS608F1 13 CS5342 4. APPLICATIONS 4.1 Single-, Double-, and Quad-Speed Modes The CS5342 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be determined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1. MCLK/LRCK Ratio Speed Mode Output Sample Rate Range (kHz) 768x Single-Speed Mode 384x 384x Double-Speed Mode 192x 192x Quad-Speed Mode 96x* * Quad-Speed Mode, 96x only available in Master Mode. 43 - 50 2 - 50 86 - 100 50 - 100 172 - 200 100 - 200 Table 1. Speed Modes and the Associated Output Sample Rates (Fs) 4.2 Operation as Either a Clock Master or Slave The CS5342 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK pins are outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The selection of clock master or slave is made via the Mode pins as shown in Table 2. M1 (Pin 16) M0 (Pin 1) 0 0 1 1 0 1 0 1 MODE Clock Master, Single-Speed Mode Clock Master, Double-Speed Mode Clock Master, Quad-Speed Mode Clock Slave, All Speed Modes Table 2. CS5342 Mode Control 14 DS608F1 CS5342 4.2.1 Operation as a Clock Master As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 18. / 1.5 / 256 Single Speed 00 / 128 Double Speed 01 / 64 Quad Speed 10 LRCK Output (Equal to Fs) 0 MCLK M[1:0] /3 1 Auto-Select /4 Single Speed 00 /2 Double Speed 01 /1 Quad Speed 10 SCLK Output Figure 18. CS5342 Master Mode Clocking 4.2.2 Operation as a Clock Slave LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and equal to 48x Fs or 64x Fs in SingleSpeed Mode. In Double-Speed and Quad-Speed Modes, the serial clock must be derived synchronously from the master clock and equal to 48x Fs. Additionally, Quad-Speed Slave Mode is only specified for operation with a VA and VD at 5 V, 5%. A unique feature of the CS5342 is the automatic selection of either Single-, Double- or Quad-Speed Mode when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are not supported when operating with a fast MCLK (768x, 384x, and 192x for Single-, Double-, and QuadSpeed Modes respectively). Please refer to Table 1 on page 14 for supported sample rate ranges. DS608F1 15 CS5342 4.2.3 Master Clock The CS5342 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is also an internal MCLK divider which is automatically activated according to the frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required. Table 3 lists some common audio output sample rates and the required MCLK frequency. Please note that not all of the listed sample rates are supported when operating with a fast MCLK (768x, 384x, 192x for Single-, Double-, and Quad-Speed Modes, respectively). Single-Speed Mode Double-Speed Mode Quad-Speed Mode 192x, 384x 96x*, 192x MCLK/LRCK Ratio 384x, 768x * Quad-Speed, 96x only available in Master Mode. SAMPLE RATE (kHz) MCLK (MHz) 32 12.288 16.9344 33.8688 18.432 36.864 12.288 16.9344 33.8688 18.432 36.864 36.864 44.1 48 64 88.2 96 192 Table 3. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates 4.3 Serial Audio Interface The CS5342 supports both IS and Left-Justified serial audio formats. Upon start-up, the CS5342 will detect the logic level on SDOUT (pin 4). A 10 k pull-up resistor to VL is needed to select IS format, and a 10 k pull-down resistor to GND is needed to select Left-Justified format. Please see Figures 13 through 16 for more information on the required timing for the two serial audio interface formats. LRCK Left Channel Right Channel SCLK SDATA 23 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 0 23 22 0 23 22 Figure 19. Left-Justified Serial Audio Interface LRCK Left Channel Right Channel SCLK SDATA 23 22 9 8 7 6 5 4 3 2 1 0 23 22 9 8 7 6 5 4 3 2 1 Figure 20. IS Serial Audio Interface 16 DS608F1 CS5342 4.4 Power-Up Sequence Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power-glitch-related issues. 4.5 Analog Connections The analog modulator samples the input at 6.144 MHz. The digital filter rejects signals within the stopband of the filter. However, there is no rejection for input signals that are multiples of the input sampling frequency (n x 6.144 MHz), where n=0, 1, 2, .... Figure 21 shows the suggested filter that attenuates any noise energy at 6.144 MHz and provides the optimum source impedance for the modulators. The use of capacitors that have a large voltage coefficient (such as general-purpose ceramics) must be avoided because these can degrade signal linearity. 634 VA 100 k 470 pF C0G 91 4.7 F CS5342 AINx AINx 2700 pF 100 k Figure 21. CS5342 Recommended Analog Input Buffer 4.6 Grounding and Power Supply Decoupling As with any high-resolution converter, the CS5342 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 17 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply or powered from the analog supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and REF_GND. The CDB5342 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs. 4.7 Synchronization of Multiple Devices In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5342's in the system. 4.8 Capacitor Size on the Reference Pin (FILT+) The CS5342 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decoupling capacitor affects the low frequency distortion performance, as shown in Figure 22, with larger capacitor values used to optimize low frequency distortion performance. The THD+N curves in Figure 22 DS608F1 17 CS5342 were measured with VA = VD = VL = 5 V in Single-Speed Master Mode using a 1 kHz input tone of magnitude -1 dB Full-Scale. 1 uF 2.2 uF 3.3 uF 4.7 uF 5.6 uF 6.8 uF 10 uF 22 uF 47 uF 100 uF Figure 22. CS5342 THD+N versus Frequency 18 DS608F1 CS5342 5. PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS608F1 19 CS5342 6. PACKAGE DIMENSIONS 16L TSSOP (4.4 mm BODY) PACKAGE DRAWING N D E11 A2 E A b2 e SIDE VIEW A1 END VIEW L SEATING PLANE 1 2 3 TOP VIEW DIM MIN INCHES NOM MAX MIN MILLIMETERS NOM A -- -- 0.043 -- -- NOTE MAX 1.10 A1 0.002 0.004 0.006 0.05 -- 0.15 A2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 D 0.193 0.1969 0.201 4.90 5.00 5.10 1 E 0.248 0.2519 0.256 6.30 6.40 6.50 E1 0.169 0.1732 0.177 4.30 4.40 4.50 e -- 0.026 BSC -- -- 0.65 BSC -- L 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 1 JEDEC #: MO-153 Controlling Dimension is Millimeters Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. THERMAL CHARACTERISTICS Parameter Symbol Allowable Junction Temperature Junction-to-ambient Thermal Impedance 20 JA Min Typ Max Unit - - 135 C - 75 - C/W DS608F1 CS5342 7. ORDERING INFORMATION Product CS5342 CS5342 Description Package Pb-Free 105 dB, 192 kHz, Multi-bit Audio A/D 16-TSSOP Converter CS5342 Evaluation Board Grade Temp Range Yes Commercial -10 to 70 C NO - - Container Order # Tube CS5342-CZZ Tape and Reel CS5342-CZZR - - 8. REVISION HISTORY Release A1 A2 PP1 PP2 PP3 F1 Changes Initial Release Modify serial port timing specs Add Applications section on speed mode detect Change value of capacitors in analog input buffer diagram Add new Applications section about capacitor on FILT+ pin Redefine slave mode timing specifications under Switching Characteristics Initial Preliminary Release. Add lead-free device ordering information Update Output Sample Rate Range table Final Release Correct dimension "e" under Package Dimensions Update maximum current and power specifications Update FILT+ output impedance specification Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS608F1 21