Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
http://www.cirrus.com
105 dB, 192 kHz, Multi-bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture
24-bit Conversion
Supports All Audio Sample Rates Including
192 kHz
105 dB Dynamic Range at 5 V
-98 dB THD+N
90 mW Power Consumption
High-Pass Filter to Remove DC Offsets
Analog/Digital Core Supplies from 3.3 V to 5 V
Supports Logic Levels between 2.5 V and 5 V
Low-Latency Digital Filter
Auto-detect Mode Selection in Slave Mode
Auto-Detect MCLK Divider
Supports 384x MCLK/LRCK Ratios
General Description
The CS5342 is a complete analog-to-digital converter
for digital audio systems. It performs sampling, analog-
to-digital conversion and anti-alias filtering, generating
24-bit values for both left and right inputs in serial form
at sample rates up to 200 kHz per channel.
The CS5342 uses a 5th-order, multi-bit Delta-Sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The CS5342 is availa ble in a 16-pin TSSOP package in
Commercial grade (-10° to 70° C). The CDB5342 Cus-
tomer Demonstration board is also available for device
evaluation and implementation suggestions. Please re-
fer to “Ordering Information” on page 21 for complete
ordering information.
The CS5342 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as set-top boxes, DVD-karaoke players, DVD record-
ers, A/V receivers, and automotive applications.
CS5342
APRIL '06
DS608F1
High-Pass
Filter
Low-Latency
Digital Filters
High-Pass
Filter
Serial Port
VA
3.3 V to 5 V
Internal
Reference
Voltages
Switch-Cap
ADC
VD
3.3 V to 5 V VL
2.5 V to 5 V
Auto-detect
MCLK Divider
Slave Mode
Auto-detect
Master Clock
Reset
Single-Ended
Analog Input
Low-Latency
Digital Filters
Switch-Cap
ADC
Mode
Configuration
Single-Ended
Analog Input
SCLK
LRCK
SDOUT
M0
M1
FILT+
VQ
AINR
AINL ÷1.5
2DS608F1
CS5342
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4
SPECIFIED OPERATING CONDITIONS ............................................................................................... 4
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 4
ANALOG CHARACTERISTICS (CS5342-CZZ) ..................................................................................... 5
DIGITAL FILTER CHARACTERISTICS .................................................................................................6
DC ELECTRICAL CHARA CTERISTIC S .............. ... ... .... ... ... ... .................... ... ... ................... .... ... ... ........ 9
DIGITAL CHARACTERISTICS ............................................................................................................... 9
SWITCHING CHARAC TE RISTIC S - SERIA L AUDI O PORT ............... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 10
2. PIN DESCRIPTION .............................................................................................................................. 12
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 13
4. APPLICATIONS ................................................................................................................................... 14
4.1 Single-, Double-, and Quad-Speed Modes .....................................................................................14
4.2 Operation as Either a Clock Master or Slave ................................................................................. 14
4.2.1 Operation as a Clock Master ........................................... ... ... ... .................... ... ... ................... 15
4.2.2 Operation as a Clock Slave ............................................. ... ... ... .................... ... ... ................... 15
4.2.3 Master Clock ......... ... ... ... .... ................... ................... .................................... ......................... 16
4.3 Serial Audio Interface ..................................................................................................................... 16
4.4 Power-Up Sequence ...................................................................................................................... 17
4.5 Analog Connections ....................................................................................................................... 17
4.6 Grounding and Power Supply Decoupling ................ ... ... ... .... ... ................... ... .... ... ... ... ...................17
4.7 Synchronization of Multiple Devices ............................................................................................... 17
4.8 Capacitor Size on the Reference Pin (FILT+) ................................................................................17
5. PARAMETER DEFINITIONS ................................................................................................................ 19
6. PACKAGE DIMENSIONS ................................................................................................................... 20
THERMAL CHARACTERISTICS .......................................................................................................... 20
7. ORDERING INFORMATION ................................................................................................................ 21
8. REVISION HISTORY ............................................................................................................................ 21
LIST OF FIGURES
Figure 1.Single-Speed Stopband Rejection ................................................................................................ 7
Figure 2.Single-Speed Stopband Rejection (detail) .................................................................................... 7
Figure 3.Single-Speed Transition Band (detail) .......................................................................................... 7
Figure 4.Single-Speed Passband Ripple .................................................................................................... 7
Figure 5.Double-Speed Stopband Rejection ...... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ..................... 7
Figure 6.Double-Speed Stopband Rejection (detail) ................................................................................... 7
Figure 7.Double-Speed Transition Band (detail) ................. ... ... ... .... ... ... ................... .................... ... ........... 8
Figure 8.Double-Speed Passband Ripple . ... ... ... .... ... ... ... .... ... ... ................... .... ... ... ... .... ... ... ... ... .... ... ........... 8
Figure 9.Quad-Speed Stopband Rejection ................................................................................................. 8
Figure 10.Quad-Speed Stopband Rejection (detail) ................................................................................... 8
Figure 11.Quad-Speed Transition Band (detail) ................. ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ........... 8
Figure 12.Quad-Speed Passband Ripple ................................................................................................... 8
Figure 13.Master Mode, Left-Justified SAI ................................................................................................ 11
Figure 14.Slave Mode, Left-Justified SAI .................................................................................................. 11
Figure 15.Master Mode, I²S SAI ......... .... ... ... ... ... .... ................... ... .... ... ... ... ... .................... ... ... ... ................ 11
Figure 16.Slave Mode, I²S SAI .................................................................................................................. 11
Figure 17.Typical Connection Diagram ..................................................................................................... 13
Figure 18.CS5342 Master Mode Clocking ............................. ... ................... .... ... ... ... .... ... ... ... ... .... ... ......... 15
Figure 19.Left-Justified Serial Audio Interface .......................................................................................... 16
Figure 20.I²S Serial Audio Interface .......................................................................................................... 16
Figure 21.CS5342 Recommended Analog Input Buffer ............................................................................ 17
Figure 22.CS5342 THD+N versus Frequency .......... ... ... .... ... ... ... .... ... ... ................... .... ... ... ... ... .... ... ... ... ... 18
DS608F1 3
CS5342
LIST OF TABLES
Table 1. Speed Modes and the Associated Output Sample Rat es (Fs) ........... ... ... ... .... ................... ......... 14
Table 2. CS5342 Mode Control ................................................................................................................. 14
Table 3. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates ...................................... 16
4DS608F1
CS5342
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristic s an d spe cif icat ion s are de rived from measurements taken at typical supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.)
Notes: 1. This part is specified at typical analog voltages of 3.3 V and 5.0 V. See “Analog Characteristics
(CS5342-CZZ)” on page 5 for details.
2. In Quad-Speed Slave Mode, the CS5342 is only specified for operation with VA and VD at 5 V, ±5%.
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 3)
3. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
4. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SRC
latch-up.
5. The maximum over/under voltage is limited by the input current.
Parameter Symbol Min Typ Max Unit
Power Supplies (Note 2, 3)Analog
Digital
Logic
VA
VD
VL
3.1
3.1
2.38
(Note 1)
3.3
3.3
5.25
5.25
5.25
V
V
V
Ambient Operating Temperature Commercial (-CZZ) TAC -10 - 70 °C
Parameter Symbol Min Max Units
DC Power Supplies: Analog
Logic
Digital
VA
VL
VD
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
V
V
V
Input Current (Note 4) Iin -10 +10 mA
Analog Input Voltage (Note 5) VIN GND-0.7 VA+0.7 V
Digital Input Voltage (Note 5) VIND -0.7 VL+0.7 V
Ambient Operating Temperature (Power Applied) TA-50 +95 °C
Storage Temperature Tstg -65 +150 °C
DS608F1 5
CS5342
ANALOG CHARACTERISTICS (CS5342-CZZ)
Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.
6. Referred to the typical full-scale input voltage.
Dynamic Performance for Commercial Grade VA = 5 V VA = 3.3 V
Single-Speed Mode Fs = 48 kHz Symbol Min Typ Max Min Typ Max Unit
Dynamic Range A-weighted
unweighted 99
96 105
102 -
-96
93 102
99 -
-dB
dB
Total Harmonic Distortion + Noise (Note 6)
-1 dB
-20 dB
-60 dB
THD+N -
-
-
-98
-82
-42
-92
-
-
-
-
-
-95
-79
-39
-89
-
-
dB
dB
dB
Double-Speed Mode Fs = 96 kHz Symbol Min Typ Max Min Typ Max Unit
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
99
96
-
105
102
99
-
-
-
96
93
-
102
99
96
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 6)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth -1 dB
THD+N -
-
-
-
-98
-82
-42
-95
-92
-
-
-
-
-
-
-
-95
-79
-39
-87
-89
-
-
-
dB
dB
dB
dB
Quad-Speed Mode Fs = 192 kHz Symbol Min Typ Max Min Typ Max Unit
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
99
96
-
105
102
99
-
-
-
96
93
-
102
99
96
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 6)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth -1 dB
THD+N -
-
-
-
-98
-82
-42
-95
-92
-
-
-
-
-
-
-
-95
-79
-39
-87
-89
-
-
-
dB
dB
dB
dB
Dynamic Performance All Modes Min Typ Max Unit
Interchannel Isolation - 90 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Gain Error -3 - +3 %
Gain Drift - ±100 - ppm/°C
Analog Input Characteristics
Full-Scale Input Vo ltage 0.54*VA 0.56*VA 0.58*VA Vpp
Input Impedance 18 - - k
6DS608F1
CS5342
DIGITAL FILTER CHARACTERISTICS
7. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 1 to 9) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
Parameter (Note 7) Symbol Min Typ Max Unit
Single-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple -0.1 - 0.035 dB
Stopband 0.5688 - - Fs
Stopband Attenuation 70 - - dB
To tal Group Delay (Fs = Output Sample Rate) tgd -12/Fs - s
Double-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple -0.1 - 0.058 dB
Stopband 0.5604 - - Fs
Stopband Attenuation 69 - - dB
To tal Group Delay (Fs = Output Sample Rate) tgd -9/Fs - s
Quad-Speed Mode (Note 2)
Passband (-0.1 dB) 0 - 0.2604 Fs
Passband Ripple -0.1 - 0.058 dB
Stopband 0.5000 - - Fs
Stopband Attenuation 60 - - dB
To tal Group Delay (Fs = Output Sample Rate) tgd -5/Fs - s
High-Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 7) -1
20 -
-Hz
Hz
Phase Deviation @ 20 Hz (Note 7) -10 -Deg
Passband Ripple --0dB
Filter Settling Time 105/Fs s
DS608F1 7
CS5342
Figure 1. Single-Speed Stopband Rejection Figure 2. Single-Speed Stopband Rejection (detail)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Fr equency (normalize d to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequ ency (normalize d to Fs)
Amplitude (dB)
Figure 3. Single-Speed Transition Band (detail) Figure 4. Single-Speed Passband Ripple
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Fr equency (normaliz ed to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Freq ue ncy (normaliz ed to Fs)
Amplitude (dB)
Figure 5. Double-Speed Stopband Rejection Figure 6. Double-Speed Stopband Rejection (detail)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Fr equency (normalize d to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequ ency (normalize d to Fs)
Amplitude (dB)
8DS608F1
CS5342
Figure 7. Double-Speed Transition Band (detail) Figure 8. Double-Speed Passband Ripple
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.46 0.47 0.48 0.49 0.50 0.51 0.52
Fr eque n cy (normalize d to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Fr eque n cy (normalize d to Fs)
Amplitude (dB)
Figure 9. Quad-Speed Stopband Rejection Figure 10. Quad-Speed Stopba nd Rejection (detail)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Fr equency (normalize d to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Fr equency (normalize d to Fs)
Amplitude (dB)
Figure 11. Quad-Speed Transition Band (detail) Figure 12. Quad-Speed Passband Ripple
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Fr equency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Freq uency (normalize d to Fs)
Amplitude (dB)
DS608F1 9
CS5342
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to 0 V. MCLK=18.432 MHz; Master Mode; refer to Note 2)
8. Power-Down Mode is defined as RST = Low with all clocks and data lines held static.
9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the “Typical Connection
Diagram”.
DIGITAL CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
DC Power Supplies: Positive Analog
Positive Digital
Positive Logic
VA
VD
VL
3.14
3.14
2.38
-
-
-
5.25
5.25
5.25
V
V
V
Power Supply Current VA = 5 V
(Normal Operation) VA = 3.3 V
VL,VD = 5 V
VL,VD = 3.3 V
IA
IA
ID
ID
-
-
-
-
21
18.2
15
9
25.5
22.5
18.5
10
mA
mA
mA
mA
Power Supply Current VA = 5 V
(Power-down Mode) (Note 8) VL,VD=5 V IA
ID
-
-1.5
0.4 -
-mA
mA
Power Consumption
(Normal Operation) VL, VD, VA = 5 V
(Normal Operation) VL, VD, VA = 3.3 V
(Power-Down Mode)(Note 8)
-
-
-
-
-
-
180
90
9.5
220
107.2
-
mW
mW
mW
Power Supply Rejection Ratio (1 kHz) (Note 9 ) PSRR - 65 - dB
VQ Nominal Voltage Output Impedance -
-VA÷2
25 -
-V
k
Filt+ Nominal Voltage Output Impedance
Maximum allowable DC current source/sink
-
-
-
VA
36
0.01
-
-
-
V
k
mA
Parameter Symbol Min Typ Max Units
High-level Input Voltage (% of VL) VIH 70% - - V
Low-level Input Voltage (% of VL) VIL - - 30% V
High-level Output Voltage at Io = 100 µA(% of VL)
VOH 70% - - V
Low-level Output Vo ltage at Io =100 µA(% of VL)
VOL - - 15% V
Input Leakage Current Iin -10 - 10 µA
10 DS608F1
CS5342
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF)
10. For a description of speed modes, please refer to Table 1 on page 14
11. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48.
Parameter Symbol Min Typ Max Unit
MCLK Specifications
MCLK Period tclkw 26 - 30 ns
52 - 1302 ns
MCLK Pulse Duty Cycle 40 - 60 %
Master Mode
SCLK falling to LRCK tmslr -20 - 20 ns
SCLK falling to SDOUT valid tsdo --32ns
SCLK Duty Cycle Single-Speed
Double-Speed
Quad-Speed
-
-
-
50
50
33
-
-
-
%
%
%
Slave Mode
Single-Speed (Note 10)
LRCK Duty Cycle 40 - 60 %
SCLK Period tsclkw 313 - - ns
SCLK Duty Cycle 45 - 55 %
SDOUT valid before SCLK rising tstp 10 - - ns
SDOUT valid after SCLK rising thld 5--ns
SCLK falling to LRCK edge tslrd -20 - 20 ns
Double-Speed (Note 10)
LRCK Duty Cycle 40 - 60 %
SCLK Period (Note 11) tsclkw 208 - - ns
SCLK Duty Cycle 45 - 55 %
SDOUT valid before SCLK rising tstp 10 - - ns
SDOUT valid after SCLK rising thld 5--ns
SCLK falling to LRCK edge tslrd -20 - 20 ns
Quad-Speed (Note 10)
LRCK Duty Cycle 40 - 60 %
SCLK Period (Note 11) tsclkw 104 - - ns
SCLK Duty Cycle 40 - 50 %
SDOUT valid before SCLK rising tstp 10 - - ns
SDOUT valid after SCLK rising thld 5--ns
SCLK falling to LRCK edge tslrd -8 - 8 ns
DS608F1 11
CS5342
Figure 13. Master Mode, Left-Justified SAI Figure 14. Slave Mode, Left-Justified SAI
SC LK output
SDOUT
LR CK output
MSB MSB-1
tsdo
tmslr
LRCK input
SCLK input
SDOUT MSB
tstp thld
tsclkw
MSB-1
tslrd
Figure 15. Master Mode, I²S SAI Figure 16. Slave Mode, I²S SAI
SC LK output
SDOUT
LRCK output
MSB
tmslr
MSB-1
tsdo
LRCK input
SCLK input
SDOUT
tstp thld
tsclkw
MSB
tslrd
12 DS608F1
CS5342
2. PIN DESCRIPTION
Pin Name # Pin Description
M0
M1 1
16 Mode Selection (Input) - Determines the operational mode of the device.
MCLK 2 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VL 3 Logic Power (Input) - Positive power for the digital input/output.
SDOUT 4 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
GND 5 Ground (Input) - Ground reference. Must be connected to analog ground.
VD 6 Digital Power (Input) - Positive power supply for the digital section.
SCLK 7 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK 8 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on
the serial audio data line.
RST 9Reset (Input) - The device enters a low-power mode when low.
AINL
AINR 10
12 Analog Input (Input) - The full-scale analog input level is specified in the Analog Characteristics
specification table.
VQ 11 Quiescent Voltage (Output) - Filter connection for the intern al quiescent reference voltage.
VA 13 Analog Power (Input) - Positive power supply for the analog section.
REFGND 14 Reference Ground (Output) - Ground reference for the internal sampling circuits.
FILT+ 15 Positive Voltage Reference (Output) - Positive reference voltage for the internal
sampling circuits.
M0 M1
MCLK FILT+
VL REFGND
SDOUT VA
GND AINR
VD VQ
SCLK AINL
LRCK RST
1
2
3
4
5
6
7
8
5
1
2
6
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
5
1
2
6
16
15
14
13
12
11
10
9
DS608F1 13
CS5342
3. TYPICAL CONNECTION DIAGRAM
Figure 17. Typical Connection Diagram
FILT+ V
0.1 µF
A/D CONVERTER
SCLK
CS5342
MCLK
VQ
1µ
F+
RST
VA L
1µ
F2.5V to 5V
1µF
+
+
SDOUT
GND
LRCK
Power Down
and M ode
Settings
Audio Data
Processor
Timing Logic
and Clock
0.1 µF
0.1 µ
F
0.1 µ
F
REFGND
1 µF
+
AINL
AINR
3.3V to 5V
1µF
+0.1 µ
F
3.3V to 5V
5.1
VD
0.1 µ
F
10 k
VL or GND
P ull-up to VL fo r I2S
Pull-down to GND for LJ
M0
M1
Analog Input Buffer
Figure 15
R esistor ma y on ly be
used if VD is derived from
VA. If used, do not drive any
other logic from VD
Capacitor value affects
low frequency distortion
performance as described
in Sec tio n 4.8
1
2
3
See Note 2 on page 4
4
4
4
1
2
3
14 DS608F1
CS5342
4. APPLICATIONS
4.1 Single-, Double-, and Quad-Speed Modes
The CS5342 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be de-
termined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)
4.2 Operation as Either a Clock Master or Slave
The CS5342 supports op eration a s e ith er a clock ma st er or sla ve. As a clock m aster, th e LRCK and SCL K
pins are outputs with th e left/right an d serial clocks synchronously generated on-chip. As a clock slave, the
LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally gener ated. The
selection of clock master or slave is made via the Mode pins as shown in Table 2.
Speed Mode MCLK/LRCK
Ratio Output Sample Rate Range (kHz)
Single-Speed Mode 768x 43 - 50
384x 2 - 50
Double-Speed Mode 384x 86 - 100
192x 50 - 100
Quad-Speed Mode 192x 172 - 200
96x* 100 - 200
* Quad-Speed Mode, 96x only available in Master Mode.
M1 (Pin 16) M0 (Pin 1) MODE
0 0 Clock Master, Single-Speed Mode
0 1 Clock Master, Double-Speed Mode
1 0 Clock Master, Quad-Speed Mode
1 1 Clock Slave, All Sp eed Modes
Table 2. CS5342 Mode Control
DS608F1 15
CS5342
4.2.1 Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/r igh t an d se ria l clocks are internally de-
rived from the master cloc k with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as
shown in Figure 18.
4.2.2 Operation as a Clock Slave
LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the
serial clock be synchronously derived from the master clock and equal to 48x Fs or 64x Fs in Single-
Speed Mode. In Double- Speed a nd Qu ad-Speed Modes, th e serial clock must be derived synchron ously
from the master clock and equal to 48x Fs. Additionally, Quad-Speed Slave Mode is only specified for
operation with a VA and VD at 5 V, ±5%.
A unique feature of th e CS5342 is the automatic selection of either Sin gle-, Double- or Quad-Speed Mode
when operating as a clock slave. The auto-mode select feature negate s the ne ed to con figur e th e Mode
pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio
sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are
not supported when operating with a fast MCLK (768x, 384x, and 192x for Single-, Double-, and Quad-
Speed Modes respectively). Please refer to Table 1 on page 14 for supported sample rate ranges.
÷ 128
÷ 256
÷ 64
M[1:0]
LRCK Output
(Equal to Fs)
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 2
÷ 4
÷ 1
SCLK Output
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 3
÷ 1.5 0
1
MCLK
Auto-Select
Figure 18. CS5342 Master Mode Clocking
16 DS608F1
CS5342
4.2.3 Master Clock
The CS5342 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.
There is also an internal MCLK divider which is automatically activated according to the frequency of the
MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required. Table 3 lists some
common audio output sample rates and the required MCLK frequency. Please note that not all of the listed
sample rates are supported when operating with a fast MCLK ( 768x, 384x, 192x for Single-, Double-, and
Quad-Speed Modes, respectively).
4.3 Serial Audio Interface
The CS5342 supports both I²S and Left-Justified serial audio formats. Upon start-up, the CS5342 will detect
the logic level on SDOUT (pin 4). A 10 k pull-up resistor to VL is needed to select I²S format, and a 10 k
pull-down resist or to GND is needed to select Left-Justified format. Please see Figures 13 through 16 for
more information on the required timing for the two serial audio interface formats.
Single-S peed Mode Double-S peed Mode Quad-Speed Mode
MCLK/LRCK Ratio 384x, 768x 192x, 384x 96x*, 192x
* Quad-Spe ed, 96x only available in Master Mode.
SAMPLE RATE (kHz) M CLK (MHz)
32 12.288
44.1 16.9344
33.8688
48 18.432
36.864
64 12.288
88.2 16.9344
33.8688
96 18.432
36.864
192 36.864
Table 3. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
Figure 19. Left-Justified Serial Audio Interface
SDATA 23 22 7 623 22
SCLK
LRCK
23 2254321087654321089 9
Left Channel Right Channel
Figure 20. I²S Serial Audio Interface
S
DATA 23 22 8 723 22
SCLK
LRCK
23 2265432108765432109 9
Left Channel Right Channel
DS608F1 17
CS5342
4.4 Power-Up Sequence
Reliable power- up can be accomplishe d by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies
drop below the minimum specified operating voltages to prevent power-glitch-related issues.
4.5 Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter rejects signals within the stopband
of the filter. However, there is no rejection for input signals that are multiples of the input sampling frequency
(n ×6.144 MHz), where n=0, 1, 2, .... Figure 21 shows the suggested filter that attenuates any noise energy
at 6.144 MHz and provides the optimum source impedance for the modulators. The use of capacitors that
have a large voltage coefficient (such as general-purpose ceramics) must be avoided because these can
degrade signal linearity.
4.6 Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS5342 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 17 shows the recommended power ar-
rangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run
from the system logic supply or powered from the analog supply via a resistor. In this case, no additional
devices should be powered from VD. Decouplin g capacitors should be as near to the ADC as possible, with
the low value ceramic capacitor be ing th e ne arest. All si gn als, e specially clocks, should be kept away from
the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decou-
pling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and
REF_GND. The CDB5342 evaluation board demonstrates the optimum layout and power supply arrange-
ments. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
4.7 Synchronization of Multiple Devices
In systems where multiple ADCs ar e required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5342’s in the system.
4.8 Capacitor Size on the Reference Pin (FILT+)
The CS5342 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this
decoupling capacitor affects the low frequency distortion performance, as shown in Figure 22, with larger
capacitor values used to optimize low frequency distortion performance. The THD+N curves in Figure 22
Figure 21. CS5342 Recommended Analog Input Buffer
100 k
100 k
VA
4.7 µF
470 pF
C0G
634
91
2700 pF
CS5342 AINx
AINx
18 DS608F1
CS5342
were measured with VA = VD = VL = 5 V in Single-Speed Master Mode usin g a 1 kHz in put tone of mag ni-
tude -1 dB Full-Scale.
Figure 22. CS5342 THD+N versus Frequency
47 uF
100 uF
22 uF
10 uF
6.8 uF
4.7 uF
3.3 uF
2.2 uF
1 uF
5.6 uF
DS608F1 19
CS5342
5. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral compon ents over th e specified
bandwidth. Dynamic Range is a signal-to- noise ratio measurement over th e specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensu res tha t the distortion co mpone nts are below the noise level and do n ot affect the m easure-
ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-3 07 . Exp resse d in de cib els .
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral compon ents over th e specified
bandwidth (typically 10 Hz to 20 k Hz), including dis