1
Data sheet acquired from Harris Semiconductor
SCHS201A
Features
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative Edge Clocking
• Typical fMAX = 60 MHz at VCC = 5V, CL = 15pF,
TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC4020 and ’HCT4020 are 14-stage ripple-carry
binary counters. All counter stages are master-slave flip-
flops. The state of the stage advances one count on the
negative clock transition of each input pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Pinout
CD54HC4020, CD54HCT4020
(CERDIP)
CD74HC4020, CD74HCT4020
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC4020F -55 to 125 16 Ld CERDIP
CD54HC4020F3A -55 to 125 16 Ld CERDIP
CD74HC4020E -55 to 125 16 Ld PDIP
CD74HC4020M -55 to 125 16 Ld SOIC
CD54HCT4020F3A -55 to 125 16 Ld CERDIP
CD74HCT4020E -55 to 125 16 Ld PDIP
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die is available which meets all electrical
specifications. Please contact your local TI sales office or
customer service for ordering information.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q12
Q13
Q14
Q6
Q5
Q7
GND
Q4
VCC
Q10
Q8
Q9
MR
CP
Q1‘
Q11
February 1998 - Revised May 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2000, Texas Instruments Incorporated
CD54/74HC4020,
CD54/74HCT4020
High Speed CMOS Logic
14-Stage Binary Counter
[ /Title
(CD74
HC402
0,
CD74
HCT40
20)
/
Sub-
j
ect
(High
Speed
CMOS
2
Functional Diagram
9
5
6
12
1
3
2
15
10
INPUT Q1’
Q4
Q5
Q6
Q7
Q8
Q9
Q10
11
MASTER
Q11
Q12
Q13
Q14
7
4
13
14
8
GND
VCC
16
PULSES
RESET
BUFFERED
OUTPUTS
14-STAGE
RIPPLE
COUNTER
TRUTH TABLE
CP COUNT MR OUTPUT STATE
↑L No Change
↓L Advance to Next State
X H All Outputs Are Low
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓= Transition from High to Low.
CD54/74HC4020, CD54/74HCT4020
3
Logic Diagram
9
Q1’
CP Q
CP Q
I
R
Q’
CP Q
CP Q
2
R
CP Q
CP Q
3
R
CP Q
CP Q
4
R
7
Q4
CP Q
CP Q
5
R
5
Q5
CP Q
CP Q
6
R
4
Q6
CP Q
CP Q
7
R
6
Q7
CP Q
CP Q
8
R
13
Q8
CP Q
CP Q
9
R
12
Q9
CP Q
CP Q
10
R
14
Q10
CP Q
CP Q
12
R
15
Q11
CP Q
CP Q
11
R
1
Q12
CP Q
CP Q
13
R
2
Q13
CP Q
CP Q
14
R
3
Q14
CP
MR
11
10
CD54/74HC4020, CD54/74HCT4020
4
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - -V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
CD54/74HC4020, CD54/74HCT4020
5
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
MR 0.65
CP 0.5
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Prerequisite for Switching Specifications
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
HC TYPES
Maximum Input Pulse
Frequency fMAX 26-5-4-ns
4.5 30 - 25 - 20 - ns
6 35 - 29 - 24 - ns
Input Pulse Width tW2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns
6 14 - 17 - 20 - ns
Reset Removal Time tREM 2 50 - 65 - 75 - ns
4.5 10 - 13 - 15 - ns
6 9 - 11 - 13 - ns
CD54/74HC4020, CD54/74HCT4020
6
Reset Pulse Width tW2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns
6 14 - 17 - 20 - ns
HCT TYPES
Maximum Input Pulse
Frequency fMAX 4.5 25 - 20 - 16 - MHz
Input Pulse Width tW4.5 20 - 25 - 30 - ns
Reset Recovery Time tREC 4.5 10 - 13 - 15 - ns
Reset Pulse Width tW4.5 20 - 25 - 30 - ns
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay Time
(Figure 1) tPLH,
tPHL CL= 50pF 2 - - 140 - 175 - 210 ns
CP to Q1’ Output 4.5 - - 28 - 35 - 42 ns
CL=15pF 5 - 11 - - - - - ns
CL= 50pF 6 - - 24 - 30 - 36 ns
Qnto Qn+ 1 tPLH,
tPHL CL= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
CL=15pF 5 - 6 - - - - - ns
CL= 50pF 6 - - 13 - 16 - 19 ns
MR to QntPLH,
tPHL CL= 50pF 2 - - 170 - 215 - 255 ns
4.5 - - 34 - 43 - 51 ns
5 - 14 - - - - - ns
6 - - 29 - 37 - 43 ns
Output Transition Time
(Figure 1) tTLH,t
THL CL= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CIN CL= 50pF - - - 10 - 10 - 10 pF
Power Dissipation Capaci-
tance
(Notes 4, 5)
CPD CL=15pF 5 - 30 - - - - - pF
HCT TYPES
Propagation Delay Time
(Figure 2) tPLH,
tPHL CL= 50pF 4.5 - - 40 - 50 - 60 ns
CP to Q1’ Output CL=15pF 5 - 17 - - - - - ns
Qnto Qn+ 1 tPLH,
tPHL CL= 50pF 4.5 - - 15 - 19 - 22 ns
CL=15pF 5 - 6 - - - - - ns
MR to QntPLH,
tPHL CL= 50pF 4.5 - - 40 - 50 - 60 ns
CL=15pF 5 - 17 - - - - - ns
Prerequisite for Switching Specifications (Continued)
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
CD54/74HC4020, CD54/74HCT4020
7
Output Transition tTLH,t
THL CL= 50pF 4.5 - - 15 - 19 - 22 ns
Input Capacitance CIN CL=15pF - - - 10 - 10 - 10 pF
Power Dissipation Capaci-
tance
(Notes 4, 5)
CPD CL=15pF 5 - 30 - - - - - pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD = VCC2 fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
CLOCK 90% 50%
10% GND
VCC
trCLtfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V 1.3V
0.3V GND
3V
trCL= 6ns tfCL= 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
CD54/74HC4020, CD54/74HCT4020
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 2000, Texas Instruments Incorporated
