2003-2012 Microchip Technology Inc. DS21830E-page 1
25AA640A/25LC640A
Device Selection Table
Features:
• Max. Clock 10 MHz
• Low-Power CMOS Technology:
- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 1 A at 5.5V
• 8192 x 8-bit Organization
• 32 Byte Page
• Self-Timed Erase and Write Cycles (5 ms max.)
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential Read
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature Ranges Supported:
Description:
The Microchip Technology Inc. 25AA640A/25LC640A
(25XX640A*) are 64 kbit Serial Electrically Erasable
PROMs. The memory is accessed via a simple Serial
Peripheral Interface (SPI) compatible serial bus. The
bus signals required are a clock input (SCK) plus sep-
arate data in (SI) and data out (SO) lines. Access to the
device is controlled through a Chip Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25XX640A is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead MSOP, 8-lead TSSOP, DFN
and TDFN.
Package Types (not to scale)
Part Number VCC Range Page Size Temp. Ranges Packages
25LC640A 2.5-5.5V 32 Byte I,E P, SN, ST, MS, MF, MNY
25AA640A 1.8-5.5V 32 Byte I P, SN, ST, MS, MF, MNY
- Industrial (I): -40Cto +85C
- Automotive (E): -40°C to +125°C
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
PDIP/SOIC
(P, SN)
TSSOP/MSOP
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
(ST, MS)
X-Rotated TSSOP
HOLD
V
CC
CS
SO
1
2
3
4
8
7
6
5
SCK
SI
V
SS
WP
(X/ST)
DFN/TDFN
CS
SO
WP
VSS
HOLD
SCK
SI
5
6
7
8
4
3
2
1
VCC
(MF/MNY)
64K SPI Bus Serial EEPROM
* 25XX640A is used in this document as a generic part number
for the 25AA640A, 25LC640A devices.
25AA640A/25LC640A
DS21830E-page 2 2003-2012 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-40°C to 125°C
ESD protection on all pins..........................................................................................................................................4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E): T
A = -40°C to +125°C VCC = 2.5V to 5.5V
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
D001 VIH1High-level input
voltage
.7 VCC VCC +1 V
D002 VIL1Low-level input
voltage
-0.3 0.3 VCC VVCC2.7V
D003 VIL2-0.3 0.2 VCC VVCC < 2.7V
D004 VOL Low-level output
voltage
—0.4VIOL = 2.1 mA
D005 VOL —0.2VIOL = 1.0 mA, VCC < 2.5V
D006 VOH High-level output
voltage
VCC -0.5 — V IOH = -400 A
D007 ILI Input leakage current — ±1 ACS = VCC, VIN = VSS or VCC
D008 ILO Output leakage
current
—±1ACS = VCC, VOUT = VSS or VCC
D009 CINT Internal Capacitance
(all inputs and
outputs)
—7pFTA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note)
D010 ICC Read
Operating Current
—
—
5
2.5
mA
mA
VCC = 5.5V; FCLK = 10.0 MHz;
SO = Open
VCC = 2.5V; FCLK = 5.0 MHz;
SO = Open
D011 ICC Write —
—
5
3
mA
mA
VCC = 5.5V
VCC = 2.5V
D012 ICCS
Standby Current
—
—
5
1
A
A
CS = VCC = 5.5V, Inputs tied to VCC or
VSS, 125°C
CS = VCC = 5.5V, Inputs tied to VCC or
VSS, 85°C
Note: This parameter is periodically sampled and not 100% tested.
2003-2012 Microchip Technology Inc. DS21830E-page 3
25AA640A/25LC640A
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
1FCLK Clock frequency —
—
—
10
5
3
MHz
MHz
MHz
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
2T
CSS CS setup time 50
100
150
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
3T
CSH CS hold time 100
200
250
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
4T
CSD CS disable time 50 — ns —
5 Tsu Data setup time 10
20
30
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
6T
HD Data hold time 20
40
50
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
7T
RCLK rise time — 100 ns (Note 1)
8T
FCLK fall time — 100 ns (Note 1)
9T
HI Clock high time 50
100
150
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
10 TLO Clock low time 50
100
150
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
11 TCLD Clock delay time 50 — ns —
12 TCLE Clock enable time 50 — ns —
13 TVOutput valid from clock
low
—
—
—
50
100
160
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
14 THO Output hold time 0 — ns (Note 1)
15 TDIS Output disable time —
—
—
40
80
160
ns
ns
ns
4.5V Vcc 5.5V (Note 1)
2.5V Vcc 4.5V (Note 1)
1.8V Vcc 2.5V (Note 1)
16 THS HOLD setup time 20
40
80
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
25AA640A/25LC640A
DS21830E-page 4 2003-2012 Microchip Technology Inc.
TABLE 1-3: AC TEST CONDITIONS
17 THH HOLD hold time 20
40
80
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
18 THZ HOLD low to output
High-Z
30
60
160
—
—
—
ns
ns
ns
4.5V Vcc 5.5V (Note 1)
2.5V Vcc 4.5V (Note 1)
1.8V Vcc 2.5V (Note 1)
19 THV HOLD high to output valid 30
60
160
—
—
—
ns
ns
ns
4.5V Vcc 5.5V
2.5V Vcc 4.5V
1.8V Vcc 2.5V
20 TWC Internal write cycle time — 5 ms (NOTE 3)
21 — Endurance 1M — E/W
Cycles
(NOTE 2)
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
AC Waveform:
VLO = 0.2V —
VHI = VCC - 0.2V (Note 1)
VHI = 4.0V (Note 2)
CL = 100 pF —
Timing Measurement Reference Level
Input 0.5 VCC
Output 0.5 VCC
Note 1: For VCC 4.0V.
2: For VCC > 4.0V.
2003-2012 Microchip Technology Inc. DS21830E-page 5
25AA640A/25LC640A
FIGURE 1-1: HOLD TIMING
FIGURE 1-2: SERIAL INPUT TIMING
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
HOLD
17
16 16 17
19
18
Don’t Care 5
High-Impedance
n + 2 n + 1 n n-1
n
n + 2 n + 1 n nn - 1
CS
SCK
SI
SO
65
8
711
3
LSB in
MSB in
High-Impedance
12
Mode 1,1
Mode 0,0
2
4
CS
SCK
SO
10
9
13
MSB out ISB out
3
15
Don’t Care
SI
Mode 1,1
Mode 0,0
14
25AA640A/25LC640A
DS21830E-page 6 2003-2012 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 25XX640A is a 8192-byte serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using dis-
crete I/O lines programmed properly in firmware to
match the SPI protocol.
The 25XX640A contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred Most Significant
Byte (MSB) first, Least Significant Byte (LSB) last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX640A in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
2.2 Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25XX640A fol-
lowed by the 16-bit address, with the three MSBs of the
address being “don’t care” bits. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin. The data stored in the memory at the next
address can be read sequentially by continuing to pro-
vide clock pulses. The internal Address Pointer is auto-
matically incremented to the next higher address after
each byte of data is shifted out. When the highest
address is reached (1FFFh), the address counter rolls
over to address 0000h, allowing the read cycle to be
continued indefinitely. The read operation is terminated
by raising the CS pin (Figure 2-1).
2.3 Write Sequence
Prior to any attempt to write data to the 25XX640A, the
write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX640A. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE instruc-
tion, followed by the 16-bit address, with the three
MSBs of the address being “don’t care” bits, and then
the data to be written. Up to 32 bytes of data can be
sent to the device before a write cycle is necessary.
The only restriction is that all of the bytes must reside
in the same page.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 2-2 and Figure 2-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 2-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
Note: Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and, end at addresses that are
integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
2003-2012 Microchip Technology Inc. DS21830E-page 7
25AA640A/25LC640A
BLOCK DIAGRAM
FIGURE 2-1: READ SEQUENCE
SI
SO
SCK
CS
HOLD
WP
STATUS
Register
I/O Control Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
VCC
VSS
TABLE 2-1: INSTRUCTION SET
Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WRDI 0000 0100 Reset the write enable latch (disable write operations)
WREN 0000 0110 Set the write enable latch (enable write operations)
RDSR 0000 0101 Read STATUS register
WRSR 0000 0001 Write STATUS register
SO
SI
SCK
CS
0 234567891011 21222324252627282930311
0100000115 14 13 12 210
76543210
Instruction 16-bit Address
Data Out
High-Impedance
25AA640A/25LC640A
DS21830E-page 8 2003-2012 Microchip Technology Inc.
FIGURE 2-2: BYTE WRITE SEQUENCE
FIGURE 2-3: PAGE WRITE SEQUENCE
SO
SI
CS
9 1011 2122232425262728293031
0000000115 14 13 12 21076543210
Instruction 16-bit Address Data Byte
High-Impedance
SCK
0 23456718
Twc
SI
CS
9 1011 2122232425262728293031
0000000115 14 13 12 21076543210
Instruction 16-bit Address Data Byte 1
SCK
0 23456718
SI
CS
41 42 43 46 47
76543210
Data Byte n (32 max.)
SCK
32 34 35 36 37 38 3933 40
76543210
Data Byte 3
76543210
Data Byte 2
44 45
2003-2012 Microchip Technology Inc. DS21830E-page 9
25AA640A/25LC640A
2.4 Write Enable (WREN) and Write
Disable (WRDI)
The 25XX640A contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch and the WRDI will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
•WRDI instruction successfully executed
•WRSR instruction successfully executed
•WRITE instruction successfully executed
FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)
FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)
SCK
0 2345671
SI
High-Impedance
SO
CS
010000 01
SCK
0 2345671
SI
High-Impedance
SO
CS
010000 0
0
25AA640A/25LC640A
DS21830E-page 10 2003-2012 Microchip Technology Inc.
2.5 Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2: STATUS REGISTER
The Write-In-Process (WIP) bit indicates whether the
25XX640A is busy with a write operation. When set to
a ‘1’, a write is in progress, when set to a ‘0’, no write
is in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
The STATUS register can be continually read until the
CS is de-asserted.
FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)
7 654 3 2 1 0
W/R –––W/RW/R R R
WPEN X X X BP1 BP0 WEL WIP
W/R = writable/readable. R = read-only.
SO
SI
CS
9101112131415
11000000
7654 2 10
Instruction
Data from STATUS Register
High-Impedance
SCK
0 23456718
3
2003-2012 Microchip Technology Inc. DS21830E-page 11
25AA640A/25LC640A
2.6 Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS reg-
ister as shown in Table 2-2. The user is able to select
one of four levels of protection for the array by writing
to the appropriate bits in the STATUS register. The
array is divided up into four segments. The user has the
ability to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3: ARRAY PROTECTION
FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
BP1 BP0 Array Addresses
Write-Protected
00 none
01 upper 1/4
(1800h-1FFFh)
10 upper 1/2
(1000h-1FFFh)
11 all
(0000h-1FFFh)
SO
SI
CS
9101112131415
01000000
7654 210
Instruction Data to STATUS Register
High-Impedance
SCK
0 23456718
3
Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
25AA640A/25LC640A
DS21830E-page 12 2003-2012 Microchip Technology Inc.
2.7 Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
•CS
must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
2.8 Power-On State
The 25XX640A powers on in the following state:
• The device is in low-power Standby mode
(CS =1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1)
WPEN
(SR bit 7)
WP
(pin 3) Protected Blocks Unprotected Blocks STATUS Register
0xxProtected Protected Protected
10xProtected Writable Writable
110 (low) Protected Writable Protected
111 (high) Protected Writable Writable
x = don’t care
2003-2012 Microchip Technology Inc. DS21830E-page 13
25AA640A/25LC640A
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
3.2 Serial Output (SO)
The SO pin is used to transfer data out of the
25XX640A. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
3.3 Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the STA-
TUS register is disabled. All other operations function
normally. When WP is high, all functions, including
writes to the nonvolatile bits in the STATUS register
operate normally. If the WPEN bit is set, WP low during
a STATUS register write sequence will disable writing
to the STATUS register. If an internal write cycle has
already begun, WP going low will have no effect on the
write.
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25XX640A in a system with WP pin
grounded and still be able to write to the STATUS reg-
ister. The WP pin functions will be enabled when the
WPEN bit is set high.
3.4 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
3.5 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX640A. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX640A while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX640A must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
Name Pin
Number
X-Rotated
Pin Number Function
CS 1 3 Chip Select Input
SO 2 4 Serial Data Output
WP 3 5 Write-Protect Pin
VSS 4 6 Ground
SI 5 7 Serial Data Input
SCK 6 8 Serial Clock Input
HOLD 7 1 Hold Input
VCC 8 2 Supply Voltage
25AA640A/25LC640A
DS21830E-page 14 2003-2012 Microchip Technology Inc.
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
8-Lead MSOP (150 mil) Example:
XXXXXT
YWWNNN
5LCAI
7281L7
T/XXXNNN
XXXXXXXX
YYWW
8-Lead PDIP
8-Lead SOIC
XX/XXYYWW
XXXXXXXT
NNN
XXXX
TYWW
8-Lead TSSOP
NNN
I/P 1L7
25LC640A
0728
Example:
Example:
SN 0728
25L640AI
1L7
1L7
5LCA
I728
Example:
MSOP 1st Line Marking Codes
Device
25AA640A
25LC640A
std mark
TSSOP 1st Line Marking Codes
Device
25AA640A
25AA640AX
25LC640A
25LC640AX
std mark
5ACA
ACAX
5LCA
LCAX
5ACA
5LCA
3
e
3
e
3
e
XXXXXXX
8-Lead DFN-S (5x6x1 mm)
XXXXXXX
XXYYWW
NNN
Example:
5LC640A
E/MF
0728
IL7
TDFN 1
st Line Marking
Device
25AA640A-I
25LC640A-E
std mark
C81
C85
8-Lead 2x3 TDFN Example:
XXX
YWW
NN
C81
828
17
25LC640A-I C84
2003-2012 Microchip Technology Inc. DS21830E-page 15
25AA640A/25LC640A
Note: Custom marking available.
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
25AA640A/25LC640A
DS21830E-page 16 2003-2012 Microchip Technology Inc.
!"#
$%& "'($)*+
,
,
φ
NOTE 2
A3
A2
A1
A
NOTE 1
NOTE 1
EXPOSED
PAD
BOTTOM VIEW
12
D2
21
E2
K
L
N
e
b
E
E1
D
D1
N
TOP VIEW
2003-2012 Microchip Technology Inc. DS21830E-page 17
25AA640A/25LC640A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
25AA640A/25LC640A
DS21830E-page 18 2003-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2012 Microchip Technology Inc. DS21830E-page 19
25AA640A/25LC640A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
25AA640A/25LC640A
DS21830E-page 20 2003-2012 Microchip Technology Inc.
'--.// !'#
,
,
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
2003-2012 Microchip Technology Inc. DS21830E-page 21
25AA640A/25LC640A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
25AA640A/25LC640A
DS21830E-page 22 2003-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2012 Microchip Technology Inc. DS21830E-page 23
25AA640A/25LC640A
"0-"112.34/ !"0'%#
,
25AA640A/25LC640A
DS21830E-page 24 2003-2012 Microchip Technology Inc.
*5-"51-"0-"*636 !*""0#
,
,
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
2003-2012 Microchip Technology Inc. DS21830E-page 25
25AA640A/25LC640A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
25AA640A/25LC640A
DS21830E-page 26 2003-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2012 Microchip Technology Inc. DS21830E-page 27
25AA640A/25LC640A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
25AA640A/25LC640A
DS21830E-page 28 2003-2012 Microchip Technology Inc.
7./38 !*#
,
2003-2012 Microchip Technology Inc. DS21830E-page 29
25AA640A/25LC640A
APPENDIX A: REVISION HISTORY
Revision A (9/2003)
Initial Release.
Revision B (12/2003)
Corrections to Section 1.0, Electrical Characteristics.
Revision C (9/2007)
Features and Description, removed reference to Pb-
free packages; Revise Table 1-2: AC Characteristics,
parameters 7 and 8; Updated Packing Information/
Package Drawings; Add DFN Package; Removed
trademark from SPI.
Revision D (10/2008)
Added TDFN Package; Updated Package Drawings.
Revision E (02/2012)
Add text to Section 2.5.
25AA640A/25LC640A
DS21830E-page 30 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21830E-page 31
25AA640A/25LC640A
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
25AA640A/25LC640A
DS21830E-page 32 2003-2012 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO: Technical Publications Manager
RE: Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21830E25AA640A/25LC640A
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2003-2012 Microchip Technology Inc. DS21830E-page 33
25AA640A/25LC640A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTape & Reel
Device
Device: 25AA640A =
25LC640A =
25AA640AX =
25LC640AX =
64k-bit, 1.8V, SPI Serial EEPROM
64k-bit, 2.5V, SPI Serial EEPROM
64k-bit, 1.8V, SPI Serial EEPROM in alternate
pinout (ST only)
64k-bit, 2.5V, SPI Serial EEPROM
in alternate pinout (ST only)
Tape & Reel: Blank =
T=
Standard packaging
Tap e & R e e l
Temperature
Range:
I=
E=
-40C to+85C
-40C to+125C
Package: MS =
P=
SN =
ST =
MF =
MNY(1) =
Plastic MSOP (Micro Small Outline), 8-lead
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (3.90 mm body), 8-lead
TSSOP (4.4 mm body), 8-lead
DFN (5x6), 8-lead
TDFN (2x3), 8-lead
Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.
Examples:
a) 25AA640A-I/MS = 64 kbit, 1.8V Serial
EEPROM, Industrial temp., MSOP
package
b) 25AA640AT-I/SN = 6 kbit, 1.8V Serial
EEPROM, Industrial temp., Tape & Reel, SOIC
package
c) 25LC640AT-E/SN = 64 kbit, 2.5V Serial
EEPROM, Extended temp., Tape & Reel, SOIC
package
d) 25LC640AT-I/ST = 64 kbit, 2.5V Serial
EEPROM, Industrial temp., Tape & Reel,
TSSOP package
e) 25LC640AXT-I/ST = 64 kbit, 2.5V Serial
EEPROM, Industrial temp., Tape & Reel,
Rotated pinout, TSSOP package
–
X
Temp Range
25AA640A/25LC640A
DS21830E-page 34 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21830E-page 35
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620760369
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21830E-page 36 2003-2012 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
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Fax: 630-285-0075
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Tel: 216-447-0464
Fax: 216-447-0643
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Tel: 972-818-7423
Fax: 972-818-2924
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Tel: 248-538-2250
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Tel: 317-773-8323
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Tel: 905-673-0699
Fax: 905-673-6509
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Asia Pacific Office
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Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
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Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
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Tel: 86-24-2334-2829
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Tel: 86-755-8203-2660
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Tel: 91-80-3090-4444
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Fax: 82-2-558-5932 or
82-2-558-5934
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Worldwide Sales and Service
11/29/11
