IDT74FCT163601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS IDT74FCT163601A DESCRIPTION: FEATURES: The FCT163601/A 18-bit registered transceiver is built using advanced dual metal CMOS technology. These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the Abus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. The FCT163601 has series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors. * 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended Range W typ. static) * CMOS power levels (0.4 * Rail-to-rail output swing for increased noise margin * Low Ground Bounce (0.3V typ.) * Inputs (except I/O) can be driven by 3.3V or 5V components * Available in TSSOP package FUNCTIONAL BLOCK DIAGRAM OEAB CLKENAB CLKAB LEAB LEBA CLKBA CLKENBA OEBA A1 1 56 55 2 28 30 29 27 CE 1D C1 CLK 3 54 B1 CE 1D C1 CLK TO 17 OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2004 1 (c) 2004 Integrated Device Technology, Inc. DSC-3251/7 IDT74FCT163601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description Max Unit OEAB 1 56 CLKENAB VTERM(2) Terminal Voltage with Respect to GND -0.5 to +4.6 V LEAB 2 55 CLKAB VTERM(3) Terminal Voltage with Respect to GND -0.5 to 7 V A1 3 54 B1 VTERM(4) Terminal Voltage with Respect to GND -0.5 to VCC+0.5 V GND 4 53 GND TSTG Storage Temperature -65 to +150 C IOUT DC Output Current -60 to +60 mA A2 5 52 B2 A3 6 51 B3 VCC 7 50 VCC A4 8 49 B4 A5 9 48 B5 A6 10 47 B6 GND 11 46 GND A7 12 45 B7 A8 13 44 B8 A9 14 43 B9 A10 15 42 B10 A11 16 41 B11 A12 17 40 B12 GND 18 39 GND A13 19 38 B13 A14 20 37 B14 A15 21 36 B15 VCC 22 35 VCC A16 23 34 B16 A17 24 33 B17 GND 25 32 GND A18 26 31 B18 OEBA 27 30 CLKBA LEBA 28 29 CLKENBA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Outputs and I/O terminals. CAPACITANCE (TA = +25C, F = 1.0MHz) Symbol CLKENBA B to A Clock Enable Input (Active LOW) Typ. Max. Unit Input Capacitance VIN = 0V 3.5 6 pF COUT Output Capacitance VOUT = 0V 3.5 8 pF FUNCTION TABLE(1,4) CLKENAB X X X H L L L L PIN DESCRIPTION Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs A to B Clock Enable Input (Active LOW) Conditions CIN NOTE: 1. This parameter is measured at characterization but not tested. TSSOP TOP VIEW Pin Names OEAB OEBA LEAB LEBA CLKAB CLKBA Ax Bx CLKENAB Parameter(1) OEAB H L L L L L L L Inputs LEAB X H H L L L L L CLKAB X X X X L H A X L H X L H X X Outputs B Z L H B0(2) L H B0(2) B0(3) NOTES: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA and CLKENBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-impedance = LOW-to-HIGH Transition 2 IDT74FCT163601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 2.7V to 3.6V Symbol VIH Test Conditions(1) Min. Typ.(2) Max. Unit 2 -- 5.5 V 2 -- VCC+0.5 -0.5 -- 0.8 VI = 5.5V -- -- 1 Input HIGH Current (I/O pins) VI = VCC -- -- 1 Input LOW Current (Input pins) VI = GND -- -- 1 Input LOW Current (I/O pins) VI = GND -- -- 1 VO = VCC -- -- 1 VO = GND -- -- 1 -- -0.7 -1.2 V -36 -60 -110 mA mA Parameter Input HIGH Level (Input pins) Guaranteed Logic HIGH Level Input HIGH Level (I/O pins) VIL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level IIH Input HIGH Current (Input pins) IIL IOZH High Impedance Output Current IOZL (3-State Output pins) VIK Clamp Diode Voltage IODH Output HIGH Current VCC = Max. VCC = Max. VCC = Min., IIN = -18mA VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V (3) (3) IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V VOH Output HIGH Voltage VCC = Min. IOH = -0.1mA VIN = VIH or VIL IOH = -3mA VCC = 3V IOH = -8mA 50 90 200 VCC-0.2 -- -- 2.4 3 -- 3 -- (5) 2.4 V A A V VIN = VIH or VIL VOL Output LOW Voltage VCC = Min. IOL = 0.1mA -- -- 0.2 VIN = VIH or VIL IOL = 16mA -- 0.2 0.4 IOL = 24mA -- 0.3 0.55 IOL = 24mA -- 0.3 0.5 -60 -135 -240 mA -- 150 -- mV -- 0.1 10 A VCC = 3V V VIN = VIH or VIL (4) IOS Short Circuit Current VH Input Hysteresis ICCL ICCH ICCZ Quiescent Power Supply Current VCC = Max., VO = GND(3) -- VCC = Max. VIN = GND or VCC NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC-0.6V at rated current. 3 IDT74FCT163601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions(1) ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = VCC -0.6V(3) ICCD Dynamic Power Supply Current(4) VCC = Max. Outputs Open OEAB = VCC, OEBA = GND One Input Toggling 50% Duty Cycle IC Total Power Supply Current(6) Min. Typ.(2) Max. Unit -- 2 30 A VIN = VCC VIN = GND -- 60 100 A/ MHz VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC, OEBA = GND LEBA = GND CLKENBA = GND fi = 5MHz One Bit Toggling VIN = VCC VIN = GND -- 0.6 1 mA VIN = VCC -0.6V VIN = GND -- 0.6 1 VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC, OEBA = GND LEBA = GND CLKENBA = GND fi = 2.5MHz Eighteen Bits Toggling VIN = VCC VIN = GND -- 3 5(5) VIN = VCC -0.6V VIN = GND -- 3 5.3(5) NOTES: 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + DICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 4 IDT74FCT163601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tSU tH tH tW tW tSK(o) Parameter CLKAB or CLKBA frequency(3) Propagation Delay Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time HIGH or LOW Ax to CLKAB, Bx to CLKBA Hold Time HIGH or LOW Ax to CLKAB, Bx to CLKBA Set-up Time HIGH or LOW Clock LOW Ax to LEAB, Bx to LEBA Clock HIGH Set-up Time, CLKEN to CLK Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA Hold Time, CLKEN to CLK LEAB or LEBA Pulse Width HIGH CLKAB or CLKBA Pulse Width HIGH or LOW Output Skew(4) Condition(1) CL = 50pF RL = 500 Min.(2) -- 1.5 Max. 150 5.5 Unit ns ns 1.5 6.2 ns 1.5 6.3 ns 1.5 6.5 ns 1.5 5.2 ns 3 -- ns 0 -- ns 2.5 2 2.5 1 -- -- -- -- ns 0 2.5 3 -- -- -- -- 0.5 ns ns ns ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. 5 ns ns IDT74FCT163601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS SWITCH POSITION 6v Open V CC 500 GND V OUT VIN Pulse Generator D.U.T. 50pF RT 500 CL Test Switch Open Drain Disable Low Enable Low 6V Disable High Enable High GND All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Test Circuits for All Outputs DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH Pulse Width Set-up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V CONTROL INPUT 1.5V OUTPUT NORMALLY LOW 3V 1.5V 0V OUTPUT NORMALLY HIGH Propagation Delay SWITCH 6V tPZH SWITCH GND 0V tPLZ tPZL VOH 1.5V VOL 3V 3V 1.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC. 6 IDT74FCT163601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT FCT XXX XX Family Temp. Range XXXX Device Type X Package CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 PA Thin Shrink Small Outline Package 601A Non-Inverting 18-Bit Registered Transceiver 163 Double-Density 3.3Volt 74 - 40C to +85C for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 7 for Tech Support: logichelp@idt.com