Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 CC2564MODN Bluetooth(R) Host Controller Interface (HCI) Module 1 Device Overview 1.1 Features 1 * Single-Chip Solution Integrating Bluetooth Basic Rate (BR)/Enhanced Data Rate (EDR)/Low Energy (LE) Features * Fully Certified Bluetooth 4.1 Module - Compliant Up to the HCI Layer - FCC (Z64-2564N)/IC (451I-2564N) Modular Grant with External Chip Antenna (see Section 6.2.1.3, Antenna) - CE Certified as Summarized in the Declaration of Conformity - Bluetooth 4.1 Controller Subsystem Qualified (QDID 55257) * BR/EDR Features Include: - Up to 7 Active Devices - Scatternet: Up to 3 Piconets Simultaneously, 1 as Master and 2 as Slaves - Up to 2 SCO Links on the Same Piconet - Support for All Voice Air-Coding - Continuously Variable Slope Delta (CVSD), A-Law, -Law, and Transparent (Uncoded) * Assisted Mode for HFP 1.6 Wideband Speech (WBS) Profile or A2DP Profile to Reduce Host Processing and Power * LE Features Include: - Support of Up to 10 Simultaneous Connections - Multiple Sniff Instances Tightly Coupled to Achieve Minimum Power Consumption - Independent Buffering for LE Allows Large Numbers of Multiple Connections without Affecting BR/EDR Performance. - Built-In Coexistence and Prioritization Handling for BR/EDR and LE * Flexibility for Easy Stack Integration and Validation Into Various Microcontrollers, Such as MSP430TM and ARM(R) Cortex(R)-M3 and Cortex(R)-M4 MCUs * Highly Optimized for Design into Small Form Factor Systems: - Single-Ended 50- RF Interface - Module Footprint: 33 Terminals, 0.9-mm Pitch, 1.2 * * * * * * * * * * * * * 7 mm x 7 mm x 1.4 mm Best-in-Class Bluetooth (RF) Performance (TX Power, RX Sensitivity, Blocking) - Class 1.5 TX Power Up to +10 dBm - -93 dbm Typical RX Sensitivity - Improved Adaptive Frequency Hopping (AFH) Algorithm with Minimum Adaptation Time - Provides Longer Range, Including 2x Range Over Other BLE-Only Solutions Advanced Power Management for Extended Battery Life and Ease of Design: - On-Chip Power Management, Including Direct Connection to Battery - Low Power Consumption for Active, Standby, and Scan Bluetooth Modes - Shutdown and Sleep Modes to Minimize Power Consumption Physical Interfaces: - UART Transport Layer with Maximum Rate of 4 Mbps - Three-Wire UART Transport Layer with Maximum Rate of 4 Mbps - Fully Programmable Digital PCM-I2S Codec Interface CC256x Bluetooth Hardware Evaluation Tool: PCBased Application to Evaluate RF Performance of the Device and Configure Service Pack Lead-Free Design Compliant with RoHS Requirements Built-In CC2564B Single-Chip Bluetooth Device Fully Compliant with Bluetooth and EDR Supports Class 1.5 (High-Output Power) Applications Small Size with Low Power Consumption Supports Maximum Bluetooth Data Rates Over HCI UART Interface Supports Multiple Bluetooth Profiles with Enhanced QoS (Mono and Stereo) Assisted A2DP (No Host Processing Required) Applications Mobile Accessories Sports and Fitness Applications Wireless Audio Solutions * * Remote Controls Toys 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 1.3 www.ti.com Description The CC2564MODN TI Bluetooth HCI module is a complete Bluetooth BR/EDR/LE HCI solution that reduces design effort and enables fast time to market. Based on TI's seventh-generation Bluetooth core, the HCI module provides a product-proven solution that is Bluetooth 4.1 compliant. When coupled with a microcontroller unit (MCU), the HCI module provides best-in-class RF performance. TI's power-management hardware and software algorithms provide significant power savings in all commonly used Bluetooth BR/EDR/LE modes of operation. With transmit power and receive sensitivity, this solution provides a best-in-class range of about 2x, compared to other BLE-only solutions. A royalty-free software Bluetooth stack available from TI is preintegrated with TI's MSP430 and ARM Cortex-M3 and Cortex-M4 MCUs. The stack is also available for made for iPod(R) (MFi) solutions and on other MCUs through TI's partner Stonestreet One. Some of the profiles supported today include: serial port profile (SPP), advanced audio distribution profile (A2DP), human interface device (HID), and several BLE profiles (these profiles vary based on the supported MCU). In addition to software, this solution consists of a reference design with a low BOM cost. For more information on TI's wireless platform solutions for Bluetooth, see TI's CC256x wiki. Device Information (1) PACKAGE BODY SIZE CC2564MODNCMOET PART NUMBER MOE (33) 7.1 mm x 7.1 mm CC2564MODNCMOER MOE (33) 7.1 mm x 7.1 mm (1) For more information on these devices, see Section 8, Mechanical, Packaging, and Orderable Information space 1.4 Functional Block Diagram Figure 1-1 shows a functional block diagram of the device. VDD_IN(VBAT) VDD_IO Bluetooth ANT CC2564MODN BT_RF filter UART PCM CC2564B device nSHUTD 32.768-kHz slow clock 38.4 MHz XTAL SWRS160-001 Figure 1-1. Functional Block Diagram 2 Device Overview Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Table of Contents 1 2 3 4 5 Device Overview ......................................... 1 5.4 Bluetooth Transport Layers ......................... 18 1.1 Features .............................................. 1 5.5 Host Controller Interface 1.2 Applications ........................................... 1 5.6 Digital Codec Interface .............................. 20 1.3 Description ............................................ 2 5.7 Assisted Modes 1.4 Functional Block Diagram ............................ 2 6 Revision History ......................................... 3 Terminal Configuration and Functions .............. 4 .......................................... 3.1 Pin Diagram 3.2 Pin Attributes ......................................... 5 4 ............................................ 6 4.1 Absolute Maximum Ratings .......................... 6 4.2 Handling Ratings ..................................... 6 4.3 Power-On Hours ...................................... 6 4.4 Recommended Operating Conditions ................ 6 4.5 Power Consumption Summary ....................... 7 4.6 Electrical Characteristics ............................. 8 4.7 Timing and Switching Characteristics ................ 8 Detailed Description ................................... 17 5.1 Overview ............................................ 17 5.2 Bluetooth BR/EDR Description...................... 17 5.3 Bluetooth LE Description ............................ 17 7 Specifications 8 ............................ ..................................... 18 22 Applications, Implementation, and Layout........ 28 ..................... .............................................. 6.3 Soldering Recommendations ....................... Device and Documentation Support ............... 7.1 Device Certification and Qualification ............... 7.2 Device Support ...................................... 7.3 Community Resources .............................. 7.4 Trademarks.......................................... 7.5 Electrostatic Discharge Caution ..................... 7.6 Glossary ............................................. 6.1 Reference Design Schematics 28 6.2 Layout 28 36 37 37 37 38 38 38 38 Mechanical, Packaging, and Orderable Information .............................................. 39 8.1 Module Outline ...................................... 39 8.2 Mechanical Data 8.3 Packaging and Ordering .................................... ............................ 40 41 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (March 2014) to Revision B * * * * * * * * * * * * * * * * * Page Changed organizational flow of document in compliance with Data Sheet Council standard .............................. 1 Changed instances of "H4 Protocol - 4-Wire UART" to "UART Transport Layer" ........................................... 1 Changed instances of "H5 Protocol - 3-Wire UART" to "Three-Wire UART Transport Layer" ............................ 1 Changed operating ambient temperature range from "-40 to 85" to "-20 to 70" in Section 4.1, Absolute Maximum Ratings ................................................................................................................................ 6 Added minimum values to Section 4.2, Handling Ratings ...................................................................... 6 Added Section 4.3, Power-On Hours .............................................................................................. 6 Changed "A3DP source" and "A3DP sink" to "Assisted A2DP source" and "Assisted A2DP sink" in Section 4.5.2.1, Current Consumption for Different Bluetooth BR/EDR Scenarios .......................................... 7 Split the "Connected (master and slave role)" cell into two cells in Section 4.5.2.2, Current Consumption for Different LE Scenarios: One for master and one for slave role. ............................................................... 8 Deleted CLK_REQ_OUT and IO1 from Table 4-2 .............................................................................. 10 Deleted "25C, 40C, 85C" from the Min, Typ, and Max column headers in Section 4.7.4.1.3, Bluetooth Transmitter--EDR .................................................................................................................. 14 Changed bitpool range of Assisted A2DP sink from "TBD" to "2-54" in Table 5-10 ........................................ 25 Changed Section 6.1 title from Reference Design ............................................................................. 28 Changed Reference Schematic .................................................................................................. 28 Added Section 6.2, Layout ......................................................................................................... 28 Added Section 6.3, Soldering Recommendations .............................................................................. 36 Added Section 7.1, Device Certification and Qualification ..................................................................... 37 Added Table 8-3 ..................................................................................................................... 41 Revision History Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 3 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com 3 Terminal Configuration and Functions 3.1 Pin Diagram 21 22 23 24 GND 13 15 16 17 14 BT_ANT AUD_OUT GND AUD_IN nSHUTD 20 GND 19 VDD_IO 18 Figure 3-1 shows the top view of the terminal designations. VDD_IN AUD_CLK NC AUD_FSYNC NC NC GND TX_DBG CC2564MODN SLOW_CLK_IN 10 9 8 7 NC GND 11 6 HCI_RTS 4 5 HCI_RX 3 2 HCI_TX GND HCI_CTS GNDPAD GNDPAD GNDPAD GNDPAD GNDPAD GNDPAD GNDPAD GNDPAD GNDPAD 1 25 26 27 28 29 30 31 32 33 12 SWRS160-006 Figure 3-1. Pin Diagram (Top View) 4 Terminal Configuration and Functions Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com 3.2 SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Pin Attributes Table 3-1 describes the terminal functions. Table 3-1. Pin Attributes No. ESD (1) (V) Pull at Reset Def. Dir. (2) I/O Type (3) HCI_CTS 1 750 PU I 8 mA HCI UART clear-to-send The device can send data when HCI_CTS is low. HCI_TX 2 750 PU O 8 mA HCI UART data transmit HCI_RX 3 750 PU I 8 mA HCI UART data receive HCI_RTS 4 750 PU O 8 mA HCI UART request-to-send Host can send data when HCI_RTS is low. GND 5 1000 NC 6 GND 7 1000 SLOW_CLK_IN 8 1000 GND 9 1000 NC 10 O Not connected NC 11 O Not connected VDD_IN 12 I Main power supply for the module GND 13 BT_ANT 14 GND 15 nSHUTD 16 GND 17 VDD_IO 18 1000 AUD_IN 19 500 PD AUD_OUT 20 500 PD AUD_CLK 21 500 PD AUD_FSYNC 22 500 PD I/O NC 23 500 PD TX_DBG 24 1000 PU GNDPAD 25 1000 Ground GNDPAD 26 1000 Ground GNDPAD 27 1000 Ground GNDPAD 28 1000 Ground GNDPAD 29 1000 Ground GNDPAD 30 1000 Ground GNDPAD 31 1000 Ground GNDPAD 32 1000 Ground GNDPAD 33 1000 Ground Name (1) (2) (3) Description Ground I Not connected Ground I 32.768-kHz clock in Fail-safe Ground Ground 500 IO Bluetooth RF I/O Ground PD I Shutdown input (active low) Ground I I I/O power supply (1.8 V nominal) 4 mA PCM data input Fail-safe O 4 mA PCM data output Fail-safe I/O HY, 4 mA PCM clock Fail-safe 4 mA PCM frame sync Fail-safe I/O 4 mA Not Connected O 2 mA TI internal debug messages. TI recommends leaving a test point. ESD: Human Body Model (HBM). JEDEC 22-A114 2-wire method. CDM: All pins pass 500 V except RF_IO, which passes 400 V. I = input; O = output; I/O = bidirectional I/O Type: Digital I/O cells. HY = input hysteresis, current = typical output current Terminal Configuration and Functions Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 5 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com 4 Specifications Unless otherwise indicated, all measurements are taken at the device pins of the TI test evaluation board (EVB). All specifications are over process, voltage, and temperature, unless otherwise indicated. 4.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise indicated). All parameters are measured as follows: VDD_IN = 3.6 V and VDD_IO = 1.8 V (unless otherwise indicated). Parameters (1) VDD_IN Value Unit -0.5 to 4.8 V (2) -0.5 to 2.145 V -0.5 to 2.1 V Supply voltage range VDD_IO Input voltage to analog pins (3) Input voltage to all other pins -0.5 to (VDD_IO + 0.5) V -20 to 70 C 10 dBm Operating ambient temperature range (4) Bluetooth RF inputs (1) (2) (3) (4) 4.2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Section 6.1, Reference Design for Power and Radio Connections. Analog pins: BT_RF, XTALP, and XTALM The module supports a temperature range of -20C to 70C because of the operating conditions of the crystal. Handling Ratings MIN TYP MAX UNIT C Tstg Storage temperature range -55 125 ESD stress voltage (1) Human body model (HBM) (2) Device -500 +500 Charged device model (CDM) (3) Device -500 +500 (1) (2) (3) 4.3 ESD measures device sensitivity and immunity to damage caused by electrostatic discharges into the device. The level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible, if necessary precautions are taken. Pins listed as 1000 V can actually have higher performance. The level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 250-V CDM is possible, if necessary precautions are taken. Pins listed as 250 V can actually have higher performance. Power-On Hours Device Conditions Power-On Hours Duty Cycle = 25% active and 75% sleep Tambient = 70C CC2564MODN 4.4 V 15,400 Hours (7 Years) Recommended Operating Conditions Sym Min Max Unit Power supply voltage Rating Condition VDD_IN 2.2 4.8 V I/O power supply voltage VDD_IO 1.62 1.92 V V High-level input voltage Default VIH 0.65 x VDD_IO VDD_IO Low-level input voltage Default VIL 0 0.35 x VDD_IO V tr and tf 1 10 ns 1 2.5 ns 400 mV 70 C I/O input rise and all times,10% to 90% -- asynchronous mode I/O input rise and fall times, 10% to 90% -- synchronous mode (PCM) Voltage dips on VDD_IN (VBAT) duration = 577 s to 2.31 ms, period = 4.6 ms Maximum ambient operating temperature (1) 6 (1) -20 A crystal-based solution is limited by the temperature range required of the crystal to meet 20 ppm. Specifications Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com 4.5 SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Power Consumption Summary 4.5.1 Static Current Consumption Typ Max Unit Shutdown mode (1) Operational Mode Min 1 7 A Deep sleep mode (2) 40 105 A Total I/O current consumption in active mode 1 mA Continuous transmission--GFSK (3) 107 mA Continuous transmission--EDR (4) (5) 112.5 mA (1) (2) (3) (4) (5) VBAT + VIO + VSHUTDOWN VBAT + VIO At maximum output power (10 dBm) At maximum output power (8 dBm) Both /4 DQPSK and 8DPSK 4.5.2 Dynamic Current Consumption 4.5.2.1 Current Consumption for Different Bluetooth BR/EDR Scenarios Conditions: VDD_IN = 3.6 V, 25C, nominal unit, 8-dBm output power Master and Slave Average Current Unit Synchronous connection oriented (SCO) link HV3 Operational Mode Master and slave 13.7 mA Extended SCO (eSCO) link EV3 64 kbps, no retransmission Master and slave 13.2 mA eSCO link 2-EV3 64 kbps, no retransmission Master and slave 10 mA GFSK full throughput: TX = DH1, RX = DH5 Master and slave 40.5 mA EDR full throughput: TX = 2-DH1, RX = 2-DH5 Master and slave 41.2 mA EDR full throughput: TX = 3-DH1, RX = 3-DH5 Master and slave 41.2 mA Sniff, four attempts, 1.28 seconds Master and slave 145 A Page or inquiry scan 1.28 seconds, 11.25 ms Master and slave 320 A Page (1.28 seconds) and inquiry (2.56 seconds) scans, 11.25 ms Master and slave 445 A A2DP source Master 13.9 mA A2DP sink Master 15.2 mA Assisted A2DP source Master 16.9 mA Assisted A2DP sink Master 18.1 mA Assisted WBS EV3; retransmit effort = 2; maximum latency = 8 ms Master and slave 17.5 and 18.5 mA Assisted WBS 2EV3; retransmit effort = 2; maximum latency = 12 ms Master and slave 11.9 and 13 mA Specifications Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 7 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 4.5.2.2 www.ti.com Current Consumption for Different LE Scenarios Conditions: VDD_IN = 3.6 V, 25C, nominal unit, 8-dBm output power Mode Description Average Current Unit Advertising, nonconnectable Advertising in all three channels 1.28-seconds advertising interval 15 bytes advertise data 114 A Advertising, discoverable Advertising in all three channels 1.28-seconds advertising interval 15 bytes advertise data 138 A Scanning Listening to a single frequency per window 1.28-seconds scan interval 11.25-ms scan window 324 A Connected (master role) 500-ms connection interval 0-ms slave connection latency Empty TX and RX LL packets Connected (slave role) 4.6 A 199 (slave) Electrical Characteristics Rating Condition High-level output voltage, VOH Low-level output voltage, VOL I/O input impedance Output rise and fall times, 10% to 90% (digital pins) I/O pull currents PCM-I2S bus, TX_DBG All others 4.7 169 (master) Min Max At 2, 4, 8 mA 0.8 x VDD_IO VDD_IO At 0.1 mA VDD_IO - 0.2 VDD_IO At 2, 4, 8 mA 0 0.2 x VDD_IO At 0.1 mA 0 0.2 Resistance 1 Unit V V M Capacitance 5 pF CL = 20 pF 10 ns PU typ = 6.5 3.5 9.7 PD typ = 27 9.5 55 PU typ = 100 50 300 PD typ = 100 50 360 A A Timing and Switching Characteristics 4.7.1 Device Power Supply The power-management hardware and software algorithms of the TI Bluetooth HCI module provide significant power savings, which is a critical parameter in an MCU-based system. The power-management module is optimized for drawing extremely low currents. 4.7.1.1 Power Sources The TI Bluetooth HCI module requires two power sources: * VDD_IN: main power supply for the module * VDD_IO: power source for the 1.8-V I/O ring The HCI module includes several on-chip voltage regulators for increased noise immunity and can be connected directly to the battery. 4.7.1.2 Power Supply Sequencing The device includes the following power-up requirements (see Figure 4-1): 8 Specifications Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com * * * SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 nSHUTD must be low. VDD_IN and VDD_IO are don't-care when nSHUTD is low. However, signals are not allowed on the I/O pins if I/O power is not supplied, because the I/Os are not fail-safe. Exceptions are SLOW_CLK_IN and AUD_xxx, which are fail-safe and can tolerate external voltages with no VDD_IO and VDD_IN. VDD_IO and VDD_IN must be stable before releasing nSHUTD. The slow clock must be stable within 2 ms of nSHUTD going high. The device indicates that the power-up sequence is complete by asserting RTS low, which occurs up to 100 ms after nSHUTD goes high. If RTS does not go low, the device is not powered up. In this case, ensure that the sequence and requirements are met. Shut down before VDD_IO removed 20 S max nSHUTD VDD_IO VDD_IN 2 ms max slow clock 100 ms HCI_RTS CC256x ready SWRS160-008 Figure 4-1. Power-Up and Power-Down Sequence 4.7.1.3 Power Supplies and Shutdown - Static States The nSHUTD signal puts the device in ultra-low power mode and performs an internal reset to the device. The rise time for nSHUTD must not exceed 20 s; nSHUTD must be low for a minimum of 5 ms. To prevent conflicts with external signals, all I/O pins are set to the high-impedance (Hi-Z) state during shutdown and power up of the device. The internal pull resistors are enabled on each I/O pin, as described in Section 3.2. Table 4-1 describes the static operation states. Table 4-1. Power Modes VDD_IN (1) (1) VDD_IO (1) nSHUTD (1) PM_MODE Comments 1 None None Asserted Shut down I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins. 2 None None Deasserted Not allowed I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins. 3 None Present Asserted Shut down I/Os are defined as 3-state with internal pullup or pulldown enabled. The terms None or Asserted can imply any of the following conditions: directly pulled to ground or driven low, pulled to ground through a pulldown resistor, or left NC or floating (high-impedance output stage). Specifications Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 9 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com Table 4-1. Power Modes (continued) VDD_IN (1) VDD_IO (1) nSHUTD (1) PM_MODE Comments 4 None Present Deasserted Not allowed I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins. 5 Present None Asserted Shut down I/O state is undefined. 6 Present None Deasserted Not allowed I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins. 7 Present Present Asserted Shut down I/Os are defined as 3-state with internal pullup or pulldown enabled. 8 Present Present Deasserted Active 4.7.1.4 See Section 4.7.1.4, I/O States in Various Power Modes I/O States in Various Power Modes CAUTION Some device I/Os are not fail-safe (see Section 3.2, Pin Attributes). Fail-safe means that the pins do not draw current from an external voltage applied to the pin when I/O power is not supplied to the device. External voltages are not allowed on these I/O pins when the I/O supply voltage is not supplied because of possible damage to the device. Table 4-2 lists the I/O states in various power modes. Table 4-2. I/O States in Various Power Modes I/O Name Shut Down (1) Default Active (1) Deep Sleep (1) I/O State Pull I/O State Pull I/O State Pull HCI_RX Z PU I PU I PU HCI_TX Z PU O-H - O - HCI_RTS Z PU O-H - O - HCI_CTS Z PU I PU I PU AUD_CLK Z PD I PD I PD AUD_FSYNC Z PD I PD I PD AUD_IN Z PD I PD I PD AUD_OUT Z PD Z PD Z PD TX_DBG Z PU O - (1) I = input, O = output, Z = Hi-Z, -- = no pull, PU = pullup, PD = pulldown, H = high, L = low 4.7.1.5 nSHUTD Requirements Sym Min Max Unit Operation mode level (1) Parameter VIH 1.42 1.98 V Shutdown mode level (1) VIL 0 0.4 V Minimum time for nSHUT_DOWN low to reset the device Rise and fall times (1) 10 5 tr and tf ms 20 s An internal 300-k pulldown retains shut-down mode when no external signal is applied to this pin. Specifications Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com 4.7.2 SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Clock Specifications 4.7.2.1 Slow Clock An external source must supply the slow clock and connect to the SLOW_CLK_IN pin. The source must be a digital signal in the range of 0 to 1.8 V. The accuracy of the slow clock frequency must be 32.768 kHz 250 ppm for Bluetooth use (as specified in the Bluetooth specification). The external slow clock must be stable within 64 slow-clock cycles (2 ms) following the release of nSHUTD. 4.7.2.2 Slow Clock Requirements Characteristics Condition Sym Min Input slow clock frequency Input slow clock accuracy (Initial + temp + aging) Unit Hz 250 ANT 50 tr and tf 15% Square wave, DC-coupled ppm 200 Frequency input duty cycle 50% ns 85% VIH 0.65 x VDD_IO VDD_IO V peak VIL 0 0.35 x VDD_IO V peak Input impedance 1 Input capacitance 4.7.3 Max Bluetooth Input transition time tr and tf (10% to 90%) Slow clock input voltage limits Typ 32768 M 5 pF Peripherals 4.7.3.1 UART Figure 4-2 shows the UART timing diagram. HCI_RTS t2 t1 HCI_RX t6 HCI_CTS t3 t4 HCI_TX Start bit Stop bit 10 bits td_uart_swrs064 Figure 4-2. UART Timing Specifications Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 11 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com Table 4-3 lists the UART timing characteristics. Table 4-3. UART Timing Characteristics Symbol Characteristics Condition Min Baud rate Typ 37.5 Max Unit 4000 kbps Baud rate accuracy per byte Receive and transmit -2.5 1.5 % Baud rate accuracy per bit Receive and transmit -12.5 12.5 % 1 byte t3 CTS low to TX_DATA on t4 CTS high to TX_DATA off t6 CTS-high pulse width t1 RTS low to RX_DATA on t2 RTS high to RX_DATA off 0 s 2 Hardware flow control 1 0 Interrupt set to 1/4 FIFO bit s 2 16 byte Figure 4-3 shows the UART data frame. tb TX D0 STR D1 Dn D2 PAR STP td_uart_swrs064 Figure 4-3. Data Frame Table 4-4 describes the symbols used in Figure 4-3. Table 4-4. Data Frame Key Symbol 4.7.3.2 Description STR Start bit D0...Dn Data bits (LSB first) PAR Parity bit (optional) STP Stop bit PCM Figure 4-4 shows the interface timing for the PCM. Tclk Tw Tw AUD_CLK tis tih AUD_IN / FSYNC_IN top AUD_OUT / FSYNC_OUT td_aud_swrs064 Figure 4-4. PCM Interface Timing Table 4-5 lists the associated PCM master parameters. 12 Specifications Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Table 4-5. PCM Master Symbol Parameter Tclk Cycle time Tw High or low pulse width Condition Min Max 244.14 (4.096 MHz) 15625 (64 kHz) Unit 50% of Tclk min tis AUD_IN setup time 25 tih AUD_IN hold time 0 top AUD_OUT propagation time 40-pF load 0 10 top FSYNC_OUT propagation time 40-pF load 0 10 Min Max ns Table 4-6 lists the associated PCM slave parameters. Table 4-6. PCM Slave Symbol Parameter Condition Tclk Cycle time Tw High or low pulse width Tis AUD_IN setup time 8 Tih AUD_IN hold time 0 8 tis AUD_FSYNC setup time tih AUD_FSYNC hold time top AUD_OUT propagation time 4.7.4 Unit 66.67 (15 MHz) 40% of Tclk ns 0 40-pF load 0 21 RF Performance 4.7.4.1 Bluetooth BR/EDR RF Performance All parameters in this section that are fast-clock dependent are verified using a 38.4-MHz XTAL and an RF load of 50 at the BT_RF port. 4.7.4.1.1 Bluetooth Receiver--In-Band Signals Characteristics Condition Operation frequency range Min Typ 2402 1 Input impedance 50 MHz -70 Pi/4-DQPSK, BER = 0.01% -92.5 -70 8DPSK, BER = 0.01% -85.5 -70 BER error floor at sensitivity + 10 dB, dirty TX off Pi/4-DQPSK 1E-7 1E-5 Maximum usable input power GFSK, BER = 0.1% -5 Pi/4-DQPSK, BER = 0.1% -10 8DPSK, BER = 0.1% -10 (1) 8DPSK Unit MHz -93 Intermodulation characteristics GFSK, BER = 0.1% Bluetooth Specification 2480 Channel spacing Sensitivity, dirty TX on (1) Max dBm 1E-5 Level of interferers (for n = 3, 4, and 5) -20 dBm -30 -39 dBm Sensitivity degradation up to 3 dB may occur for minimum and typical values where the Bluetooth frequency is a harmonic of the fast clock. Specifications Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 13 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com Characteristics Condition C/I performance (2) Min GFSK, co-channel EDR, co-channel Image = -1 MHz EDR, adjacent 1 MHz, (image) 8 11 13 8DPSK 16.5 21 -10 0 Pi/4-DQPSK -10 0 8DPSK -5 5 -38 -30 Pi/4-DQPSK -38 -30 8DPSK -38 -25 GFSK, adjacent -2 MHz EDR, adjacent -2 MHz -28 -20 Pi/4-DQPSK -28 -20 8DPSK -22 -13 -45 -40 Pi/4-DQPSK -45 -40 8DPSK -44 -33 GFSK, adjacent |3| MHz EDR, adjacent |3| MHz RF return loss RX mode LO leakage Bluetooth Specification 9.5 GFSK, adjacent +2 MHz EDR, adjacent, +2 MHz Max Pi/4-DQPSK GFSK, adjacent 1 MHz (2) Typ Frf = (received RF - 0.6 MHz) Unit dB -10 dB -63 dBm Numbers show ratio of desired signal to interfering signal. Smaller numbers indicate better C/I performance. 4.7.4.1.2 Bluetooth Transmitter--GFSK Characteristics Min Typ Maximum RF output power (1) 10 Gain control range 30 Power control step Max Bluetooth Specification dBm 2 8 dB 2 to 8 Adjacent channel power |M-N| = 2 -45 -20 Adjacent channel power |M-N| > 2 -50 -40 (1) Unit dBm To modify maximum output power, use an HCI VS command. 4.7.4.1.3 Bluetooth Transmitter--EDR Characteristics EDR output power Min Typ Pi/4-DQPSK VDD_IN = VBAT 8 8DPSK VDD_IN = VBAT 8 EDR relative power -2 Gain control range Max Bluetooth Specification dBm 1 -4 to +1 8 2 to 8 30 Power control step 2 Unit dB Adjacent channel power |M-N| = 1 -30 -26 dBc Adjacent channel power |M-N| = 2 -27 -20 dBm -42 -40 dBm Adjacent channel power |M-N| > 2 (1) 14 (1) Adjacent channel power measurements take into account specification exception of three bands, as defined by the Test Suite Structure (TSS) and Test Purposes (TP) Bluetooth Documentation Specification. Specifications Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 4.7.4.1.4 Bluetooth Modulation--GFSK Characteristics Condition -20 dB bandwidth GFSK Modulation characteristics f1avg f2max limit for at least 99.9% of all f2max Sym Mod data = 4 1 s, 4 0 s: 111100001111... F1 avg Mod data = 1010101... F2 max Min Max Bluetooth Specification Unit 925 1000 kHz 165 140 to 175 kHz 130 88 > 80 % kHz DH1 -25 25 < 25 DH3 and DH5 -35 35 < 40 20 < 20 kHz/ 50 s +75 < 75 kHz Drift rate Initial carrier frequency tolerance > 115 kHz f2avg, f1avg Absolute carrier frequency drift Typ f0 - fTX -75 4.7.4.1.5 Bluetooth Modulation--EDR Characteristics Condition Min Typ Max Bluetooth Specification Unit Carrier frequency stability -10 10 10 kHz Initial carrier frequency tolerance -75 75 75 kHz Rms DEVM (1) 99% DEVM (1) Peak DEVM (1) (1) Pi/4-DQPSK 6 8DPSK 6 20 13 Pi/4-DQPSK 30 30 8DPSK 20 20 Pi/4-DQPSK 14 35 8DPSK 16 25 % Max performance refers to maximum TX power. 4.7.4.2 Bluetooth LE RF Performance All parameters in this section that are fast-clock dependent are verified using a 38.4-MHz XTAL and an RF load of 50 at the BT_RF port. 4.7.4.2.1 BLE Receiver--In-Band Signals Characteristic Condition Operation frequency range Min Typ 2402 2 Input impedance 50 PER = 30.8%; dirty TX on Maximum usable input power GMSK, PER = 30.8% Intermodulation characteristics Level of interferers (for n = 3, 4, 5) (1) BLE Specification 2480 Channel spacing Sensitivity, dirty TX on (1) Max -93 -10 -30 Unit MHz MHz -70 dBm -10 dBm -50 dBm Sensitivity degradation up to 3 dB may occur where the BLE frequency is a harmonic of the fast clock. Specifications Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 15 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Characteristic Condition C/I performance (2) Image = -1 MHz Min Typ GMSK, co-channel RX mode LO leakage (2) www.ti.com Max BLE Specification Unit 21 8 GMSK, adjacent 1 MHz -5 15 GMSK, adjacent +2 MHz -45 -17 GMSK, adjacent -2 MHz -22 -15 GMSK, adjacent |3| MHz -47 -27 Frf = (received RF - 0.6 MHz) -63 dB dBm Numbers show wanted signal-to-interfering signal ratio. Smaller numbers indicate better C/I performance. 4.7.4.2.2 BLE Transmitter Characteristics Min Typ Max BLE Specification Unit dBm RF output power (VDD_IN = VBAT) (1) 10 (2) 10 Adjacent channel power |M-N| = 2 -45 -20 Adjacent channel power |M-N| > 2 -50 -30 (1) (2) dBm To modify maximum output power, use an HCI VS command. To achieve the BLE specification of 10-dBm maximum, an insertion loss of > 2 dB is assumed between the RF ball and the antenna. Otherwise, use an HCI VS command to modify the output power. 4.7.4.2.3 BLE Modulation Characteristics Modulation characteristics Condition f1avg f2max limit for at least 99.9% of all f2max Sym Min Mod data = 4 1s, 4 0 s: 1111000011110000. .. f1 avg 250 Mod data = 1010101... f2 max 210 16 BLE Specification Unit 225 to 275 185 kHz 0.8 0.9 -25 Drift rate Initial carrier frequency tolerance Max kHz f2avg, f1avg Absolute carrier frequency drift Typ -25 Specifications 25 50 kHz 15 20 kHz/50 ms 25 100 kHz Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 5 Detailed Description 5.1 Overview Table 5-1. Technology and Assisted Modes Supported Module CC2564MODN 5.2 Description Technology Supported BR/EDR LE Bluetooth 4.1 + BLE Bluetooth 4.1 + ANT Assisted Modes Supported ANT HFP 1.6 (WBS) A2DP Bluetooth BR/EDR Description The TI Bluetooth HCI module is Bluetooth 4.1 compliant up to the HCI level (for the technology supported, see Table 5-1): * Up to seven active devices * Scatternet: Up to 3 piconets simultaneously, 1 as master and 2 as slaves * Up to two synchronous connection oriented (SCO) links on the same piconet * Very fast AFH algorithm for asynchronous connection-oriented link (ACL) and extended SCO (eSCO) link * Supports typically 10-dBm TX power without an external power amplifier (PA), thus improving Bluetooth link robustness * Digital radio processor (DRPTM) single-ended 50- I/O for easy RF interfacing * Internal temperature detection and compensation to ensure minimal variation in RF performance over temperature * Flexible pulse-code modulation (PCM) and inter-IC sound (I2S) digital codec interface: - Full flexibility of data format (linear, A-Law, -Law) - Data width - Data order - Sampling - Slot positioning - Master and slave modes - High clock rates up to 15 MHz for slave mode (or 4.096 MHz for master mode) * Support for all voice air-coding - CVSD - A-Law - -Law - Transparent (uncoded) 5.3 Bluetooth LE Description * * * * * * Bluetooth 4.1 compliant Solution optimized for proximity and sports use cases Supports up to 10 (CC2564 or CC2564B) simultaneous connections Multiple sniff instances that are tightly coupled to achieve minimum power consumption Independent buffering for LE, allowing large numbers of multiple connections without affecting BR/EDR performance. Includes built-in coexistence and prioritization handling for BR/EDR and LE Detailed Description Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 17 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com NOTE ANT and the assisted modes (HFP 1.6 and A2DP) are not available when BLE is enabled. 5.4 Bluetooth Transport Layers Figure 5-1 shows the Bluetooth transport layers. UART transport layer Host controller interface Data Control HCI data handler General modules: Event HCI vendorspecific HCI command handler Data Trace Link manager Timers Data Sleep Link controller RF SWRS121-016 Figure 5-1. Bluetooth Transport Layers 5.5 Host Controller Interface The TI Bluetooth HCI module incorporates one UART module dedicated to the HCI transport layer. The HCI interface transports commands, events, and ACL between the device and the host using HCI data packets. The maximum baud rate of the UART module is 4 Mbps; however, the default baud rate after power up is set to 115.2 kbps. The baud rate can thereafter be changed with a VS command. The device responds with a command complete event (still at 115.2 kbps), after which the baud rate change occurs. The UART module includes the following features: * Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions * Transmitter underflow detection * CTS and RTS hardware flow control (UART transport layer) * XON and XOFF software flow control (Three-wire UART transport layer) Table 5-2 lists the UART module default settings. Table 5-2. UART Module Default Settings Parameter 18 Value Bit rate 115.2 kbps Data length 8 bits Stop bit 1 Parity None Detailed Description Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com 5.5.1 SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 UART Transport Layer The UART Transport Layer includes four signals: * TX * RX * CTS * RTS Flow control between the host and the TI Bluetooth HCI module is byte-wise by hardware. Figure 5-2 shows the H4 UART interface. Host_RX HCI_RX Host_TX HCI_TX Host CC2564MODN Host_CTS HCI_CTS Host_RTS HCI_RTS SWRS160-003 Figure 5-2. UART Transport Layer When the UART RX buffer of the TI Bluetooth HCI module passes the flow control threshold, it sets the HCI_RTS signal high to stop transmission from the host. When the HCI_CTS signal is set high, the module stops transmission on the interface. If HCI_CTS is set high while transmitting a byte, the module finishes transmitting the byte and stops the transmission. The UART Transport Layer includes a mechanism that handles the transition between active mode and sleep mode. The protocol occurs through the CTS and RTS UART lines and is known as the enhanced HCI low level (eHCILL) power-management protocol. For more information on the UART Transport Layer, see Part A, UART Transport Layer, found in Volume 4: HCI Transports of the Adopted Bluetooth Core Specifications. 5.5.2 Three-Wire UART Transport Layer The Three-Wire UART Transport Layer consists of three signals (see Figure 5-3. * TX * RX * GND Host_RX HCI_RX Host_TX HCI_TX Host CC2564MODN GND GND SWRS160-009 Figure 5-3. Three-Wire UART Transport Layer The Three-Wire UART Transport Layer supports the following features: * Software flow control (XON/XOFF) * Power management using the software messages: - WAKEUP - WOKEN - SLEEP * CRC data integrity check Detailed Description Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 19 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com For more information on the Three-Wire UART Transport Layer, see Part D: Three-Wire UART Transport Layer , found in Volume 4: HCI Transports of the Adopted Bluetooth Core Specifications. 5.6 Digital Codec Interface The codec interface is a fully programmable port to support seamless interfacing with different PCM and I2S codec devices. The interface includes the following features: * Two voice channels * Master and slave modes * All voice coding schemes defined by the Bluetooth specification: linear, A-Law, and -Law * Long and short frames * Different data sizes, order, and positions * High flexibility to support a variety of codecs * Bus sharing: Data_Out is in Hi-Z state when the interface is not transmitting voice data. 5.6.1 Hardware Interface The interface includes four signals: * Clock: configurable direction (input or output) * Frame_Sync and Word_Sync: configurable direction (input or output) * Data_In: input * Data_Out: output or 3-state The module can be the master of the interface when generating the Clock and Frame_Sync signals or the slave when receiving these two signals. For slave mode, clock input frequencies of up to 15 MHz are supported. At clock rates above 12 MHz, the maximum data burst size is 32 bits. For master mode, the module can generate any clock frequency between 64 kHz and 4.096 MHz. 5.6.2 I2S When the codec interface is configured to support the I2S protocol, these settings are recommended: * Bidirectional, full-duplex interface * Two time slots per frame: time slot-0 for the left channel audio data; and time slot-1 for the right channel audio data * Each time slot is configurable up to 40 serial clock cycles long, and the frame is configurable up to 80 serial clock cycles long. 5.6.3 Data Format The data format is fully configurable: * The data length can be from 8 to 320 bits in 1-bit increments when working with 2 channels, or up to 640 bits when working with 1 channel. The data length can be set independently for each channel. * The data position within a frame is also configurable within 1 clock (bit) resolution and can be set independently (relative to the edge of the Frame_Sync signal) for each channel. * The Data_In and Data_Out bit order can be configured independently. For example, Data_In can start with the most significant bit (MSB); Data_Out can start with the least significant bit (LSB). Each channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for sample sizes up to 24 bits. * Data_In and Data_Out are not required to be the same length. * The Data_Out line is configured to Hi-Z output between data words. Data_Out can also be set for permanent Hi-Z, regardless of the data output. This configuration allows the module to be a bus slave in a multislave PCM environment. At power up, Data_Out is configured as Hi-Z. 20 Detailed Description Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com 5.6.4 SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Frame Idle Period The codec interface handles frame idle periods, in which the clock pauses and becomes 0 at the end of the frame, after all data are transferred. The module supports frame idle periods both as master and slave of the codec bus. When the module is the master of the interface, the frame idle period is configurable. There are two configurable parameters: * Clk_Idle_Start: indicates the number of clock cycles from the beginning of the frame to the beginning of the idle period. After Clk_Idle_Start clock cycles, the clock becomes 0. * Clk_Idle_End: indicates the time from the beginning of the frame to the end of the idle period. The time is given in multiples of clock periods. The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period. For example, for clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90. Between both Frame_Sync signals there are 70 clock cycles (instead of 100). The clock idle period starts 60 clock cycles after the beginning of the frame and lasts 90 - 60 = 30 clock cycles. Thus, the idle period ends 100 - 90 = 10 clock cycles before the end of the frame. The data transmission must end before the beginning of the idle period. Figure 5-4 shows the frame idle timing. Frame period Frame_Sync Data_In Data_Out Frame idle Clock Clk_Idle_Start Clk_Idle_End frmidle_swrs064 Figure 5-4. Frame Idle Period 5.6.5 Clock-Edge Operation The codec interface of the module can work on the rising or the falling edge of the clock and can sample the Frame_Sync signal and the data at inversed polarity. Figure 5-5 shows the operation of a falling-edge-clock type of codec. The codec is the master of the bus. The Frame_Sync signal is updated (by the codec) on the falling edge of the clock and is therefore sampled (by the module) on the next rising clock. The data from the codec is sampled (by the module) on the falling edge of the clock Detailed Description Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 21 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com PCM FSYNC PCM CLK D7 PCM DATA IN D6 D5 D4 D3 D2 D1 D0 CC256x SAMPLE TIME SWRS121-004 Figure 5-5. Negative Clock Edge Operation 5.6.6 Two-Channel Bus Example Figure 5-6 shows a 2-channel bus in which the two channels have different word sizes and arbitrary positions in the bus frame. (FT stands for frame timer.) ... Clock FT 127 0 1 2 3 4 5 6 7 ... 42 43 44 8 9 127 0 Fsync MSB LSB MSB LSB Data_Out bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 ... Data_In bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 ... PCM_data_window CH1 data start FT = 0 CH1 data length = 11 CH2 data start FT = 43 CH2 data length = 8 Fsync period = 128 Fsync length = 1 twochpcm_swrs064 Figure 5-6. 2-Channel Bus Timing 5.7 Assisted Modes The TI Bluetooth HCI module contains an embedded coprocessor that can be used for multiple purposes. The module uses the coprocessor to perform the LE or ANT functionality. The module also uses the coprocessor to execute the assisted HFP 1.6 (WBS) or assisted A2DP functions. Only one of these functions can be executed at a time because they all use the same resources (that is, the coprocessor; see Table 5-1 for the modes of operation supported by the module). This section describes the assisted HFP 1.6 (WBS) and assisted A2DP modes of operation in the module. These modes of operation minimize host processing and power by taking advantage of the device coprocessor to perform the voice and audio SBC processing required in HFP 1.6 (WBS) and A2DP profiles. This section also compares the architecture of the assisted modes with the common implementation of the HFP 1.6 and A2DP profiles. The assisted HFP 1.6 (WBS) and assisted A2DP modes of operation comply fully with the HFP 1.6 and A2DP Bluetooth specifications. For more information on these profiles, see the corresponding Bluetooth profile specification in Adopted Bluetooth Core Specifications. 22 Detailed Description Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com 5.7.1 SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Assisted HFP 1.6 (WBS) The HFP 1.6 Profile Specification adds the requirement for WBS support. The WBS feature allows twice the voice quality versus legacy voice coding schemes at the same air bandwidth (64 kbps). This feature is achieved using a voice sampling rate of 16 kHz, a modified subband coding (mSBC) scheme, and a packet loss concealment (PLC) algorithm. The mSBC scheme is a modified version of the mandatory audio coding scheme used in the A2DP profile with the parameters listed in Table 5-3. Table 5-3. mSBC Parameters Parameter Value Channel mode Mono Sampling rate 16 kHz Allocation method Loudness Subbands 8 Block length 15 Bitpool 26 The assisted HFP 1.6 mode of operation implements this WBS feature on the embedded coprocessor. That is, the mSBC voice coding scheme and the PLC algorithm are executed in the coprocessor rather than in the host, thus minimizing host processing and power. One WBS connection at a time is supported and WBS and NBS connections cannot be used simultaneously in this mode of operation. Figure 5-7 shows the architecture comparison between the common implementation of the HFP 1.6 profile and the assisted HFP 1.6 solution. Bluetooth Stack Bluetooth Stack CC2564MODN Bluetooth Controller CC256x CC2564MODN Bluetooth Controller Figure 5-7. HFP 1.6 Architecture Versus Assisted HFP 1.6 Architecture Detailed Description Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 23 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 5.7.2 www.ti.com Assisted A2DP The A2DP enables wireless transmission of high-quality mono or stereo audio between two devices. A2DP defines two roles: * A2DP source is the transmitter of the audio stream. * A2DP sink is the receiver of the audio stream. A typical use case streams music from a tablet, phone, or PC (the A2DP source) to headphones or speakers (the A2DP sink). This section describes the architecture of these roles and compares them with the corresponding assisted-A2DP architecture. To use the air bandwidth efficiently, the audio data must be compressed in a proper format. The A2DP mandates support of the SBC scheme. Other audio coding algorithms can be used; however, both Bluetooth devices must support the same coding scheme. SBC is the only coding scheme spread out in all A2DP Bluetooth devices, and thus the only coding scheme supported in the assisted A2DP modes. Table 5-4 lists the recommended parameters for the SBC scheme in the assisted A2DP modes. Table 5-4. Recommended Parameters for the SBC Scheme in Assisted A2DP Modes SBC Encoder Settings (1) Sampling frequency (kHz) Mid Quality High Quality Mono Joint Stereo Mono Joint Stereo 44.1 48 44.1 48 44.1 48 44.1 48 Bitpool value 19 18 35 33 31 29 53 51 Resulting frame length (bytes) 46 44 83 79 70 66 119 115 Resulting bit rate (Kbps) 127 132 229 237 193 198 328 345 (1) Other settings: Block length = 16; allocation method = loudness; subbands = 8. The SBC scheme supports a wide variety of configurations to adjust the audio quality. Table 5-5 through Table 5-12 list the supported SBC capabilities in the assisted A2DP modes. Table 5-5. Channel Modes Channel Mode Status Mono Supported Stereo Supported Joint stereo Supported Table 5-6. Sampling Frequency Sampling Frequency (kHz) Status 16 Supported 44.1 Supported 48 Supported Table 5-7. Block Length Block Length Status 16 Supported Table 5-8. Subbands 24 Subbands Status 8 Supported Detailed Description Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Table 5-9. Allocation Method Allocation Method Status Loudness Supported Table 5-10. Bitpool Values Bitpool Range Status Assisted A2DP sink: 2-54 Supported Assisted A2DP source: 2-54 Supported Table 5-11. L2CAP MTU Size L2CAP MTU Size (Bytes) Status Assisted A2DP sink: 260-800 Supported Assisted A2DP source: 260-1021 Supported Table 5-12. Miscellaneous Parameters Item Value Status A2DP content protection Protected Not supported AVDTP service Basic type Supported L2CAP mode Basic mode Supported L2CAP flush Nonflushable Supported For detailed information on the A2DP profile, see the A2DP Profile Specification at Adopted Bluetooth Core Specifications. 5.7.2.1 Assisted A2DP Sink The A2DP sink role is the receiver of the audio stream in an A2DP Bluetooth connection. In this role, the A2DP layer and its underlying layers are responsible for link management and data decoding. To handle these tasks, two logic transports are defined: * Control and signaling logic transport * Data packet logic transport The assisted A2DP takes advantage of this modularity to handle the data packet logic transport in the module by implementing a light L2CAP layer (L-L2CAP) and light AVDTP layer (L-AVDTP) to defragment the packets. Then the assisted A2DP performs the SBC decoding on-chip to deliver raw audio data through the module PCM-I2S interface. Figure 5-8 shows the comparison between a common A2DP sink architecture and the assisted A2DP sink architecture. Detailed Description Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 25 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com A2DP Sink Architecture Assisted A2DP Sink Architecture Host Processor Host Processor Bluetooth Stack PCM / I2S A2DP Profile Bluetooth Stack 44.1 KHz 48 KHz Audio CODEC 16 bits A2DP Profile SBC AVDTP AVDTP Data Control Control L2CAP L2CAP HCI HCI Control Data Control HCI Data HCI CC2564MODN Bluetooth Controller CC2564MODN Bluetooth Controller PCM / I2S 44.1 KHz 48 KHz 16 bits Audio CODEC SBC L-AVDTP L-L2CAP Figure 5-8. A2DP Sink Architecture Versus Assisted A2DP Sink Architecture For more information on the A2DP sink role, see the A2DP Profile Specification at Adopted Bluetooth Core Specifications. 5.7.2.2 Assisted A2DP Source The role of the A2DP source is to transmit the audio stream in an A2DP Bluetooth connection. In this role, the A2DP layer and its underlying layers are responsible for link management and data encoding. To handle these tasks, two logic transports are defined: * Control and signaling logic transport * Data packet logic transport The assisted A2DP takes advantage of this modularity to handle the data packet logic transport in the module. First, the assisted A2DP encodes the raw data from the module PCM-I2S interface using an onchip SBC encoder. The assisted A2DP then implements an L-L2CAP layer and an L-AVDTP layer to fragment and packetize the encoded audio data. Figure 5-9 shows the comparison between a common A2DP source architecture and the assisted A2DP source architecture. 26 Detailed Description Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 A2DP Source Architecture Assisted A2DP Source Architecture Host Processor Host Processor Bluetooth Stack PCM / I2S A2DP Profile Bluetooth Stack 44.1 KHz 48 KHz Audio CODEC 16 bits A2DP Profile SBC AVDTP AVDTP Data Control Control L2CAP L2CAP HCI HCI Control Data Control HCI Data HCI CC2564MODN Bluetooth Controller CC2564MODN Bluetooth Controller PCM / I2S 44.1 KHz 48 KHz 16 bits Audio CODEC SBC L-AVDTP L-L2CAP Figure 5-9. A2DP Source Architecture Versus Assisted A2DP Source Architecture For more information on the A2DP source role, see the A2DP Profile Specification at Adopted Bluetooth Core Specifications. Detailed Description Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 27 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com 6 Applications, Implementation, and Layout 6.1 Reference Design Schematics Figure 6-1 shows the reference schematics for the TI Bluetooth HCI module. Figure 6-1. Reference Schematics 6.2 Layout This section provides the printed circuit board (PCB) layout rules and considerations, including component placement and routing guidelines, when designing a board with the CC2564MODN module. The integrator of the CC2564MODN module must comply with the PCB layout recommendations described in the following subsections to preserve the FCC and Industry Canada (IC) modular radio certification. Moreover, TI recommends customers follow the guidelines described in this section to achieve similar performance to that obtained with the TI reference design. 6.2.1 Layout Guidelines 6.2.1.1 PCB Stack-Up The recommended PCB stack-up is a four-layer design based on a standard flame-retardant 4 (FR4) material (see Figure 6-2). Layer 1 (TOP - RF + Signal) Use layer 1 to place the module on and to route signal traces. In particular, the RF trace must be run on this layer. Layer 2 (L2 - Ground) Layer 2 must be a solid ground layer. 28 Applications, Implementation, and Layout Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Layer 3 (L3 - Power) Use layer 3 to route power traces or place power planes. Layer 4 (BOTTOM - Signal) Use layer 4 as a second routable layer to run signal traces (except RF signals). Figure 6-2. PCB Stack-Up TI recommends a board thickness of 62.4 mils and a substrate dielectric of 4.2. For details, see Table 6-1. NOTE These parameters are used for the 50- impedance matching of the RF trace. For more information, see Section 6.2.1.2, RF Interface Guidelines. Table 6-1. Recommended PCB Properties Item Value Solder mask 0.4 mil TOP copper + plating 1 oz/1.4 mil PP (substrate) 10 mil L2 copper + plating 1 oz/1.4 mil Core (substrate) 36 mil L3 copper + plating 1 oz/1.4 mil PP (substrate) 10 mil Bottom copper + plating 1 oz/1.4 mil Solder mask 0.4 mil Final thickness 62.4 mil = 1.585 mm Applications, Implementation, and Layout Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 29 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 6.2.1.2 www.ti.com RF Interface Guidelines 6.2.1.2.1 RF Trace Route the RF traces on layer 1 (top) and keep the routes as short as possible. These traces must be 50, controlled-impedance traces with reference to the solid ground in the layer 2-microstrip transmission line. The TI reference design uses an RF trace width equal to 17 mils, which conforms to a 50 -3% simulated result, based on the following PCB properties: (see Table 6-1 and Figure 6-3). * Substrate height: 10 mils * Substrate dielectric: 4.2 * Trace width: 17 mils * Trace thickness: 1.4 mils * Ground clearance: 20 mils TI * * * recommends the following guidelines for a good RF trace design: The RF traces must have via stitching on both ground planes around the RF trace (see Figure 6-3). Avoid placing clock signals close to the RF path. Place a u.FL connector (or similar) between the module and antenna if possible or during prototype phases (see Figure 6-3.) * The RF path should look like one single path along the RF traces and matching components. See Figure 6-4 for the good (OK) case versus the not good (NG) case. * The RF trace bends must be gradual with an approximate maximum bend of 45 degrees with trace mitered. RF traces must not have sharp corners. In addition: - Avoid case (1) in Figure 6-5. A right angle leads to scattering and makes matching weak. - Case (2) in Figure 6-5 is not recommended. Even if this bend had a good 50 , a careful simulation would be required. - Case (3) in Figure 6-5 is recommended. The half-arc angle reduces scattering caused by a right angle. Figure 6-3. Placing a u.FL Connector Between the Module and Antenna 30 Applications, Implementation, and Layout Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Figure 6-4. Good (OK) vs Not Good (NG) RF Path Figure 6-5. Not Recommended vs Recommended Trace Bends 6.2.1.3 Antenna The module must be used with the approved chip antenna (LTA-5320-2G4S3-A) and must comply with the following guidelines to preserve the modular radio certification (see Figure 6-6). * Antenna clearance area = 15 mm x 8 mm * Antenna solder termination to board edge length = 186 mils * Antenna feed point to right side ground length = 140 mils * Antenna feed point to last component trace = 244 mils * Antenna pads to inside ground length = 208 mils * An inductor L1 = 9.1 nH is required to properly match the chip antenna. In * * * addition, follow these general recommendations for a proper design with any antenna: Place the matching circuit as close as possible to the antenna feed point. Do not place traces or ground under the antenna section. Place the antenna, RF traces, and modules on the edge of the PCB product. In addition, consider the proximity of the antenna to the enclosure and consider the enclosure material. Applications, Implementation, and Layout Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 31 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com Figure 6-6. Antenna Guidelines 6.2.1.4 Power Supply and Ground Guidelines 6.2.1.4.1 Power Traces TI * * * * recommends the following guidelines for the power supply of the CC2564MODN module: Use a star pattern format to supply power to the different pads of the module. Keep the power traces (VBAT and VIO) more than 14 mils. Use short power supply traces. Place decoupling capacitors as close as possible to the module (see Figure 6-7). Figure 6-7. Placing Decoupling Capacitors as Close as Possible to the Module 32 Applications, Implementation, and Layout Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 6.2.1.4.2 Ground The common ground must be the solid ground plane in layer 2. TI recommends using a large ground pad under the module and placing enough ground vias beneath for a stable system and thermal dissipation (see Figure 6-8). Figure 6-8. Using a Large Ground Pad Under the Module 6.2.1.5 Clock Guidelines Remember that clock signal routing directly influences RF performance because of the signal trace susceptibility to noise. 6.2.1.5.1 Slow Clock TI recommends the following guidelines: * Keep the slow clock signal lines as short as possible and at least 4-mils wide. * Traces of slow clock signals must have a ground plane on each side of the signal trace to reduce undesired signal coupling. * To reduce the capacitive coupling of undesired signals into the clock line, do not route slow clock traces above or below other signals (especially digital signals). Figure 6-9 shows the slow clock trace in the TI reference design. Applications, Implementation, and Layout Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 33 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com Figure 6-9. Slow Clock Trace in TI Reference Design 6.2.1.6 Digital Interface Guidelines 6.2.1.6.1 UART The CC2564MODN UART default baud rate is 115.2 kbps but can run up to 4 Mbps. TI recommends separating these lines from the DC supply lines, RF lines, and sensitive clock lines and circuitry. To improve the return path and isolation, run the lines with ground on the adjacent layer when possible. 6.2.1.6.2 PCM The digital audio lines (pulse-code modulation [PCM]) are high-speed digital lines in which the four wires (AUD_CLK, AUD_FSYNC, AUD_IN, and AUD_OUT) must be roughly the same length. TI recommends running these lines as a bus interface (see Figure 6-10). These lines are high-speed digital and must be separated from DC supply lines, RF lines, and sensitive clock lines and circuitry. Run the lines with ground on the adjacent layer to improve the return path and isolation. Figure 6-10. Running the Digital Audio Lines 34 Applications, Implementation, and Layout Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com 6.2.2 SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Reference Design Drawings Figure 6-11 through Figure 6-16 shows the PCB layers and assembly drawings for the CC2564MODNEM reference design board. For more information (such as schematics, BOM, and design files), see TI's CC2564MODN Reference Design product page. Figure 6-11. Top Silkscreen Figure 6-12. Bottom Silkscreen Figure 6-13. Layer 1 Figure 6-14. Layer 2 Applications, Implementation, and Layout Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 35 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com Figure 6-15. Layer 3 6.3 Figure 6-16. Layer 4 Soldering Recommendations Figure 6-17 shows the recommended reflow profile. Figure 6-17. Reflow Profile 36 Applications, Implementation, and Layout Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 7 Device and Documentation Support 7.1 Device Certification and Qualification The TI CC2564MODN module is certified for the FCC, IC, and ETSI/CE. Moreover, the module is a Bluetooth Qualified Design by the Bluetooth Special Interest Group (Bluetooth SIG). TI Customers that build products based on the TI CC2564MODN module can save in testing cost and time per product family. For more information, see the CC256x Regulatory Compliance wiki and the CC256x Bluetooth SIG Qualification wiki. 7.1.1 FCC Certification The TI CC2564MODN module is certified for the FCC as a single-modular transmitter. The module is a FCC-certified radio module that carries a modular grant. The module complies with the intentional radiator portion (Part 15c) of the FCC certification: Part 15.247 transmitter tests. For more information, see CC2564MODN Modular Grant, FCC ID: Z64-2564N. 7.1.2 IC Certification The TI CC2564MODN module is certified for the IC as a single-modular transmitter. The TI CC2564MODN module meets IC modular approval and labeling requirements. The IC follows the same testing and rules as the FCC regarding certified modules in authorized equipment. For more information, see CC2564MODN Modular Grant, IC ID: 451I-2564N. 7.1.3 ETSI/CE Certification The TI CC2564MODN module is CE certified with certifications to the appropriate EU radio and EMC directives summarized in the Declaration of Conformity and evidenced by the CE mark. The module is tested against the ETSI EN300-328 v1.8.1 radio tests, which is accepted by a number of countries for radio compliance. For more information, see CC2564MODN DoC. 7.1.4 Bluetooth Special Interest Group Qualification The TI CC2564MODN module is Bluetooth qualified and carries a Bluetooth 4.1 Controller Subsystem Qualification Design ID (QDID), which covers the lower layers of a Bluetooth design up to the HCI layer. TI customers that build products based on the TI CC2564MODN module can reference this QDID in their Bluetooth product Listing. For more information, see CC2564MODN Controller Subsystem, QDID 55257. 7.2 7.2.1 Device Support Development Support For a complete listing of development-support tools, see the TI CC256x wiki. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 7.2.2 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent evolutionary stages of product development from engineering prototypes through fully qualified production devices. X null Experimental, preproduction, sample or prototype device. Device may not meet all product qualification conditions and may not fully comply with TI specifications. Experimental/Prototype devices are shipped against the following disclaimer: "This product is still in development and is intended for internal evaluation purposes." Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of fitness for a specific purpose, of this device. Device is qualified and released to production. TI's standard warranty applies to production devices. Device and Documentation Support Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN 37 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 7.2.3 www.ti.com Documentation Support In future revisions of this data sheet, this section will list supporting documents for the CC2564MODN device. 7.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 7.4 Trademarks MSP430, E2E are trademarks of Texas Instruments. Cortex is a registered trademark of ARM Limited. ARM is a registered trademark of ARM Physical IP, Inc. iPod is a registered trademark of Apple, Inc. Bluetooth is a registered trademark of Bluetooth SIG, Inc. 7.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 7.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 38 Device and Documentation Support Copyright (c) 2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODN www.ti.com SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 8 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 8.1 Module Outline Figure 8-1 shows the outline of the TI Bluetooth HCI module. Top View L a4 a5 Bottom View c1 c5 a3 c2 a2 a1 c4 W c3 b2 b1 b3 Side View T SWRS160-012 Figure 8-1. Outline of TI Bluetooth HCI Module Table 8-1 lists the dimensions of the TI Bluetooth HCI module outline. Table 8-1. Dimensions of TI Bluetooth HCI Module Mechanical Outline Marking Dimensions (mm) Marking Dimensions (mm) L (body size) 7.0 (0.1) b1 0.95 (0.1) W (body size) 7.0 (0.1) b2 1.35 (0.15) T (thickness) 1.4 (max) b3 1.35 (0.15) a1 1.1 (0.15) c1 0.4 (0.05) a2 1.1 (0.15) c2 0.4 (0.05) a3 0.6 (0.1) c3 0.5 (0.1) a4 0.6 (0.1) c4 0.5 (0.1) a5 0.5 (0.1) c5 0.35 (0.05) Copyright (c) 2014, Texas Instruments Incorporated Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: CC2564MODN 39 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 8.2 Mechanical Data 40 Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: CC2564MODN www.ti.com Copyright (c) 2014, Texas Instruments Incorporated CC2564MODN www.ti.com 8.3 8.3.1 SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Packaging and Ordering Package and Ordering Information Table 8-2. Package and Order Information (1) Minimum Orderable Quantity Part Number (1) Status Package Type CC2564MODNCMOET Active MOE 250 CC2564MODNCMOER Active MOE 2000 Part number marking key: * CC2564 - module variant * MODNC - module marking (commercial) * MOEx - module package designator (R: tape/reel; T: small reel) Figure 8-2 shows the markings for the TI Bluetooth HCI module. Figure 8-2. CC2564MODN Markings Table 8-3 describes the CC2564MODN markings. Table 8-3. CC2564MODN Markings Marking CC2564MODN Description Model number Z64 - 2564N FCC ID: single modular FCC grant ID 451I - 2564N IC: single modular IC grant ID AXXXXXX XXXX CE Lot order code (for example, A0A7123): * A = fixed * Second and third digits = year code by hex (for example, 0A = 2010) * Fourth digit = month code by hex (for example, 7 = July) * Fifth to seventh digit = serial number by hex (for example, 123) Production date code (for example, 1424): * XX = year (for example, 14 = 2014) * XX = week (for example, 24 = week 24) CE compliance mark Copyright (c) 2014, Texas Instruments Incorporated Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: CC2564MODN 41 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 8.3.2 www.ti.com Empty Tape Portion Figure 8-3 shows the empty portion of the carrier tape. Empty portion Empty portion Device on tape portion End Start 270-mm MIN User direction of feed The length is to extend so that no unit is visible on the outer layer of tape. swrs064-001 Figure 8-3. Carrier Tape and Pockets 8.3.3 Device Quantity and Direction When pulling out the tape, the A1 corner is on the left side (see Figure 8-4). A1 corner Carrier tape Sprocket hole Embossment Cover tape User direction of feed SWRS064-002 Figure 8-4. Direction of Device 8.3.4 Insertion of Device Figure 8-5 shows the insertion of the device. insert_swrs064 Figure 8-5. Insertion of Device 42 Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: CC2564MODN Copyright (c) 2014, Texas Instruments Incorporated CC2564MODN www.ti.com 8.3.5 SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Tape Specification Figure 8-6 shows the dimensions of the tape. * * * * * * * 8.3.6 Figure 8-6. Tape Dimensions (mm) Cumulative tolerance of the 10-sprocket hole pitch is 0.20. Carrier camber is within 1 mm in 250 mm. Material is black conductive polystyrene alloy. All dimensions meet EIA-481-D requirements. Thickness: 0.30 0.05 mm Packing length per 22-inch reel is 110.5 m (1:3). Component load per 13-inch reel is 2000 pieces. Reel Specification Figure 8-7 shows the reel specifications: * 330-mm reel, 12-mm width tape * Reel material: Polystyrene (static dissipative/antistatic) 330.0 RFF 100.0 RFF A Figure 8-7. Reel Dimensions (mm) Copyright (c) 2014, Texas Instruments Incorporated Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: CC2564MODN 43 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 8.3.7 www.ti.com Packing Method Figure 8-8 shows the reel packing method. B Humidity indicator A Desiccant C C D 360mm 285mm 375mm Figure 8-8. Reel Packing Method 8.3.8 Packing Specification 8.3.8.1 Reel Box Each moisture-barrier bag is packed into a reel box, as shown in Figure 8-9. rlbx_swrs064 Figure 8-9. Reel Box (Carton) 44 Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: CC2564MODN Copyright (c) 2014, Texas Instruments Incorporated CC2564MODN www.ti.com 8.3.8.2 SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 Reel Box Material The reel box is made from corrugated fiberboard. 8.3.8.3 Shipping Box If the shipping box has excess space, filler (such as cushion) is added. Figure 8-10 shows a typical shipping box. NOTE The size of the shipping box may vary depending on the number of reel boxes packed. box_swrs064 Figure 8-10. Shipping Box (Carton) 8.3.8.4 Shipping Box Material The shipping box is made from corrugated fiberboard. 8.3.8.5 Labels Figure 8-11 shows the antistatic and humidity notice. Figure 8-11. Antistatic and Humidity Notice Figure 8-12 shows the MSL caution and storage condition notice. Figure 8-12. MSL Caution and Storage Condition Notice Copyright (c) 2014, Texas Instruments Incorporated Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: CC2564MODN 45 CC2564MODN SWRS160B - FEBRUARY 2014 - REVISED JULY 2014 www.ti.com Figure 8-13 shows the label for the inner box. Figure 8-13. Inner Box Label Example 46 Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: CC2564MODN Copyright (c) 2014, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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