74VHC08MTCX_NL - FAIRCHILD SEMICONDUCTOR

October, 2017 − Rev. 11 1Publication Order Number:

MC74VHC08/D

MC74VHC08

Quad 2-Input AND Gate

The MC74VHC08 is an advanced high speed CMOS 2−input AND

gate fabricated with silicon gate CMOS technology. It achieves high

speed operation similar to equivalent Bipolar Schottky TTL while

maintaining CMOS low power dissipation.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V

systems to 3.0 V systems.

Features

•High Speed: tPD = 4.3 ns (Typ) at VCC = 5.0 V

•Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25°C

•High Noise Immunity: VNIH = VNIL = 28% VCC

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Designed for 2.0 V to 5.5 V Operating Range

•Low Noise: VOLP = 0.8 V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300 mA

•ESD Performance:

Human Body Model > 2000 V;

Machine Model > 200 V

•Chip Complexity: 24 FETs or 6 Equivalent Gates

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free and are RoHS Compliant

3Y1

Figure 1. Logic Diagram

6Y2

8Y3

11 Y4

Y = AB

Figure 2. Pinout: 14−Lead Packages

1314 12 11 10 9 8

21 34567

VCC B4 A4 Y4 B3 A3 Y3

A1 B1 Y1 A2 B2 Y2 GND

(Top View)

SOIC−14

D SUFFIX

CASE 751A

TSSOP

DT SUFFIX

CASE 948G

www.onsemi.com

(Note: Microdot may be in either location)

MARKING

DIAGRAMS

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

FUNCTION TABLE

Inputs Output

VHC

ALYW 



A = Assembly Location

WL, L = Wafer Lot

Y = Year

WW, W = Work Week

G or  = Pb−Free Package

VHC08G

AWLYWW

MC74VHC08

www.onsemi.com

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎ

–0.5 to +7.0

ÎÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎÎÎ

–0.5 to +7.0

ÎÎÎ

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage

ÎÎÎÎÎ

–0.5 to VCC +0.5

ÎÎÎ

ÎÎÎÎ

IIK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Diode Current

ÎÎÎÎÎ

−20

ÎÎÎ

ÎÎÎÎ

IOK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Diode Current

ÎÎÎÎÎ

±20

ÎÎÎ

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±50

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, SOIC Package†

TSSOP Package†

ÎÎÎÎÎ

500

450

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

–65 to +150

ÎÎÎ

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of

these limits are exceeded, device functionality should not be assumed, damage may occur and

reliability may be affected.

†Derating − SOIC Package: – 7 mW/°C from 65° to 125°C

TSSOP Package: − 6.1 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Min

ÎÎÎÎÎ

Max

ÎÎÎÎ

Unit

ÎÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎ

2.0

ÎÎÎÎÎ

5.5

ÎÎÎÎ

ÎÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎÎÎ

5.5

ÎÎÎÎ

ÎÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage

ÎÎÎÎÎ

VCC

ÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature

ÎÎÎÎÎ

−55

ÎÎÎÎÎ

+125

ÎÎÎÎ

°C

ÎÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 3.3 V ±0.3 V

VCC = 5.0 V ±0.5 V

ÎÎÎÎÎ

100

ÎÎÎÎ

ns/V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS

ÎÎÎÎ

Symbo

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎÎ

TA = −55°C to 125°C

ÎÎÎ

Unit

ÎÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎÎÎ

Max

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎ

Minimum High−Level

Input Voltage

ÎÎÎÎÎÎ

ÎÎÎÎ

2.0

3.0 to 5.5

ÎÎÎÎ

1.50

VCC x 0.7

ÎÎÎ

ÎÎÎÎ

1.50

VCC x 0.7

ÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎ

Maximum Low−Level

Input Voltage

ÎÎÎÎÎÎ

ÎÎÎÎ

2.0

3.0 to 5.5

ÎÎÎÎ

ÎÎÎ

0.50

VCC x 0.3

ÎÎÎÎ

ÎÎÎÎÎ

0.50

VCC x 0.3

ÎÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎ

Minimum High−Level

Output Voltage

ÎÎÎÎÎÎ

Vin = VIH or VIL

IOH = −50 mA

ÎÎÎÎ

2.0

3.0

4.5

ÎÎÎÎ

1.9

2.9

4.4

ÎÎÎ

2.0

3.0

4.5

ÎÎÎ

ÎÎÎÎ

1.9

2.9

4.4

ÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎ

Vin = VIH or VIL

IOH = −4.0 mA

IOH = −8.0 mA

ÎÎÎÎ

3.0

4.5

ÎÎÎÎ

2.58

3.94

ÎÎÎ

ÎÎÎÎ

2.48

3.80

ÎÎÎÎÎ

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎ

Maximum Low−Level

Output Voltage

ÎÎÎÎÎÎ

Vin = VIH or VIL

IOL = 50 mA

ÎÎÎÎ

2.0

3.0

4.5

ÎÎÎÎ

ÎÎÎ

0.0

ÎÎÎ

0.1

ÎÎÎÎ

ÎÎÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎÎÎ

Vin = VIH or VIL

IOL = 4.0 mA

IOL = 8.0 mA

ÎÎÎÎ

3.0

4.5

ÎÎÎÎ

ÎÎÎ

0.36

ÎÎÎÎ

ÎÎÎÎÎ

0.44

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎ

Maximum Input

Leakage Current

ÎÎÎÎÎÎ

Vin = 5.5 V or GND

ÎÎÎÎ

0 to 5.5

ÎÎÎÎ

ÎÎÎ

±0.1

ÎÎÎÎ

ÎÎÎÎÎ

±1.0

ÎÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎ

Maximum Quiescent

Supply Current

ÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

5.5

ÎÎÎÎ

ÎÎÎ

2.0

ÎÎÎÎ

ÎÎÎÎÎ

20.0

ÎÎÎ

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74VHC08

www.onsemi.com

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)

ÎÎÎÎ

Symbo

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎÎ

TA = −55°C to 125°C

ÎÎÎ

Unit

ÎÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎÎÎ

Max

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎ

Maximum Propagation

Delay,

A or B to Y

ÎÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3 V CL = 15 pF

CL = 50 pF

ÎÎÎÎ

ÎÎÎ

6.2

8.7

ÎÎÎ

8.8

12.3

ÎÎÎÎ

1.0

ÎÎÎÎÎ

10.5

14.0

ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 V CL = 15 pF

CL = 50 pF

ÎÎÎÎ

ÎÎÎ

4.3

5.8

ÎÎÎ

5.9

7.9

ÎÎÎÎ

1.0

ÎÎÎÎÎ

7.0

9.0

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎ

Maximum Input

Capacitance

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎ

CPD Power Dissipation Capacitance (Note 1)

Typical @ 25°C, VCC = 5.0 V

1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC/4 (per gate). CPD is used to determine the

no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)

Symbo

Characteristic

TA = 25°C

Unit

Typ Max

VOLP Quiet Output Maximum Dynamic VOL 0.3 0.8 V

VOLV Quiet Output Minimum Dynamic VOL −0.3 −0.8 V

VIHD Minimum High Level Dynamic Input Voltage 3.5 V

VILD Maximum Low Level Dynamic Input Voltage 1.5 V

Figure 3. Switching Waveforms

A or B

50% VCC

tPLH tPHL

GND

VCC

50%

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 4. Test Circuit

Figure 5. Input Equivalent Circuit

INPUT

ORDERING INFORMATION

Device Package Shipping†

MC74VHC08DR2G SOIC−14

(Pb−Free) 2500 Units / Tape & Reel

MC74VHC08DTR2G TSSOP−14

(Pb−Free) 2500 Units / Tape & Reel

NLV74VHC08DTRG*

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable

MC74VHC08

www.onsemi.com

PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE L

6.50

14X

0.58

14X

1.18

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.

14 8

0.25 B M

X 45

SEATING

PLANE



0.25 B S

13X

DET AIL A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

D8.55 8.75 0.337 0.344

E3.80 4.00 0.150 0.157

A1.35 1.75 0.054 0.068

b0.35 0.49 0.014 0.019

L0.40 1.25 0.016 0.049

e1.27 BSC 0.050 BSC

A3 0.19 0.25 0.008 0.010

A1 0.10 0.25 0.004 0.010

M0 7 0 7

H5.80 6.20 0.228 0.244

h0.25 0.50 0.010 0.019

 

0.10

MC74VHC08

www.onsemi.com

PACKAGE DIMENSIONS

TSSOP−14 WB

CASE 948G

ISSUE C

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.



U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

ÉÉÉ

DETAIL E

−W−

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

−V−

14X REFK

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

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MC74VHC08/D

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