PRODUCT THCT2000M, THCT2000E PREVIEW DIRECTION DISCRIMINATORS D2889, NOVEMBER 1985 @ inputs are TTL- and CMOS-Voltage THCT2000M . . . JD PACKAGE Compatible THCT2000E . . . JD OR N PACKAGE @ Interfaces Mechanical Devices to Data Bus @ Identifies and Measures Forward or Backward Rotation or Direction Measures Pulse Duration and Frequency Cascadable 16-Bit Up/Down Counter 8-Bit Parallel 3-State Bus with Each Output Capable of Driving up to 15 LSTTL Loads @ Dependable Texas Instruments Quality and Reliability description The THCT2000 direction discriminator can determine the direction and displacement of a mechanical device based on input signals from two transducers in quadrature. !t can also measure a pulse duration using a known clock rate, or a frequency over a known time interval. It includes a 16-bit counter, which can be used separately. Several of these devices may be TH! cascaded to provide accuracy greater than p2ns 25 16-bits. p3iis zt The device may be used in many diverse GND J? 23 applications, and is specifically designed for use b4 8 22[] in many types of microprocessor-based systems. DS Hs aif] Some of the possibilities include motor controls, D6 [J10 20] robotics, tracker balls {mice}, lathe or tooting D7 Uti 9f] machines, automobiles, and conveyer belts or other transport mechanisms. The THCT2000M is characterized for operation over the full military temperature range of 65C to 125C. The THCT2000E is characterized for operation from ~40C to 85C. (TOP VIEW cO[}i3 16] READY GND (14 18{]) RUIV/RLO CT2000M .. . FK PACKAGE THCT2Q00E . . . FN PACKAGE (TOP VIEW) eo - Of/0(H OY _ 6 Bl2I8 Sista 432 1 28 2726 12 13 14 15 16 17 18 BIBZR6ss5 alo z|zJjoss ole \< lez kee NO LS! Devices PRODUCT PREVIEW documents contain information . on products in the formative or design phase of A development. Characteristic fata fad other TEXAS specifications are design goals. Texes Instruments reserves the right to c aye or discontinue these INSTRUMENTS products without notice. POST OFFICE BOX 225012 DALLAS, TEXAS 75265 Copyright 1985, Texas Instruments Incorporated 2-593 THCT2000M, THCT2000E DIRECTION DISCRIMINATORS logic symbolt qs hy S9IDIAD DIRECTION DISCRIMINATOR & _ THCT2000 a (27) mh up maxcTP=_"2) co oy (26)_ Nh. pown MINCT bh 12) 55 201 3) al A | DIRECTION 0 8) ng p20 |p| signats 1 Bo, (5) 9) 2 D2 me (18) MODE 3 16) p3 m1 REGISTER a7 SELECT 4 {8) 54 m2 (9) 5 10) DS crx 22) crock 6 ny ps reser 124) ml reset 7 ON 57 ae 115) (16) RLi/ALO 4<JREGISTER LOAD READY P\ READY uspmse 22 | _sp/MS6 BYTE SELECT cs 4) cup setect ro 2) reap we 28) WRITE ENABLE t This symbol is in accordance with ANSI/IEEE Std 91-1984. functional block diagram Mo M1 M2 BI Cl MEASUREMENT LOGIC 16-BIT COUNTER CLOCK 8 16-BIT R 16-TO-8 MUX BUFFER a m w mi 4 CONTROL LOGIC lg aa LSB/MSB RUV/RLO 07-06 2-594 we TEXAS INSTRUMENTS POST OFFICE BOX 225012 @ DALLAS, TEXAS 75265 THCT2000M, THCT2000E DIRECTION DISCRIMINATORS PIN DESCRIPTION NAME NUMBER A,B 20, 21 Signat measurement inputs. BI 26 Cascade input for counting down. In mode 0, BI is used as the clock input for counting down. Triggering occurs on the high-to-low transition. BO 12 Counter output underflow signal. Active (low) for a duration equal to the low level of the input clock. Gi 27 Cascade input for counting up. In mode O, Gi is used as the clock input for counting up. Triggering occurs on the high-to-low transition. CLK 22 Clock input. Used for internal synchronization and control timing. co 13 Counter output overflow signal. Active (low) for a duration equal to the tow level of the input clock. cs 4 Chip select input. This active-low input is used to enable read and write functions. For additional! details, see read and write timing diagrams. 00-D7 3, 4, 5, 6, Counter load inputs/register output data lines. 8, 9, 10, 11 GNG 7,14 Pins 7 and 14 are both internally connected to the ground rail of the integrated circuit but both should be connected to the system ground far proper operation. LSB/M5B 23 Byte select input. During read operations, a high level selects the least significant byte, while alow level selects the most significant byte. For write operations, this input directs the data on the bus into the least significant or mest significant byte position of the counter. See write timing diagrams Yi for additional details. MO, M1, M2 19,18, 17 Mode select inputs. : RD 2 Read input. When active (low) in conjunction with CS low, the data stored in the output register will 8 be present on the data bus as selected by the LSB/MSB input. See read timing diagrams for additional Oo details. S READY 16 Ready output. When active (low), this output indicates to the processor that it may complete the read O or write operation. READY is synchronous with the negative-going edge of CLK. This output requires a pullup resistor (1 kQ nominal). Do RESET 24 Counter and contro! fogic reset. When active (low), the counter is asynchronously reset to zero while = the control logic is asynchronously initialized to the proper state as determined by the mode control inputs. The output register is not affected by RESET. ALI/ROO 15 Register load input/register load output (open drain). This pin can be used as an input to directly load the output register, or it can be used as an output to detect whenever the output register has been loaded. When used as an output, a pullup resistor {1 kQ nominal) is required. See read timing diagrams for additional details. Vec 28 Power supply voltage. WE 25 Write enable input. When active (law) in conjunction with ES low, the data present on D0-D7 will be asynchronously loaded into the counter as selected by LSB/MSB. See write timing diagrams for additional details. Texas EXAS 2-595 INSTRUMENTS POST OFFICE BOX 225012 @ DALLAS. TEXAS 75265