BCM5704C
®
DUAL 10/100/1000BASE-T CONTROLLER WITH INTEGRATED TRANSCEIVER
•Single-chip, dual-port solution for dual LAN on Motherboard
(LoM) and network interface card (NIC) applications
•Two integrated 10BASE-T/100BASE-TX/1000BASE-T
transceivers
•Two 10/100/1000 triple-speed MACs
•Single host interface
- PCI v2.2 32/64-bit, 33/66 MHz
- PCI-X v1.0 64-bit, 66/100/133 MHz
•Dual ultra-deep 64-KB on-chip packet buffer
•Dual high-speed RISC cores with 16-KB caches
- Programmable, in-line packet classification
•SMBus 2.0 controller
•On-chip power circuit controller and Wake on LAN power
switching circuit
•Performance features
•TCP, IP, UDP checksum
•TCP segmentation
•CPU task offload
•Adaptive interrupts
•Ultra-deep 64-KB packet buffer
•Robust manageability
•PXE 2.0 remote boot
•Alert specification forum—ASF 1.0 support
•Wake on LAN (WoL)
•Out-of-box WoL
•Intelligent Platform Management Interface (IPMI), ver. 1.5
•Statistic gathering (SNMP MIB II, Ethernet-like MIB, Ethernet
MIB)
•Comprehensive diagnostic and configuration software suite
•ACPI 1.1a-compliant (multiple power modes)
•Advanced network features
•Priority queuing—802.1p Layer 2 priority encoding; support
for four priority queues
•Virtual LANs—802.1q VLAN tagging; support for up to 64
VLANs
•Jumbo frames (9 KB)
•802.3x flow control
•Advanced server features
•Link aggregation—802.3ad, GEC/FEC, Smart Load Balancing
(supports heterogeneous teams)
•Heterogeneous, mixed speed failover
•Hot-plug PCI support
•Low-power, 0.13-µm CMOS design
•300-pin HBGA package
•3.3V I/Os (5V tolerant)
JTAG
•Industry’s smallest dual 10/100/1000 MAC/PHY solution—
power and space optimized for LoM and low-profile NIC
applications
•Completely backward compatible:
•To existing 10/100 network infrastructure
•To existing PCI based desktop and server platforms
•Futureproof
•PCI-X interface, on-chip programmable CPUs, ASF support
•Performance focused—optimized for throughput and CPU
utilization
•Adaptive interrupts
•PCI-X—eliminates PCI bottlenecks
•Ultra-deep 64-KB packet buffer—lowers CPU utilization,
avoids PCI congestion
•Networking task offloads reduces utilization level of CPU
•Robust and highly manageable
•PXE 2.0, ACPI 1.1, Wake on LAN, ASF 1.0, IPMI
•Integrated cable testing (link quality, length, pair skew, pair
polarity, pair swap)
•Advanced features
•VLAN, priority queuing, jumbo frames
•RISC processors for advanced packet classification
•Server class reliability, availability and performance features
•Link aggregation and load balancing
- Switch-dependent
• 802.3ad (LACP), generic trunking (GEC/FEC)
- Switch- and NIC-independent
• Smart Load Balancing (unique technology that supports
heterogeneous teams and can operate with any switch)
•Failover
- Smart Load Balancing allows heterogeneous failover
•Hot-plug PCI
•Low power for zero airflow implementations
•0.13-µm CMOS design
•Advanced power management
•Space savings for LoM
•300-pin HBGA package
•No external memory
•Integrated power circuitry
FEATURES SUMMARY OF BENEFITS
OVERVIEW
®
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: info@broadcom.com
Web: www.broadcom.com
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
5704C-PB03-R 5/7/04
Broadcom®, the pulse logo, and Connecting everything® are trademarks of Broadcom Corporation and/
or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the
property of their respective owners.
The BCM5704C is a fully integrated dual-port, 10/100/1000BASE-T
Gigabit Ethernet media access control and physical layer transceiver
solution for high-performance network applications. The BCM5704C is
a highly integrated solution combining two triple-speed, IEEE 802.3-
compliant media access control (MAC), PCI, and PCI-X bus interfaces,
an on-chip buffer memory, and an integrated physical layer transceiver
in a single device. The BCM5704C is fabricated in a low-voltage, 0.13-
µm CMOS process providing a low-power system solution. By itself the
BCM5704C provides a complete single-chip dual-port Gigabit Ethernet
NIC or LoM solution.
The BCM5704C includes two 10/100/1000-Mbps Ethernet MACs with
full/half-duplex capability at all speeds and two 10/100/1000 copper
PHYs. Support for the following 802.3 functions is featured in the MAC:
VLAN tagging, layer 2 priority encoding, link aggregation, and full-
duplex flow control.
Although the device provides a single PCI v2.2/PCI-X v1.0 bus
interface, the device functions as if there are two logical software
interfaces. Interrupts are handled via two interrupt pins (INTA and
INTB) on the PCI connector. Individual MAC on-chip memory provides
packet buffering for higher performance and load balancing. Each MAC
function contains dual (TX and RX) on-chip processors enabling custom
frame processing features, including TCP segmentation.
The transceiver is fully compatible with the IEEE 802.3 standard for
auto-negotiation of speed. Additionally, several Plug and Play
enhancements have been added to make the device even more user
friendly. A link quality indicator LED gives installers an instant visual
indication if there are any issues with the wiring plant supporting
operation at the desired speed. This includes physical wiring defects or
channel conditions, such as excessive cable length, return loss, crosstalk,
echo, and noise. Broadcom’s remote cable management and diagnostics
software can be used with the device to provide remote management of
the cable and a first level of diagnostics and fault isolation. The
BCM5704C continually monitors various channel conditions. The
optional wirespeed capability allows the BCM5704C to force auto-
negotiation to be automatically limited by the speed that the channel can
reliably support, rather than the performance of the end equipment.
Target applications of the BCM5704C:
BCM5704C software support:
•Microsoft® Windows® 98, NT4.0, 2000, XP, NT64
•Linux® 2.2, 2.4
•Linux64®
•NetWare® 4.x, 5.x, 6.x
•PXE 2.0
•Solaris™ x86
PCI
ARBITER
PCI/PCI-X
PLL
PCI_CLK
XTAL_I
XTAL_O
CLOCK
GENERATOR
PCI/PCI-X
Bus
RDAC
PORT 1 LED Interface
P1_TRD+/- [3:0]
P2_TRD+/- [3:0]
JTAG
SEEPROM Interface
FLASH Interface
Regulator Control
General Purpose IO
(GPIO)
STATUS
MII
PCI MII
CONTROL
STATUS CONTROL
PCI FUNCTION #1
PCI FUNCTION #2
REGISTERS
REGISTERS
RX CPU BIAS
JTAG
LED
CONTROL
LED
CONTROL
FLASH
EEPROM
SMBus
REGULATOR
CONTROL
GPIO
ETHERNET
TRANSCEIVER
TX CPU
RX CPU
TX CPU
64KB BUFFER
MEMORY
64 KB BUFFER
MEMORY
MEDIA ACCESS
CONTROLLER (MAC)
ETHERNET
TRANSCEIVER
DMA
CONTROL
MEDIA ACCESS
CONTROLLER (MAC)
DMA
CONTROL
PORT 2 LED Interface
