ees AT 28 C256 Features @ Fast Read Access Time - 150 ns @ Automatic Page Write Operation Internal Address and Data Latches for 64-Bytes Internal Control Timer @ Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum 1 to 64-Byte Page Write Operation @ Low Power Dissipation 50 mA Active Current 200 pA CMOS Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology Endurance: 10* or 10 Cycles Data Retention: 10 Years Single 5V + 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout Full Military, Commercial, and Industrial Temperature Ranges Description The AT28C256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac- tured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 200 pA. (continued) Pin Configurations TSOP Pin Name Function Top View AQ-A14 Addresses aE: 7 38s ato CE Chip Enable ae aed 3 26 m vor os OE Output Enable We aia 3 23 B vos vos vec 4 7 a WE Write Enable Ais cps 5 20 7! yog ONO AT 10 18 |) vor 00-07 | Data Inputs/Outputs as 84 yp BR no aad 43 te at NC No Connect a3 114 a) a2 oc Don't Connect CERDIP, PDIP, PGA LCC, PLCC FLATPACK, SOIC Top View Top View Top View 4 ] 3 1 27 26 A? A14 VCC A132 as | a7 | ata | WE | A13 A\2 2 ME 5 | 2 | 20 | 24 | 25 AS_| Al2| VCC] AQ | AB 716 22 | 2a A3 | _A4 OE | Alt 9 | a 20 | 21 ai| a2| | CE [ato 13 2t voo 7 GND vos vor 14 381 301520 72) 13 | 15 | 17 | 18 Vos12 poaas vot | YO2| VO3| vos | VO6 Note: PLCC package pins 1 and 17 are DON'T CONNECT. AIMEL 256K (32K x 8) Paged CMOS E?7PROM OO06F 2-217AIMEL Description (Continued) The AT28C256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writ- ing of up to 64-bytes simultaneously. During a write cycle, the addresses and 1 to 64-bytes of data are internally latched, freeing the address and data bus for other opera- tions. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA POLLING of 07. Once the end of a write cycle has been detected a new access for a read or write can begin. Block Diagram Atmel's 28C256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inad- vertent writes. The device also includes an extra 64-bytes of E2PROM for device identification or tracking. Voc > DATA INPUTS/OUTPUTS GND o> _ WOO - VO7 agepesey oe DE. CE AND WE >| DATA LATCH WE "| ~ Logic INPUT/OUTPUT te 4 BUFFERS apres | 1 DECODER + Y-GATING INPUTS | | C >] CELL MATRIX X DECODER . IDENTIFICATION Absolute Maximum Ratings Temperature Under Bias................. -55C to +125C Storage Temperature... cee -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...........0.0. -0.6V to +6.25V All Output Voltages with Respect to Ground ............. -0.6V to Vcc + 0.6V Voltage on OE and A9 with Respect to Ground wee -0.6V to +13.5V 2-218 NOTICE: Stresses beyond those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT28C256 quees A 18 C256 Device Operation READ: The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The_outputs are put in the high impedance state when either CE or OE is high. This dual- line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cy- cle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of twc, a read operation will effectively be a poll- ing operation. PAGE WRITE: The page write operation of the AT28C256 allows 1 to 64-bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 addi- tional bytes. Each successive byte must be written within 150 us (tac) of the previous byte. If the tatc limit is ex- ceeded the AT28C256 will cease accepting data and com- mence the internal programming operation. All bytes dur- ing a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page write operation, A6 - A14 must be the same. The AO to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be pre- sented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28C256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in 1/06 toggling be- tween one and zero. Once the write has completed, 1/06 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. AIMEt DATA PROTECTION: If precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT2BC256 in the follow- ing ways: (a) Vcc sense - if Vcc is below 3.8V (typical) the write function is inhibited; (b) Vcc power-on delay - once Vcc has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write:_(c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typi- cal) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C256 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after twc the entire AT28C256 will be pro- tected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C256. This is done by pre- ceding the data to be written by the same 3-byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable com- mand sequence is issued. Power transitions do not dis- able SDP and SDP will protect the AT28C256 during power-up and power-down conditions. All command se- quences must conform to the page write timing specifica- tions. The data in the enable and disable command se- quences is not written to the device and the memory ad- dresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device with- out the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of two, read operations will effectively be polling operations. (continued) 2-219AIMEL Device Operation (Continued) DEVICE IDENTIFICATION: An extra 64-bytes of 2PROM memory are available to the user for device identification. By raising A9 to 12V + 0.5V and using ad- dress locations 7FCOH to 7FFFH the additional bytes may be written to or read from in the same manner as the regu- lar memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software code. Please see Sott- ware Chip Erase application note for details. DC and AC Operating Range AT28C256-15 AT28C256-20 AT28C256-25 AT28C256-35 ; Com. orc - 70C oc - 70C orc - 70C Coe eture (Case) Ind. -40C - 85C -40C - 85C -40C - 85C Mil. -85C - 126C -55C - 125C -65C - 125C -55C - 125C Voc Power Supply 5V + 10% 5V + 10% 5V + 10% 5V + 10% Operating Modes Mode CE OE WE vO Read VIL Vit ViH DouT Write @) ViL Vin Vit Din Standby/MWrite Inhibit VIH x) Xx High Z Write Inhibit X x ViIH Waite Inhibit x ViL x Output Disable Xx Vin xX High Z Chip Erase Vit Vu ) Vit High Z Notes: 1. X can be Viz or Vin. 3. VH = 12.0V + 0.5V. 2. Refer to AC Programming Waveforms. DC Characteristics Symbol Parameter Condition Min Max Units lu Input Load Current Vin = OV to Voc + 1V 10 pA Ito Output Leakage Current Vio = OV to Vcc 10 pA isp1 Vcc Standby Current CMOS CE = Vcc - 0.3V to Veo + 1V Gom., Ind. 200 HA Mil. 300 yA Isp Voc Standby Current TTL CE = 2.0V to Voc + 1V 3 mA lec Vcc Active Current f = 5 MHz; lour=OmA 50 mA Vit Input Low Voltage 0.8 Vv VIH Input High Voltage 2.0 Vv Voi Output Low Voltage lo. =2.1mA 45 Vv VoH Output High Voltage lou = -400 pA 2.4 Vv 2-220 AT28C256 uuuees AT 28 C256 AC Read Characteristics AT28C256-15 | AT28C256-20 | AT28C 256-25 | AT28C 256-35 Symbol Parameter Min Max Min Max Min Max Min Max Units tacc Address to Output Delay 150 200 250 350 ns tee CE to Output Delay 150 200 250 350 | ns toe ?) OE to Output Delay 0 70 0 80 0 100} 0 100] ns tor 4) | CE or OE to Output Float 0 50 0 55 0 60 0 70 ns Output Hold from OE, CE or toH Address, whichever 0 0 0 0 ns occurred first AC Read Waveforms *:* ADDRESS <[ ADDRESS VALID CE tcE ToT ____ > OE ' t0E tOH > l acc > HIGH Z OUTPUT g { OUTPUT VALID Notes: 1. CE may be delayed up to tacc - tce after the address 3. tor is specified from OE or CE whichever occurs first transition without impact on tacc. (C_ = 5 pF). 2. OE may be delayed up to tce - tok after the falling 4. This parameter is characterized and is not 100% tested. edge of CE without impact on tce or by tacc - toe after an address change without impact on tacc. Input Test Waveforms and Output Test Load Measurement Level sov 3.0V AC Ac 1.8K DRIVING MEASUREMENT OUTPUT LEVELS LEVEL PIN 0.0V ta, tr < Sns 1.3K t 100 pF Pin Capacitance (f = 1 MHz, T = 25C) Typ Max Units Conditions CIN 4 6 pF Vin = OV CouTt 8 12 pF Vout = 0V Note: 1. This parameter is characterized and is not 100% tested. ANMEL 2221AC Write Characteristics ce __ Symbol Parameter Min Max Units tas, toes Address, OE Set-up Time 0 ns taH Address Hold Time 50 ns tcs Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns twp Write Pulse Width (WE or CE) 100 ns tos Data Set-up Time 50 ns (DH, tOEH Data, OE Hold Time 0 ns tov Time to Data Valid NR Note: 1. NR =No Restriction AC Write Waveforms WE Controlled CE Controlled 2-222 ADDRESS a WAST) b- tAH CE aN a lon 1087] WE - tDV -}-- 1DS | |-tDH DATA IN en OE I oN 1088 ] tOEH a ADDRESS: 2 oe CE DATA AT28C256ees A128 C256 Page Mode Characteristics Symbol Parameter Min Max Units two Write Cycle Time AT28C256 10 ms AT28C256F 3.0 ms tas Address Set-up Time 0 ns taH Address Hold Time 50 ns tos Data Set-up Time 50 ns tDH Data Hold Time 0 ns twe Write Pulse Width 100 ns tBLc Byte Load Cycle Time 150 ps twPH Write Pulse Width High 50 ns Page Mode Write Waveforms "') OF tWP; tWPH tBLC WE tAS -\. _y = -\tAH AQ -A14 t- : _-tDH / vi VALID ADD! x x ) x "1Ds 7 DATA VALID DATA, i BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 62 BYTE 63 L.-tWC _ Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. Chip Erase Waveforms VIH CE VIL tg = ty = 5 psec (min.) tw = 10 msec (min.) VH = 12.0V + 0.5V 2-223AIMEL Software Data ' Protection Enable Algorithm LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA AG TO ADDRESS 5555 WRITES ENABLED ) LOAD DATA XX TO ANY ADDRESS 4) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE Notes for software program code: 1. Data Format: 1/07 - I/O0 (Hex); Address Format: A14 - AO (Hex). Software Data Protection Disable Algorithm LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA xx To ANY ADDRESS * 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period LOAD LAST BYTE even if no other data is loaded. TO 4. 1 to 64-bytes of data are loaded. LAST ADDRESS Software Protected Write Cycle Waveforms ":) EXIT DATA PROTECT STATE) So A OE -, Pen A CE VL NIN LN FON FNS WR tWPH- tBLCi-- _ : : eA Sy oe weg ENN OO ~| tAH [| tDH . oe AQ - A5 Neve ADDRESS, , _ x iL Agata 5555 2AAA 5555 / Mh _ Mh ma _| X\ PAGE ADDRESS, a ee cu i an oy " Af oy 7 5 YA ~ DATA x AA 55 t no x . x y - a (hewn a. _. oi BYTE 0 BYTE 62 BYTE 63 m= two or Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 2. OE must be high only when WE and CE are both low. 2-224 AT28C256 cuesmes {129256 Data Polling Characteristics Symbol Parameter Min Typ Max Units tDH DataHold Time _0 ns tOEH OE Hold Time 0 ns toe OE to Output Delay (2) ns twr Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. Data Polling Waveforms = aS NS NS NS NL tOE HIGH Z =| WR WO7 Sy een Ol a/ AO-A4. AN Xn SX OA Toggle Bit Characteristics " Symbol Parameter Min Typ Max Units {DH Data Hold Time 10 ns toEH GE Hold Time 10 ns toe OE to Output Delay 2) ns toEHP OE High Pulse 150 ns twa Write Recovery Time 0 ns Notes: 1, These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. Toggle Bit Waveforms: * WE y eT NS NS VS NSN m tOEH oe . 4 af fo __ OE \ /f- \ Jf \ ae tOE tOH HIGH Z pS et 06 a / __ Lo tWR Notes: 1. Toggling either OE or CE or both OE and CE will 3. Any address location may be used but the address operate toggle bit. should not vary. 2. Beginning and ending state of 1/06 will vary. AIMEL 2-225AIMEL NORMALIZED SUPPLY CURRENT vs. 13 TEMPERATURE N OY 4- : i m 1.2] | __ ! ' 14 \ ! 2 104 > ; d , 984 : . ! c | TT Cc os | i : 55 25 5 35 65 95 125 Temperature (C) NORMALIZED SUPPLY CURRENT vs. 4 ADDRESS FREQUENCY N * : : " wel Pf a | | i nee | ; 0.8 | d Veo = 5V | 071 _T=25C | C | C 06 : \ 0 1 2 3 4 5 Frequency (MHz) NORMALIZED SUPPLY CURRENT vs. ha SUPPLY VOLTAGE nt - 4 c c ; 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) 2-226 AT28C256 eueuuensees AT OS C256 Ordering Information AIMEL tacc Ioc (mA) Ordering Code Pack Oo ti (ns) | Active | Standby g Bonage peration Range 150 50 0.2 AT28C256(E,F)-15UC 32J Commercial AT28C256(E,F)-15PC 28P6 (0C to 70C) AT28C256(E,F)-15SC 28S AT28C256(E,F)-15TC 28T AT28C256(E,F)-15J1 32J Industrial AT28C256(E,F)-15Pl 28P6 (-40C to 85C) AT28C256(E,F)-15S1 28S AT28C256(E,F)-15TI 28T 50 0.3 AT28C256(E,F)-15DM/883 28D6 Mititary/883C AT28C256(E,F)-15FM/883 28F Class B, Fully Comptiant AT28C256(E,F)-15LM/883 32L (-55C to 125C) AT28C256(E,F)-15UM/883 28U 200 50 0.2 AT28C256(E,F)-20UC 32J Commercial AT28C256(E,F)-20PC 28P6 (0C to 70C) AT28C256(E,F)}-20SC 28S AT28C256(E,F)-20TC 28T AT28C256(E,F)-20J1 32u Industrial AT28C256(E,F)-20PI 28P6 (-40C to 85C) AT28C256(E,F)-20SI 28S AT28C256(E,F)-20T| 28T 50 0.3 AT28C256(E,F)-20DM/883 28D6 Military/883C AT28C256(E,F)-20FM/883 28F Class B, Fully Compliant AT28C256(E,F)-20LM/883 32L (-55C to 125C) AT28C256(E,F)-20UM/883 28U 250 50 0.2 AT28C256(E,F)-25JC 32J Commercial AT28C256(E,F)-25PC 28P6 (0C to 70C) AT28C256-W DIE AT28C256(E,F)-25J! 32J Industrial AT28C256(E,F)-25PI 28P6 (-40C to 85C) 50 0.3 AT28C256(E,F)-25DM/883 28D6 Military/883C AT28C256(E,F)-25FM/883 28F Class B, Fully Compliant AT28C256(E,F)-25LM/883 32L (-55C to 125C) AT28C256(E,F)-25UM/883 28uU AT28C256(E,F)-35UM/883 28U 50 0.2 AT28C256-W DIE Commercial (0C to 70C) (continued) 2-227ANMEL rey Ordering Information (Continued) tacc lec (mA) Ordering Code Package Operation Range (ns) | Active | Standby 9 9 P 9 150 8) 50 0.35 5962-88525 16 UX 28U Military/883C 5962-88525 16 XX 28D6 Class B, Fully Compliant 5962-88525 16 YX 32L (-55C to 125C) 5962-88525 16 ZX 28F 5962-88525 15 UX 28U Military/883C 5962-88525 15 XX 28D6 Class B, Fully Compliant 5962-88525 15 YX 32L (-55C to 125C) 5962-88525 15 ZX 28F 5962-88525 14 UX 28U Military/883C 5962-88525 14 XX 28D6 Class B, Fully Compliant 5962-88525 14 YX 32L (-55C to 125C) 5962-88525 14 ZX 28F 50 0.35 5962-88525 08 UX 28U Military/883C 5962-88525 08 XX 28D6 Class B, Fully Compliant 5962-88525 08 YX 32L (-55C to 125C) 5962-88525 08 ZX 28F 5962-88525 07 UX 28U Military/883C 5962-88525 07 XX 28D6 Class B, Fully Compliant 5962-88525 07 YX 32L (-55C to 125C) 5962-88525 07 ZX 28F 5962-88525 06 UX 28U Military/883C 5962-88525 06 XX 28D6 Class B, Fully Compliant 5962-88525 06 YX 32L (-55C to 125C) 5962-88525 06 ZX 28F 200 ) 50 0.35 5962-88525 12 UX 28U Military/883C 5962-88525 12 XX 2806 Class B, Fulty Compliant 5962-88525 12 YX 32L (-55C to 125C) 5962-88525 12 ZX 28F 50 0.35 5962-88525 04 UX 28U Military/883C 5962-88525 04 XX 28D6 Class B, Fully Compliant 5962-88525 04 YX 32L (-55C to 125C) 5962-88525 04 ZX 28F | 250 ) 50 0.35 5962-88525 13 UX 2BU Military/883C 5962-88525 13 XX 28D6 Class B, Fully Compliant 5962-88525 13 YX 32L (-55C to 125C) 5962-88525 13 ZX 28F 5962-88525 11 UX 28U Military/883C | 5962-88525 11 XX 28D6 Class B, Fully Compliant 5962-88525 11 YX 32L (-55C to 125C) 5962-88525 11 ZX 28F (continued) 2-228 AT28C256 sumeees AT 28C256 Ordering Information (Continued) tacc Icc (MA) Ordering Code oO; (ns) Active | Standby rdering Cod Package peration Range 250 50 0.35 5962-88525 05 UX 28U Military/883C 5962-88525 05 XX 28D6 Class B, Fully Compliant 5962-88525 05 YX 32L (-55C to 125C) 5962-88525 05 ZX 28F 5962-88525 03 UX 28U Military/883C 5962-88525 03 XX 28D6 Class B, Fully Compliant 5962-88525 03 YX 32L (-55C to 125C) 5962-88525 03 ZX 28F 300 50 0.35 5962-88525 10 UX 28U Military/883C 5962-88525 10 XX 28D6 Class B, Fully Compliant 5962-88525 10 YX 32L (-55C to 125C} 5962-88525 10 ZX 28F 50 0.35 5962-88525 02 UX 28U Military/883C 5962-88525 02 XX 28D6 Class B, Fully Compliant 5962-BB525 02 YX 32L (-55C to 125C) 5962-88525 02 ZX 28F 350 50 0.35 5962-88525 09 UX 28U Military/883C 5962-88525 09 XX 28D6 Class B, Fully Compliant 5962-88525 09 YX 32L (-55C to 125C) 5962-88525 09 ZX 28F 50 0.35 5962-88525 01 UX 28U Military/883C 5962-88525 01 XX 28D6 Class B, Fully Compliant 5962-88525 01 YX 32L (-55C to 125C) 5962-88525 01 ZX 28F Notes: 1. Electrical specifications for these speeds are defined by Standard Microcircuit Drawing 5962-88525. 2. See Valid Part Number table below. 3. SMD specifies Software Data Protection feature for device type, although Atmel product supplied to every device type in the SMD is 100% tested for this feature. Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28C256 15 JC, JI, PC, PI, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883 AT28C256E 15 JC, JI, PC, Pl, SC, SI, TC, Tl, DM/883, FM/883, LM/883, UM/883 AT28C256F 15 JC, JI, PC, Pl, SC, SI, TC, Tl, DM/883, FM/883, LM/883, UM/883 AT28C256 20 JC, JI, PC, PI, SC, SI, TC, Tl, DM/883, FM/883, LM/883, UM/883 AT28C256E 20 JC, JI, PC, Pl, SC, SI, TC, Tl, DM/883, FM/883, LM/883, UM/883 AT28C256F 20 JC, JI, PC, PI, SC, SI, TC, Tl, DM/883, FM/883, LM/883, UM/883 AT28C256 25 JC, JI, PC, Pi, SC, SI, TC, Tl, DM/883, FM/883, LM/883, UM/883 AT28C256E 25 JC, Ji, PC, Pl, SC, SI, TC, Tl, DM/883, FM/883, LM/883, UM/883 AT28C256F 25 JC, JI, PC, Pl, SC, SI, TC, TI, DM/883, FM/883, LM/883, UM/883 AT28C256 - Ww ATMEL 228AImEt Package Type 28D6 28 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual inline Package (Cerdip) 28F 28 Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 32L 32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 28P6 28 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28S 28 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28 Lead, Plastic Thin Small Outline Package (TSOP) 28U 28 Pin, Ceramic Pin Grid Array (PGA) Ww Die Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 2-230 AT28C256 sun