256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
SDRAM Unbuffered SODIMM
144pin Unbuffered SODIMM based on 512Mb B-die
64-bit Non ECC
Revision 1.2
March 2004
* Samsung Electronics reserves the right to change products or specification without notice.
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
Revision History
Revision 1.0 (January, 2004)
- First release
Revision 1.1 (February, 2004)
- Corrected typo.
Revision 1.2 (March. 2004)
- Corrected package dimension.
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
144Pin Unbuffered SODIMM based on 512Mb B-die(x8, x16)
Ordering Information
Operating Frequencies
Part Number Density Organization Component Composition Component
Package Height
M464S3354BTS-C(L)7A 256MB 32M x 64 32Mx16(K4S511632B) * 4EA 54-TSOP(II) 1,000mil
M464S6554BTS-C(L)7A 512MB 64M x 64 32Mx16(K4S511632B) * 8EA 1,250mil
7A
@CL3 @CL2
Maximum Clock Frequency 133MHz(7.5ns) 100MHz(10ns)
CL-tRCD-tRP(clock) 3 - 3 - 3 2 - 2 - 2
Feature
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs Latency (Access from column address)
Burst length (1, 2, 4, 8)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Serial presence detect with EEPROM
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
VSS
DQM0
DQM1
VDD
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
VSS
DQM4
DQM5
VDD
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VDD
DQ44
DQ45
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
DQ14
DQ15
VSS
NC
NC
**CLK0
VDD
RAS
WE
**CS0
**CS1
DU
VSS
NC
NC
VDD
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
DQ46
DQ47
VSS
NC
NC
**CKE0
VDD
CAS
**CKE1
A12
*A13
**CLK1
VSS
NC
NC
VDD
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
DQ21
DQ22
DQ23
VDD
A6
A8
VSS
A9
A10/AP
VDD
DQM2
DQM3
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VDD
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
DQ53
DQ54
DQ55
VDD
A7
BA0
VSS
BA1
A11
VDD
DQM6
DQM7
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VDD
Voltage Key
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
Pin Description
Pin Name Function Pin Name Function
A0 ~ A12 Address input (Multiplexed) WE Write enable
BA0 ~ BA1 Select bank DQM0 ~ 7 DQM
DQ0 ~ DQ63 Data input/output VDD Power supply (3.3V)
CLK0 ~ CLK1 Clock input VSS Ground
CKE0 ~ CKE1 Clock enable input SDA Serial data I/O
CS0 ~ CS1 Chip select input SCL Serial clock
RAS Row address strobe DU Don′t use
CAS Column address strobe NC No connection
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
PIN CONFIGURATION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A12 Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12
Column address : (x16 : CA0 ~ CA9)
BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
FUNCTIONAL BLOCK DIAGRAM
VDD
Vss
Three 0.1uF X7R 0603Capacitors To all SDRAMs
A0 ~ A12, BA0 & 1
CKE0
RAS
CAS
WE
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
per each SDRAM
DQn Every DQ pin of SDRAM
10Ω
CLK1
10Ω
10pF
U0
U1
CLK0
U2
U3
Serial PD
SDA
SCL
SA1 SA2SA0
WP
47KΩ
256MB, 32Mx64 Module (M464S3354BTS) (Populated as 1 bank of x16 SDRAM Module)
CS0
DQM0
DQM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM CS
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQM CS
UDQM
DQM2
DQM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQM CS
UDQM DQM7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDQM CS
UDQM
DQM4
DQM5
DQM6
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
FUNCTIONAL BLOCK DIAGRAM
VDD
Vss
Three 0.1 uF X7R 0603 Capacitors
per each SDRAM To all SDRAMs
A0 ~ A12, BA0 & 1
CKE0
RAS
CAS
WE
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U3
CKE1 SDRAM U4 ~ U7
U0/U4
U1/U5
CLK0/1
U2/U6
U3/U7
DQn Every DQ pin of SDRAM
10Ω
Serial PD
SDA
SCL
SA1 SA2SA0
WP
47KΩ
512MB, 64Mx64 Module (M366S6554BTS) (Populated as 2 bank of x16 SDRAM Module)
DQM7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM4
CS0
DQM0
DQM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM CS
UDQM DQM5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQM CS
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U6
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM CS
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM CS
UDQM
CS1
DQM6DQM2
LDQM CS LDQM CS LDQM CS
LDQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQM
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD1.0 * # of component W
Short circuit current IOS 50 mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD 3.0 3.3 3.6 V
Input high voltage VIH 2.0 3.0 VDDQ+0.3 V 1
Input low voltage VIL -0.3 0 0.8 V 2
Output high voltage VOH 2.4 - - V IOH = -2mA
Output low voltage VOL --0.4VIOL = 2mA
Input leakage current ILI -10 - 10 uA 3
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Parameter Symbol M464S3354BTS M464S6454BTS Unit
Min Max Min Max
Input capacitance (A0 ~ A12, BA0 ~ BA1)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0 ~ CKE1)
Input capacitance (CLK0 ~ CLK1)
Input capacitance (CS0 ~ CS1)
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
15
15
15
15
15
10
10
25
25
25
21
25
12
12
25
25
15
15
15
10
10
45
45
25
21
25
12
12
pF
pF
pF
pF
pF
pF
pF
1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Notes :
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition
Version
Unit Note
7A
Operating current
(One bank active) ICC1
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
400 mA 1
Precharge standby current
in power-down mode
ICC2P CKE ≤ VIL(max), tCC = 10ns 8
mA
ICC2PS CKE & CLK ≤ VIL(max), tCC =∞8
Precharge standby current
in non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 80
mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 40
Active standby current in
power-down mode
ICC3P CKE ≤ VIL(max), tCC = 10ns 25
mA
ICC3PS CKE & CLK ≤ VIL(max), tCC =∞25
Active standby current in
non power-down mode
(One bank active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 120 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 100 mA
Operating current
(Burst mode) ICC4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
520 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 800 mA 2
Self refresh current ICC6 CKE ≤ 0.2V
C 12 mA
L 6 mA
1. Measured with outputs open.
2. Refresh period is 64ms.
Notes :
M464S3354BTS (32M x 64, 256MB Module)
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition
Version
Unit Note
7A
Operating current
(One bank active) ICC1
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
520 mA 1
Precharge standby current
in power-down mode
ICC2P CKE ≤ VIL(max), tCC = 10ns 16
mA
ICC2PS CKE & CLK ≤ VIL(max), tCC =∞16
Precharge standby current
in non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 160
mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 80
Active standby current in
power-down mode
ICC3P CKE ≤ VIL(max), tCC = 10ns 50
mA
ICC3PS CKE & CLK ≤ VIL(max), tCC =∞50
Active standby current in
non power-down mode
(One bank active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 240 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 200 mA
Operating current
(Burst mode) ICC4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
640 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 920 mA 2
Self refresh current ICC6 CKE ≤ 0.2V
C 24 mA
L 12 mA
1. Measured with outputs open.
2. Refresh period is 64ms.
Notes :
M464S6554BTS (64M x 64, 512MB Module)
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
3.3V
1200Ω
870Ω
Output
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Vtt = 1.4V
50Ω
Output
50pF
Z0 = 50Ω
(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter Value Unit
AC input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
OPERATING AC PARAMETER
Notes :
(AC operating conditions unless otherwise noted)
Parameter Symbol Version Unit Note
7A
Row active to row active delay tRRD(min) 15 ns 1
RAS to CAS delay tRCD(min) 20 ns 1
Row precharge time tRP(min) 20 ns 1
Row active time tRAS(min) 45 ns 1
tRAS(max) 100 us
Row cycle time tRC(min) 65 ns 1
Last data in to row precharge tRDL(min) 2 CLK 2
Last data in to Active delay tDAL(min) 2 CLK + tRP -
Last data in to new col. address delay tCDL(min) 1 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 3
Number of valid output data CAS latency=3 2 ea 4
CAS latency=2 1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter Symbol 7A Unit Note
Min Max
CLK cycle
time
CAS latency=3 tCC
7.5 1000 ns 1
CAS latency=2 10
CLK to valid
output delay
CAS latency=3 tSAC
5.4 ns 1,2
CAS latency=2 6
Output data
hold time
CAS latency=3 tOH
3ns 2
CAS latency=2 3
CLK high pulse width tCH 2.5 ns 3
CLK low pulse width tCL 2.5 ns 3
Input setup time tSS 1.5 ns 3
Input hold time tSH 0.8 ns 3
CLK to output in Low-Z tSLZ 1ns2
CLK to output
in Hi-Z
CAS latency=3 tSHZ
5.4 ns
CAS latency=2 6
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A0 ~ A9,
A11, A12
Note
Register Mode register set H X L L L L X OP code 1,2
Refresh
Auto refresh HHLL LHX X 3
Self
refresh
Entry L 3
Exit L H LH HHXX3
HX XX 3
Bank active & row addr. H X L L H H X V Row address
Read &
column address
Auto precharge disable HXLHLHXV
LColumn
address
4
Auto precharge enable H 4,5
Write &
column address
Auto precharge disable H X LHLLX V LColumn
address
4
Auto precharge enable H 4,5
Burst stop H X L H H L X X 6
Precharge Bank selection HXLLHLX
VL X
All banks XH
Clock suspend or
active power down
Entry H L HX XX X
X
LV VV
Exit L H X X X X X
Precharge power down mode
Entry H L HX XX X
X
LH HH
Exit L H HX XX X
LV VV
DQM H V X 7
No operation command H X HX XX XX
LH HH
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Notes :
X
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
2.66
2.50
Units : Inches (Millimeters)
2-R 0.078 Min
(2.00 Min)
0.18
(4.60)
0.91
(23.20)
1.29
(32.80)
0.24
(6.0)
0.13
0.79
(20.00)
(3.30)
(63.60)
(67.56)
Detail Z
0.16 ± 0.0039
(4.00 ± 0.10)
0.06 ± 0.0039
(1.50 ± 0.1)
Tolerances : ± 0.006(.15) unless otherwise specified
The used device is 32Mx16 SDRAM, TSOPII
SDRAM Part No. : K4S511632B
2-φ 0.07
(1.80)
1.00
(25.40)
0.16 ± 0.039
(4.00 ± 0.10)
0.083
(2.10)
0.10
(2.50)
ZY
0.15
(3.70)
0.150 Max
0.04 ± 0.0039
(1.00 ± 0.10)
0.125 Min
(3.20 Min)
(3.80 Max)
0.157 Min
(4.00 Min)
1 59 61 143
2 60 62 144
0.03 TYP
0.024 ± 0.001
0.008 ±0.006
(0.200 ±0.150)
(0.600 ± 0.050)
(0.80 TYP)
0.100 Min
(2.540 Min)
Detail Y
PACKAGE DIMENSIONS : 32Mx64 (M464S3354BTS)
256MB, 512MB Unbuffered SODIMM
Rev. 1.2 March 2004
SDRAM
Tolerances : ±.006(.15) unless otherwise specified
The used device is 32Mx16 SDRAM, TSOPII
SDRAM Part No. : K4S511632B
2.66
2.50
Units : Inches (Millimeters)
2-R 0.078 Min
(2.00 Min)
0.18
(4.60)
0.91
(23.20)
1.29
(32.80)
0.24
(6.0)
0.13
0.79
(20.00)
(3.30)
(63.60)
(67.56)
Detail Z
0.16 ± 0.0039
(4.00 ± 0.10)
0.06 ± 0.0039
(1.50 ± 0.1)
2-φ 0.07
(1.80)
1.25
(31.75)
0.16 ± 0.039
(4.00 ± 0.10)
0.083
(2.10)
0.10
(2.50)
ZY
0.15
(3.70)
0.150 Max
0.04 ± 0.0039
(1.00 ± 0.10)
0.125 Min
(3.20 Min)
(3.80 Max)
0.157 Min
(4.00 Min)
1 59 61 143
2 60 62 144
0.03 TYP
0.024 ± 0.001
0.008 ±0.006
(0.200 ±0.150)
(0.600 ± 0.050)
(0.80 TYP)
0.100 Min
(2.540 Min)
Detail Y
PACKAGE DIMENSIONS : 64Mx64 (M464S6554BTS)
