R5F5631BDDFC#V0 - Renesas Electronics

RX63N Group, RX631 Group

Renesas MCUs

R01DS0098EJ0100 Rev.1.00 Page 1 of 172

Jun 13, 2012

Features

RX63N Group products incorporate an Ethernet controller while

RX631 Group products do not.

■32-bit RX CPU core

Max. operating frequency: 100 MHz

Capable of 165 DMIPS in operation at 100 MHz

Single precision 32-bit IEEE-754 floating point

Two types of multiply-and-accumulation unit (between memories and

between registers)

32-bit multiplier (fastest instruction execution takes one CPU clock cycle)

Divider (fastest instruction execution takes two CPU clock cycles)

Fast interrupt

CISC Harvard architecture with 5-stage pipeline

Variable-length instructions: Ultra-compact code

Supports the memory protection unit (MPU)

JTAG and FINE (two-line) debugging interfaces

■Low-power de s ig n an d a rch itecture

Operation from a single 2.7- to 3.6-V supply

Low power consumption: A product that supports all peripheral functions

draws only 500 μA/MHz.

RTC is capable of operation from a dedicated power supply (min. operating

voltage: 2 V).

Four low-power modes

■On-chip main flash memory, no wait states

Supports ROM-less versions and versions with up to 2 Mbytes of ROM

(ROM-less version: RX631 Group only)

100-MHz operation, 10-ns read cycle (no wait states)

384-Kbyte to 2-Mbyte capacities

User code programmable via the USB, SCI, or JTAG

■On-chip data flash memory

ROM-less or 32 Kbytes of ROM (reprogrammable up to 100,000 times)

Programming/erasing as background operations (BGOs)

■On-chip SRAM, no wait states

32- to 128-Kbyte capacities

For instructions and operands

Can provide backup on deep software standby

■DMA

DMAC: Four channels

DTC

EXDMAC: Two channels

Dedicated DMAC for the Ethernet controller: Single channel

■Reset and supply management

Power-on reset (POR)

Low voltage detection (LVD) with voltage settings

■Clock functions

External crystal oscillator or internal PLL for operation at 4 to 16 MHz

Internal 125-kHz LOCO and 50-MHz HOCO

Dedicated 125-kHz LOCO for the IWDT

■Real-time cl ock

Adjustment functions (30 seconds, leap year, and error)

Time capture function

(for capturing times in response to event-signal input on external pins)

■Independent watchdog timer

125-kHz LOCO clock operation

■Useful functions for IEC60730 compliance

Oscillation-stoppage detection, frequency measurement, CRC, IWDT, self-

diagnostic function for the A/D converter, etc.

■Various communications interfaces

Ethernet MAC (1) (not in RX631 Group products)

Host/function or OTG controller (1) and function controller (1) with full-

speed USB 2.0 transfer

CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 3

modules)

SCI with multiple functionalities (up to 13)

Choose from among asynchronous mode, clock-synchronous mode, smart-

card interface mode, simplified SPI, simplified I2C, and extended serial

mode.

I2C bus interface for transfer at up to 1 Mbps (up to 4)

RSPI for high-speed transfer (up to 3)

■External address space

Buses for high-speed data transfer (max. operating frequency of 50 MHz)

8 CS areas (8 × 16 Mbytes)

Multiplexed address data or separate address lines are selectable per area.

8-, 16-, or 32-bit bus space is selectable per area

Independent SDRAM area (128 Mbytes)

■Up to 20 extended-function timers

16-bit MTU2: input capture, output compare, PWM waveform output,

phase-counting mode (6 channels)

16-bit TPU: input capture, output compare, phase-counting mode (12

channels)

8-bit TMR (4 channels)

16-bit compare-match timers (4 channels)

■A/D converter for 1-MHz Operation

Up to 21 12-bit channels, and incorporating 1 sample-and-hold circuit

Up to 8 10-bit channels, and incorporating 1 sample-and-hold circuit

Addition of results of A/D conversion (in the 12-bit converter)

Self diagnosis (for the 10-bit converter)

■10-bit D/A converter: 2 channels

■Temperature sensor for measuring temperature wi thin

the chip

■Register wri t e pro te c tio n c an protect values in

important registers against overwriting.

■Up to 134 pins for GPIO

5-V tolerance, open drain, input pull-up, switchable driving ability

■Operating temp. range

–40°C to +85°C

PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch

PLQP0144KA-A 20 × 20mm, 0.5-mm pitch

PLQP0100KB-A 14 × 14mm, 0.5-mm pitch

PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch

PTLG0145KA-A 7 × 7mm, 0.5-mm pitch

PTLG 01 00KA- A 5 .5 × 5 .5mm, 0.5-mm pitc h

PLBG0176GA-A 13 × 13mm, 0.8-mm pitch

100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash

memory, Ethernet MAC, full-speed USB 2.0 host/function/OTG interface,

various communications interfaces including CAN, 10- & 12-bit A/D

converters, RTC

R01DS0098EJ0100

Rev.1.00

Jun 13, 2012

Features

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Jun 13, 2012

RX63N Group, RX631 Group 1. Overview

1. Overview

1.1 Outline of Specifications

Table 1.1 lists the specifications in outline, and table 1.2 gi ve s a compari s on of the functions of pro ducts in di fferent

packages.

Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will

differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Dif ferent Packages in the

RX63N/RX631 Group.

Table 1.1 Outline of Specifications (1/5)

Classification Module/Function Description

CPU CPU Maximum operating frequency: 100 MHz

32-bit RX CPU

Minimum instruction execution time: One instruction per state (cycle of the system

clock)

Address space: 4-Gbyte linear

Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Nine 32-bit registers

Accumulator: One 64-bit register

Basic instructions: 73

Floating-point instructions: 8

DSP instructions: 9

Addressing modes: 10

Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

On-chip 32-bit multiplier: 32 x 32  64 bits

On-chip divider: 32 / 32  32 bits

Barrel shifter: 32 bits

Memory protection unit (MPU)

FPU Single precision (32-bit) floating point

Data types and floating-point exceptions in conformance with the IEEE754 standard

Memory ROM Capacity: Romless, 768 Kbytes, 1 Mbyte, 1.5 Mbytes, 2 Mbytes

100 MHz, no-wait access

On-board programming: Four types

Off-board programming (parallel programmer mode)

RAM Capacity: 128 Kbytes

100 MHz, no-wait access

E2 data flash Capacity: 32 Kbytes

Programming/erasing: 100,000 times

MCU operating modes Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled

expansion mode (software switching)

Clock Clock generation circuit Main clock oscillator, subclock oscillator, low-speed/high-speed on-chip oscillator, PLL

frequency synthesizer, and IWDT-dedicated on-chip oscillator

Main-clock oscillation stoppage detection

Separate frequency-division and multiplication settings for the system clock (ICLK),

peripheral module clock (PCLK), FlashIF clock (FCLK) and external bus clock (BCLK)

The CPU and other bus masters run in synchronization with the system clock (ICLK):

Up to 100 MHz

Peripheral modules run in synchronization with the peripher al module clock (PCLK):

Up to 50 MHz

Flash IF run in synchronization with the flashIF clock (FCLK): Up to 50 MHz

Devices connected to the external bus run in synchronization with the external bus

clock (BCLK): Up to 50 MHz

Reset Pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer reset,

watchdog timer reset, deep software standby reset, and software reset

Voltage detection circuit When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or

internal interrupt is generated.

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RX63N Group, RX631 Group 1. Overview

Low power

consumption Low power

consumption facilities Module stop function

Four low power consumption modes

Sleep mode, all-module clock stop mode, software standby mode, and deep software

standby mode

Battery backup function

Interrupt Interrupt controller

(ICUb) Peripheral function interrupts: 187 sources

External interrupts: 16 (pins IRQ0 to IRQ15)

Software interrupts: One source

Non-maskable interrupts: 6 sources

Sixteen levels specifiable for the order of priority

External bus extension The external address space can be divided into nine areas (CS0 to CS7, SDCS), each

with independent control of access settings.

Capacity of each area: 16 Mbytes (CS0 to CS7), 128 Mbytes (SDCS)

A chip-select signal (CS0# to CS7#, SDCS#) can be output for each area.

Each area is specifiable as an 8-, 16-, or 32-bit bus space.

The data arrangement in each area is selectable as little or big endian (only for data).

SDRAM interface connectable

Bus format: Separate bus, multiplex bus

Wait control

Write buffer facility

DMA DMA controller

(DMAC) 4 channels

Three transfer modes: Normal transfer, repeat transfer, and block transfer

Activation sources: Software trigger, external interrupts, and interrupt requests from

peripheral functions

EXDMA controller

(EXDMACa) 2 channels

Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster

transfer

Single-address transfer enabled with the EDACK signal

Capable of direct data transfer to TFT LCD panels

Activation sources: Software trigger, external DMA requests (EDREQ), and interrupt

requests from peripheral functions

Data transfer controller

(DTCa) Three transfer modes: Normal transfer, repeat transfer, and block transfer

Activation sources: External interrupts and interrupt requests from peripheral functions

I/O ports Programmable I/O ports I/O ports for the 177-pin TFLGA (in the planning stage), 176-pin LFBGA (in the planning

stage), and 176-pin LQFP

I/O pins: 133

Input pins: 1

Pull-up resistors: 133

Open-drain outputs: 133

5-V tolerance: 18

I/O ports for the 145-pin TFLGA (in the planning stage) and 144-pin LQFP

I/O pins: 111

Input pins: 1

Pull-up resistors: 111

Open-drain outputs: 111

5-V tolerance: 18

I/O ports for the 100-pin LQFP

I/O pins: 78

Input pins: 1

Pull-up resistors: 78

Open-drain outputs: 78

5-V tolerance: 17

Table 1.1 Outline of Specifications (2/5)

Classification Module/Function Description

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RX63N Group, RX631 Group 1. Overview

Timers 16-bit timer pulse unit

(TPUa) (16 bits x 6 channels) x 2 unit

Maximum of 16 pulse-input/output possible

Select from among seven or eight counter-input clock signals for each channel

Input capture/output compare function

Output of PWM waveforms in up to 15 phases in PWM mode

Buffered operation and phase-counting mode (two phase encoder input) depending on

the channel

Support for cascade-connected operation (32 bits x 2 channels)

PPG output trigger can be generated

Capable of generating conversion start triggers for the A/D converters

Signals from the input capture pins are input via a digital filter

Clock frequency measuring method

Multi-function timer

pulse unit 2 (MTU2a) (16 bits x 6 channels) x 1 unit

Time bases for the 6 16-bit timer channels can be provided via up to 16 pulse-input/

output lines and three pulse-input lines

Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/

4, PCLK/16, PCLK/64, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5,

for which only four signals are available.

Input capture function

21 output compare/input capture registers

Complementary PWM output mode

Reset synchronous PWM mode

Phase-counting mode

Generation of triggers for A/D converter conversion

Digital filter

Signals from the input capture pins are input via a digital filter

PPG output trigger can be generated

Clock frequency measuring function

Frequency measuring

method (MCK) The MTU or unit 0 TPU module can be used to monitor the main clock, subclock,

HOCO clock, LOCO clock, and PLL clock for abnormal frequencies.

Port output enable 2

(POE2a) Controls the high-impedance state of the MTU’s waveform output pins

Programmable pulse

generator (PPG) (4 bits x 4 groups) x 2 units

Pulse output with the MTU2 or TPU output as a trigger

Maximum of 32 pulse-output possible

8-bit timers (TMR) (8 bits x 2 channels) x 2 units

Select from among seven internal clock signals (PCLK/1, PCLK/2, PCLK/8, PCLK/32,

PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal

Capable of output of pulse trains with desired duty cycles or of PWM signals

The 2 channels of each unit can be cascaded to create a 16-bit timer

Generation of triggers for A/D converter conversion

Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12

Compare match timer

(CMT) (16 bits x 2 channels) x 2 units

Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/

512)

Realtime clock (RTCa) Clock sources: Main clock, subclock

Clock and calendar functions

Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt

Battery backup operation

Time-capture facility for three values

Watchdog timer

(WDTA) 14 bits x 1 channel

Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/

512, PCLK/2048, PCLK/8192)

Independent watchdog

timer (IWDTa) 14 bits x 1 channel

Counter-input clock: IWDT-dedicated on-chip oscillator

Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,

dedicated clock/128, dedicated clock/256

Table 1.1 Outline of Specifications (3/5)

Classification Module/Function Description

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RX63N Group, RX631 Group 1. Overview

Communication

function Ethernet controller

(ETHERC) Input and output of Ethernet/IEEE 802.3 frames

Transfer at 10 or 100 Mbps

Full- and half-duplex modes

MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as

defined in IEEE 802.3u

Detection of Magic PacketsTM*1 or output of a "wake-on-LAN" signal (WOL)

Compliance with flow control as defined in IEEE 802.3x standards

Note 1. Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc.

DMA controller for

Ethernet controller

(EDMAC)

Alleviation of CPU loads by the descriptor control method

Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes

USB 2.0 host/function

module (USBa) Includes a UDC (USB Device Controller) and transceiver for USB 2.0

Host/function module: one port, function module: one port

Compliance with the USB 2.0 specification

Transfer rate: Full speed (12 Mbps)

Self-power mode and bus power are selectable

OTG (On the Go) operation is possible

Incorporates 2 Kbytes of RAM as a transfer buffer

Serial communications

interfaces (SCIc, SCId) 13 channels (SCIc: 12 channels + SCId: 1 channel)

SCIc

Serial communications modes: Asynchronous, clock synchronous, and smart-card

interface

Multi-processor function

On-chip baud rate generator allows selection of the desired bit rate

Choice of LSB-first or MSB-first transfer

Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12

Simple I2C

Simple SPI

SCId (The following functions are added to SCIc)

Supports the serial communications protocol, which contains the start frame and

information frame

Supports the LIN format

I2C bus interfaces

(RIIC) 4 channels (one of them is FM+)

Communication formats

I2C bus format/SMBus format

Supports the multi-master

Max. transfer rate: 1 Mbps (channel 0)

IEBus (IEB) 1 channel

Supports protocol control for the IEBus

Half-duplex asynchronous transfer

Multi-master operation

Broadcast communications function

Two selectable modes, differentiated by transfer rate

Note: • IEBus (Inter Equipment Bus) is a registered trademark of Renesas Electronics

Corporation.

CAN module (CAN) 3 channels

Compliance with the ISO11898-1 specification (standard frame and extended frame)

32 mailboxes each

Serial peripheral

interfaces (SPI) 3 channels

RSPI transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),

and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four

lines) or clock-synchronous operation (three lines)

Capable of handling serial transfer as a master or slave

Data formats

Switching between MSB first and LSB first

The number of bits in each transfer can be changed to any number of bits from 8 to 16,

or to 20, 24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with

each frame having up to 32 bits)

Buffered structure

Double buffers for both transmission and reception

Table 1.1 Outline of Specifications (4/5)

Classification Module/Function Description

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RX63N Group, RX631 Group 1. Overview

12-bit A/D converter (S12ADa) 1 unit (1 unit x 14 channels)

12-bit resolution

Conversion time: 1.0 s per channel (in operation with PCLK at 50 MHz)

Operating mode

Scan mode (single scan mode or continuous scan mode)

Sample-and-hold function

Reference voltage generation

Three ways to start A/D conversion

Conversion can be started by software, a conversion start trigger from a timer (MTU,

TPU, or TMR), or an external trigger signal.

A/D conversion of the temperature sensor output

10-bit A/D converter (ADb) 1 unit (1 unit x 8 channels)

10-bit resolution

Conversion time: 1.0 s per channel (in operation with PCLK at 50 MHz)

Operating mode

Scan mode (single scan mode or continuous scan mode)

External amplifier connection mode

Sample-and-hold function

Three ways to start A/D conversion

Conversion can be started by software, a conversion start trigger from a timer (MTU,

TPU, or TMR), or an external trigger signal.

D/A converter (DAa) 2 channels

10-bit resolution

Output voltage: 0 V to VREFH

Temper ature sensor 1 channel

Precision: ±1ºC

The voltage of the temperature is converted into a digital value by the 12-bit A/D

converter.

CRC calculator (CRC) CRC code generation for arbitrary amounts of data in 8-bit units

Select any of three generating polynomials:

X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1.

Generation of CRC codes for use with LSB-first or MSB-first communications is

selectable

Operating frequency Up to 100 MHz

Power supply voltage VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,

Vbatt = 2.0 V to 3.6 V

Operating temperature 40 to +85C (products with wide-temperature-range spec.)

Package 177-pin TFLGA (PTLG0177KA-A) (in the planning stage)

176-pin LFBGA (PLBG0176GA-A) (in the planning stage)

176-pin LQFP (PLQP0176KB-A)

145-pin TFLGA (PTLG0145KA-A) (in the planning stage)

144-pin LQFP (PLQP0144KA-A)

100-pin LQFP (PLQP0100KB-A)

On-chip debugging system E1 emulator (JTAG and FINE interfaces)

E20 emulator (JTAG interface)

Table 1.1 Outline of Specifications (5/5)

Classification Module/Function Description

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RX63N Group, RX631 Group 1. Overview

Table 1.2 Comparison of Functions for Different Packages in the RX63N/RX631 Group

Functions RX63N Group RX631 Group

Package

177-pin

176-pin 145-pin

144-pin 100-pin 177-pin

176-pin 145-pin

144-pin 100-pin

External bus

width External bus width 32 bits 16 bits 32 bits 16 bits

SDRAM area controller Available Not available Available Not available

DMA DMA controller Ch. 0 to 3 Ch. 0 to 3

EXDMA controller Ch. 0 and 1 Ch. 0 and 1

Data transfer controller Available Available

Timers 16-bit timer pulse unit Ch. 0 to 11 Ch. 0 to 5 Ch. 0 to 11 Ch. 0 to 5

Multi-function timer pulse unit 2 Ch. 0 to 5 Ch. 0 to 5

Port output enable 2 Available Available

Programmable pulse generator Ch. 0 and 1 Ch. 0 and 1

8-bit timers Ch. 0 to 3 Ch. 0 to 3

Compare match timer Ch. 0 to 3 Ch. 0 to 3

Realtime clock Available Available

Watchdog timer Available Available

Independent watchdog timer Available Available

Communication

function Ethernet controller Available Not available

DMA controller for Ethernet

controller Available Not available

USB 2.0 host/function module Ch. 0 and 1 ch0 Ch. 0 and 1 c h0

Serial communications interfaces

(SClc) Ch. 0 to 11 Ch. 0 to 3,

5, 6, 8 and 9 Ch. 0 to 11 Ch. 0 to 3,

5, 6, 8 and 9

Serial communications interfaces

(SCld) Ch. 12 Ch. 12

I2C bus interfaces Ch. 0 to 3 ch0, 2 Ch. 0 to 3 ch0, 2

IEBus Available Available

Serial peripheral interfaces ch0 to 2 Ch. 0 and 1 ch0 to 2 Ch. 0 and 1

CAN module For 1.5 M or more: Ch. 0 to 2,

For 1 M or less: Ch. 0 and 1 Ch. 0 and 1 For 1.5 M or more: Ch. 0 to 2,

For 1 M or less: Ch. 0 and 1 Ch. 0 and 1

12-bit A/D converter (channel) AN000 to 020 AN000 to 013 AN000 to 020 AN000 to 013

10-bit A/D converter (channel) AN0 to 7 AN0 to 7

D/A converter (resolution x channel) Ch. 0 and 1 ch1 Ch. 0 and 1 ch1

Temperature sensor Available Available

CRC calculator Available Available

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RX63N Group, RX631 Group 1. Overview

1.2 List of Products

Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no.

Table 1.3 List of Products (1/3)

Group Part No. Package ROM Capacity RAM Capacity E2Data Flash

Operating

Frequency

(Max.)

RX63N R5F563NACDFP PLQP0100KB-A 768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NADDFP PLQP0100KB-A 768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NACDFB PLQP0144KA-A 768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NADDFB PLQP0144KA-A 768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NACDLK PTLG0145KA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NADDLK PTLG0145KA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NACDFC PLQP0176KB-A 768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NADDFC PLQP0176KB-A 768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NACDLC PTLG0177KA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NADDLC PTLG0177KA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NACDBG PLBG0176GA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NADDBG PLBG0176GA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F563NBCDFP PLQP0100KB-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NBDDFP PLQP0100KB-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NBCDFB PLQP0144KA-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NBDDFB PLQP0144KA-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NBCDLK PTLG0145KA-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NBDDLK PTLG0145KA-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NBCDFC PLQP0176KB-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NBDDFC PLQP0176KB-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NBCDLC PTLG0177KA-A*11 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NBDDLC PTLG0177KA-A*11 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NBCDBG PLBG0176GA-A*11 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NBDDBG PLBG0176GA-A*11 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDCDFP PLQP0100KB-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDDDFP PLQP0100KB-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDCDFB PLQP0144KA-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDDDFB PLQP0144KA-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDCDLK PTLG0145KA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDDDLK PTLG0145KA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDCDFC PLQP0176KB-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDDDFC PLQP0176KB-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDCDLC PTLG0177KA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDDDLC PTLG0177KA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDCDBG PLBG0176GA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NDDDBG PLBG0176GA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NECDFP PLQP0100KB-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NEDDFP PLQP0100KB-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NECDFB PLQP0144KA-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NEDDFB PLQP0144KA-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NECDLK PTLG0145KA-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

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Jun 13, 2012

RX63N Group, RX631 Group 1. Overview

RX63N R5F563NEDDLK PTLG0145KA-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NECDFC PLQP0176KB-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NEDDFC PLQP0176KB-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NECDLC PTLG0177KA-A*12 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NEDDLC PTLG0177KA-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NECDBG PLBG0176GA-A*12 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F563NEDDBG PLBG0176GA-A*12 Mbyte 128 Kbytes 32 Kbytes 100 MHz

RX631 R5F5631ACDFP PLQP0100KB-A 768K Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631ADDFP PLQP0100KB-A 768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631ACDFB PLQP0144KA-A 768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631ADDFB PLQP0144KA-A 768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631ACDLK PTLG0145KA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631ADDLK PTLG0145KA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631ACDFC PLQP0176KB-A 768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631ADDFC PLQP0176KB-A 768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631ACDLC PTLG0177KA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631ADDLC PTLG0177KA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631ACDBG PLBG0176GA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631ADDBG PLBG0176GA-A*1768 Kbytes 128 Kbytes 32 Kbytes 100 MHz

R5F5631BCDFP PLQP0100KB-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631BDDFP PLQP0100KB-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631BCDFB PLQP0144KA-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631BDDFB PLQP0144KA-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631BCDLK PTLG0145KA-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631BDDLK PTLG0145KA-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631BCDFC PLQP0176KB-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631BDDFC PLQP0176KB-A 1 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631BCDLC PTLG0177KA-A*11 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631BDDLC PTLG0177KA-A*11 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631BCDBG PLBG0176GA-A*11 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631BDDBG PLBG0176GA-A*11 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DCDFP PLQP0100KB-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DDDFP PLQP0100KB-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DCDFB PLQP0144KA-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DDDFB PLQP0144KA-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DCDLK PTLG0145KA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DDDLK PTLG0145KA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DCDFC PLQP0176KB-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DDDFC PLQP0176KB-A 1.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DCDLC PTLG0177KA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DDDLC PTLG0177KA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DCDBG PLBG0176GA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631DDDBG PLBG0176GA-A*11.5 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631ECDFP PLQP0100KB-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

Table 1.3 List of Products (2/3)

Group Part No. Package ROM Capacity RAM Capacity E2Data Flash

Operating

Frequency

(Max.)

R01DS0098EJ0100 Rev.1.00 Page 10 of 172

Jun 13, 2012

RX63N Group, RX631 Group 1. Overview

Note 1. In the planning stage

Figure 1.1 How to Read the Product Part No.

RX631 R5F5631EDDFP PLQP0100KB-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631ECDFB PLQP0144KA-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631EDDFB PLQP0144KA-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631ECDLK PTLG0145KA-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631EDDLK PTLG0145KA-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631ECDFC PLQP0176KB-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631EDDFC PLQP0176KB-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631ECDLC PTLG0177KA-A*12 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631EDDLC PTLG0177KA-A 2 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631ECDBG PLBG0176GA-A*12 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5F5631EDDBG PLBG0176GA-A*12 Mbyte 128 Kbytes 32 Kbytes 100 MHz

R5S56310CDFC PLQP0176KB-A 0 Mbyte 128 Kbytes 0 Kbytes 100 MHz

Table 1.3 List of Products (3/3)

Group Part No. Package ROM Capacity RAM Capacity E2Data Flash

Operating

Frequency

(Max.)

Type of memory

F : Flash memory version

S : ROMless version

Package type, number of pins, and pin pitch

FC: LQFP/176/0.50

BG: LFBGA/176/0.80

LC : TFLGA/177/0.50

FB : LQFP/144/0.50

LK : TFLGA/145/0.50

FP : LQFP/100/0.50

ROM, RAM and E2 data flash capacity

E : 2 Mbytes/128 Kbytes/32 Kbytes

D: 1.5 Mbytes/128 Kbytes/32 Kbytes

B : 1 Mbyte/128 Kbytes/32 Kbytes

A : 768 Kbytes/128 Kbytes/32 Kbytes

0 : 0 bytes/128 Kbytes/0 bytes

Group name

3N : RX63N Group

31 : RX631 Group

Renesas MCU

Renesas semiconductor product

C: CAN not included

D: CAN included

Series name

RX600 Series

R 5 F 5 6 D F PCAN3

D: Products with wide-tempera ture-ranse

spec. (–40 to 85°C)

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RX63N Group, RX631 Group 1. Overview

1.3 Block Diagram

Figure 1.2 shows a block diagram.

Figure 1.2 Block Diagram

ETHERC : Ethernet controller

EDMAC : DMA controller for Ethernet controller

ICUb : Interrupt controller

DTCa : Data transfer controller

DMACA : DMA controller

EXDMACa : EXDMA controller

BSC : Bus controller

WDTA : Watchdog timer

IWDTa : Independent watchdog timer

CRC : CRC (cyclic redundancy check) calculator

SCIc, SCId : Serial communications interface

MPU : Memory protection unit

RSPI : Serial peripheral interface

CAN : CAN module

MTU2a : Multi-function timer pulse unit 2

POE2a : Port output enable 2

TPUa : 16-bit timer pulse unit

PPG : Programmable pulse generator

TMR : 8-bit timer

CMT : Compare match t imer

RTCa : Realtime clock

RIIC : I2C bus interface

IEB : IEBus controller

External bus

BSC

Operand bus

Instruction bus

Internal main bus 1

Clock

generati

on circuit

RX CPU

RAM

ROM

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

10-bit ADC × 8 channels

12-bit ADC × 21 channels

MTU2a × 6ch

10-bit DAC × 2 channel

RIIC × 4ch

USB 2.0 function module

CAN × 3ch

RTCa

POE2a

TPUa × 6ch (unit 1)

IEB

CMT × 2 channels (unit 1)

CMT × 2 channels (unit 0)

TMR × 2 channels (unit 1)

TMR × 2 channels (unit 0)

PPG (unit 1)

PPG (unit 0)

RSPI (unit 1)

RSPI (unit 0)

Internal main bus 2

DTCa

DMACA ×

4ch

ICUb

Temperature sensor

TPUa × 6ch (unit 0)

RSPI (unit 2)

USB 2.0 host/function module

Port D

Port E

Port F

Port G

Port H

Port J

EDMAC

ETHERC

EXDMACa

Internal peripheral buses 1 to 6

SCIc × 12ch

WDTA

E2 Data Flash

CRC

IWDTa

SCId × 1ch

MPU

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RX63N Group, RX631 Group 1. Overview

1.4 Pin Functions

Table 1.4 lists the pin functions.

Table 1.4 Pin Functi ons (1/6)

Classifications Pin Name I/O Description

Power supply VCC Input Power supply pin. Connect it to the system power supply.

Connect this pin to VSS via a 0.1-µF capacitor. The capacitor

should be placed close to the pin.

VCL Input Connect this pin to VSS via a 0.1-F capacitor. The capacitor

should be placed close to the pin.

VSS Input Ground pin. Connect it to the system power supply (0 V).

VBAT Input Backup power pin

Clock XTAL Output Pins for a crystal resonator. An external clock signal can be

input through the EXTAL pin.

EXTAL Input

BCLK Output Outputs the external bus clock for external devices.

SDCLK Output Outputs the clock dedicated for the SDRAM.

XCOUT Output Input/output pins for the subclock oscillator. Connect a crystal

resonator between XCOUT and XCIN.

XCIN Input

Operating mode control MD Input Pins for setting the operating mode. The signal levels on these

pins must not be changed during operation.

System control RES# Input Reset signal input pin. This LSI enters the reset state when this

signal goes low.

EMLE Input Input pin for the on-chip emulator enable signal. When the on-

chip emulator is used, this pin should be driven high. When not

used, it should be driven low.

BSCANP Input Boundary scan enable pin. Boundary scan is enabled when this

pin goes high. When not used, it should be driven low.

On-chip emulator FINEC Input Fine interface clock pin

FINED I/O Fine interface pin

TRST# Input On-chip emulator or boundary scan pins. When the EMLE pin is

driven high, these pins are dedicated for the on-chip emulator.

TMS Input

TDI Input

TCK Input

TDO Output

TRCLK Output This pin outputs the clock for synchronization with the trace

data.

TRSYNC# Output This pin indicates that output from the TRDATA0 to TRDATA3

pins is valid.

TRDATA0 to TRDATA3 Output These pins output the trace information.

Address bus A0 to A23 Output Output pins for the address.

Data bus D0 to D15 I/O Input and output pins for the bidirectional data bus.

Multiplexed bus A0/D0 to A15/D15 I/O Address/data multiplexed bus

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RX63N Group, RX631 Group 1. Overview

Bus control RD# Output Strobe signal which indicates that reading from the external bus

interface space is in progress.

WR# Output Strobe signal which indicates that writing to the external bus

interface space is in progress, in 1-write strobe mode.

WR0# to WR3# Output Strobe signals which indicate that either group of data bus pins

(D7 to D0 and D15 to D8) is valid in writing to the external bus

interface space, in byte strobe mode.

BC0# to BC3# Output Strobe signals which indicate that either group of data bus pins

(D7 to D0 and D15 to D8) is valid in access to the external bus

interface space, in 1-write strobe mode.

ALE Output Address latch signal when address/data multiplexed bus is

selected.

CKE Output Output pin for SDRAM clock enable signals.

SDCS# Output Output pin for SDRAM chip select signals.

RAS# Output Output pin for SDRAM row address strobe signals.

CAS# Output Output pin for SDRAM column address strobe signals.

Bus control WE# Output Output pin for SDRAM write enable signals.

DQM0 to DQM3 Output Output pins for SDRAM I/O data mask enable signals.

CS0# to CS7# Output Select signals for CS area.

WAIT# Input Input pins for wait request signals in access to the external

space.

EXDMA controller EDREQ0, EDREQ1 Input pins for external DMA transfer requests.

EDACK0, EDACK1 Output pins for single address transfer acknowledge signals.

Interrupt NMI Input Non-maskable interrupt request signal.

IRQ0 to IRQ15 Input Maskable interrupt request signals.

Multi-function timer pulse

unit 2 MTIOC0A, MTIOC0B

MTIOC0C, MTIOC0D I/O The TGRA0 to TGRD0 input capture input/output compare

output/PWM output pins.

MTIOC1A, MTIOC1B I/O The TGRA1 and TGRB1 input capture input/output compare

output/PWM output pins.

MTIOC2A, MTIOC2B I/O The TGRA2 and TGRB2 input capture input/output compare

output/PWM output pins.

MTIOC3A, MTIOC3B

MTIOC3C, MTIOC3D I/O The TGRA3 to TGRD3 input capture input/output compare

output/PWM output pins.

MTIOC4A, MTIOC4B

MTIOC4C, MTIOC4D I/O The TGRA4 to TGRD4 input capture input/output compare

output/PWM output pins.

MTIC5U, MTIC5V

MTIC5W Input The TGRU5, TGRV5, and TGRW5 input capture input/dead

time compensation input pins.

MTCLKA, MTCLKB

MTCLKC, MTCLKD Input Input pins for external clock signals.

Port output enable 2 POE0# to POE3#

POE8# Input Input pins for request signals to place the MTU large-current

pins in the high impedance state.

Table 1.4 Pin Functi ons (2/6)

Classifications Pin Name I/O Description

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RX63N Group, RX631 Group 1. Overview

16-bit timer pulse unit TIOCA0, TIOCB0

TIOCC0, TIOCD0 I/O The TGRA0 to TGRD0 input capture input/output compare

output/PWM output pins.

TIOCA1, TIOCB1 I/O The TGRA1 and TGRB1 input capture input/output compare

output/PWM output pins.

TIOCA2, TIOCB2 I/O The TGRA2 and TGRB2 input capture input/output compare

output/PWM output pins.

TIOCA3, TIOCB3

TIOCC3, TIOCD3 I/O The TGRA3 to TGRD3 input capture input/output compare

output/PWM output pins.

TIOCA4, TIOCB4 I/O The TGRA4 and TGRB4 input capture input/output compare

output/PWM output pins.

TIOCA5, TIOCB5 I/O The TGRA5 and TGRB5 input capture input/output compare

output/PWM output pins.

TCLKA, TCLKB

TCLKC, TCLKD Input Input pins for external clock signals.

TIOCA6, TIOCB6

TIOCC6, TIOCD6 I/O The TGRA6 to TGRD6 input capture input/output compare

output/PWM output pins.

TIOCA7, TIOCB7 I/O The TGRA7 and TGRB7 input capture input/output compare

output/PWM output pins.

TIOCA8, TIOCB8 I/O The TGRA8 and TGRB8 input capture input/output compare

output/PWM output pins.

TIOCA9, TIOCB9

TIOCC9, TIOCD9 I/O The TGRA9 to TGRD9 input capture input/output compare

output/PWM output pins.

TIOCA10, TIOCB10 I/O The TGRA10 and TGRB10 input capture input/output compare

output/PWM output pins.

TIOCA11, TIOCB11 I/O The TGRA11 and TGRB11 input capture input/output compare

output/PWM output pins.

TCLKE, TCLKF

TCLKG, TCLKH Input Input pins for external clock signals.

Programmable pulse

generator PO0 to PO31 Output Output pins for the pulse signals.

8-bit timer TMO0 to TMO3 Output Output pins for the compare match signals.

TMCI0 to TMCI3 Input Input pins for the external clock signals that drive for the

counters.

TMRI0 to TMRI3 Input Input pins for the counter-reset signals.

Serial communications

interface (SCIc) Asynchronous mode/clock synchronous mode

SCK0 to SCK11 I/O Input/output pins for clock signals.

RXD0 to RXD11 Input Input pins for data reception.

TXD0 to TXD11 Output Output pins for data transmission.

CTS0# to CTS11# Input Transfer start control input pins

RTS0# to RTS11# Output Transfer start control output pins

Simple I2C mode

SSCL0 to SSCL11 I/O Input/output pins for the I2C clock

SSDA0 to SSDA11 I/O Input/output pins for the I2C data

Serial communications

interface (SCIc) Simple SPI mode

SCK0 to SCK11 I/O Input/output pins for the clock

SMISO0 to SMISO11 I/O Input/output pins for slave transmit data.

SMOSI0 to SMOSI11 I/O Input/output pins for master transmit data.

SS0# to SS11# Input Input pins for chip select signals

Table 1.4 Pin Functi ons (3/6)

Classifications Pin Name I/O Description

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RX63N Group, RX631 Group 1. Overview

Serial communications

interface (SCId) Asynchronous mode/clock synchronous mode

SCK12 I/O Input/output pin for clock signals.

RXD12 Input Input pin for data reception.

TXD12 Output Output pin for data transmission.

CTS12# Input Transfer start control input pins

RTS12# Output Transfer start control output pins

Simple I2C mode

SSCL12 I/O Input/output pins for the I2C clock

SSDA12 I/O Input/output pins for the I2C data

Simple SPI mode

SCK12 I/O Input/output pins for the clock

SMISO12 I/O Input/output pins for slave transmit data.

SMOSI12 I/O Input/output pins for master transmit data.

SS12# Input Input pins for chip select signals

Extended serial mode

RXDX12 Input Input pin for receive data

TXDX12 Output Output pin for transmit data

SIO12 I/O Input/output pin for transfer data

I2C bus interface SCL0[FM+],

SCL1 to SCL3 I/O Input/output pin for clocks. Bus can be directly driven by the

N-channel open drain output.

SDA0[FM+],

SDA1 to SDA3 I/O Input/output pin for data. Bus can be directly driven by the

N-channel open drain output.

Ethernet controller REF50CK Input 50-MHz reference clock. This pin inputs reference signals for

transmission/reception timings in RMII mode.

RMII_CRS_DV Input Indicates that there are carrier detection signals and valid

receive data on RMII_RXD1 and RMII_RXD0 in RMII mode.

RMII_TXD0, RMII_TXD1 Output 2-bit transmit data in RMII mode.

RMII_RXD0, RMII_RXD1 Input 2-bit receive data in RMII mode.

RMII_TXD_EN Output Output pin for data transmit enable signals in RMII mode.

RMII_RX_ER Input Indicates an error has occurred during reception of data in RMII

mode.

ET_CRS Input Carrier detection/data reception enable pin.

ET_RX_DV Input Indicates that there are valid receive data on ET_ERXD3 to

ET_ERXD0.

ET_EXOUT Output General-purpose external output pin.

ET_LINKSTA Input Inputs link status from the PHY-LSI.

ET_ETXD0 to ET_ETXD3 Output 4 bits of MII transmit data.

ET_ERXD0 to ET_ERXD3 Input 4 bits of MII receive data.

ET_TX_EN Output Transmit enable pin. Indicates that transmit data is ready on

ET_ETXD3 to ET_ETXD0.

ET_TX_ER Output Transmit error pin. Notifies the PHY_LSI of an error during

transmission.

ET_RX_ER Input Receive error pin. Recognizes an error during reception.

ET_TX_CLK Input Transmit clock pin. This pin inputs reference signals for output

timings from ET_TX_EN, ET_ETXD3 to ET_ETXD0, and

ET_TX_ER.

ET_RX_CLK Input Receive clock pin. This pin inputs reference signals for input

timings to ET_RX_DV, ET_ERXD3 to ET_ERXD0, and

ET_RX_ER.

Table 1.4 Pin Functi ons (4/6)

Classifications Pin Name I/O Description

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RX63N Group, RX631 Group 1. Overview

Ethernet controller ET_COL Input Inputs collision detection signals.

ET_WOL Output Receives Magic packets.

ET_MDC Output Outputs reference clock signals for information transfer via

ET_MDIO.

ET_MDIO I/O Inputs or outputs bidirectional signals for exchange of

management information between the RX63N Group and the

PHY-LSI.

USB 2.0 host/function

module VCC_USB Input Power supply pin.

VSS_USB Input Ground pin.

USB0_DP, USB1_DP I/O Inputs or outputs USB transceiver D+ data.

USB0_DM, USB1_DM I/O Inputs or outputs USB transceiver D- data.

USB0_VBUS, USB1_VBUS Input Input pins for detection of connection and disconnection of the

USB cable.

USB0_EXICEN Output Output pin for control the low power of the OTG chip.

USB0_VBUSEN Output Supply enable pin of VBUS (5 V) for the OTG chip.

USB0_OVRCURA,

USB0_OVRCURB, Input Input pin for detection of external over current.

USB0_ID Input ID input pin of mini-AB connector at the OGT operation.

USB0_DPUPE,

USB1_DPUPE Output Pull-up control pins of the D+ signal at the function operation.

USB0_DPRPD Output Pull-down control pins of the D+ signal at the host operation.

USB0_DRPD Output Pull-down control pins of the D- signal at the host operation.

CAN module CRX0 to CRX2 Input Input pin.

CTX0 to CTX2 Output Output pin.

Serial peripheral

interface RSPCKA, RSPCKB

RSPCKC I/O Clock input/output pin.

MOSIA, MOSIB, MOSIC I/O Inputs or outputs data output from the master.

MISOA, MISOB, MISOC I/O Inputs or outputs data output from the slave.

SSLA0, SSLB0, SSLC0 I/O Input or output pins slave selection

SSLA1 to SSLA3

SSLB1 to SSLB3

SSLC1 to SSLC3

Output Output pins slave selection

IEBus controller IERXD Input Input pin for data reception.

IETXD Output Output pin for data transmission.

Realtime clock RTCOUT Output Output pin for 1-Hz clock.

RTCIC0 to RTCIC2 Input Time capture event input pin

12-bit A/D converter AN000 to AN020 Input Input pins for the analog signals to be processed by the A/D

converter.

ADTRG0# Input Input pins for the external trigger signals that start the A/D

conversion.

10-bit A/D converter AN0 to AN7 Input Input pins for the analog signals to be processed by the A/D

converter.

ANEX0 Output Extended analog output pin

ANEX1 Input Extended analog input pin

ADTRG# Input Input pins for the external trigger signals that start the A/D

conversion.

D/A converter DA0, DA1 Output Output pins for the analog signals to be processed by the D/A

converter.

Analog power supply AVCC0 Input Analog voltage supply pin for the 12-bit A/D converter. Connect

this pin to VCC if the 12-bit A/D converter is not to be used.

AVSS0 Input Analog ground pin for the 12-bit A/D converter. Connect this pin

to VSS if the 12-bit A/D converter is not to be used.

VREFH0 Input Analog reference voltage supply pin for the 12-bit A/D converter .

Connect this pin to VCC if the 12-bit A/D converter is not to be

used.

Table 1.4 Pin Functi ons (5/6)

Classifications Pin Name I/O Description

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RX63N Group, RX631 Group 1. Overview

Analog power supply VREFL0 Input Analog reference ground pin for the 12-bit A/D converter.

Connect this pin to VSS if the 12-bit A/D converter is not to be

used.

VREFH Input Reference voltage input pin for the 10-bit A/D converter and D/A

converter. This is used as the analog power supply for the

respective modules. Connect this pin to VCC if neither the 10-bit

A/D converter nor the D/A converter is in use.

VREFL Input Reference ground pin for the 10-bit A/D converter and D/A

converter. This is used as the analog ground for the respective

modules. Set this pin to the same potential as the VSS pin.

I/O ports P00 to P03, P05, P07 I/O 6-bit input/output pins.

P10 to P17 I/O 8-bit input/output pins.

P20 to P27 I/O 8-bit input/output pins.

P30 to P37 I/O 8-bit input/output pins. (P35 input/output pins)

P40 to P47 I/O 8-bit input/output pins.

P50 to P57 I/O 8-bit input/output pins.

P60 to P67 I/O 8-bit input/output pins.

P70 to P77 I/O 8-bit input/output pins.

P80 to P87 I/O 8-bit input/output pins.

P90 to P97 I/O 8-bit input/output pins.

PA0 to PA7 I/O 8-bit input/output pins.

PB0 to PB7 I/O 8-bit input/output pins.

PC0 to PC7 I/O 8-bit input/output pins.

PD0 to PD7 I/O 8-bit input/output pins.

PE0 to PE7 I/O 8-bit input/output pins.

PF0 to PF5 I/O 6-bit input/output pins.

PG0 to PG7 I/O 8-bit input/output pins.

PJ3, PJ5 I/O 2-bit input/output pins.

Table 1.4 Pin Functi ons (6/6)

Classifications Pin Name I/O Description