ANALOG Low Cost, Complete IC DEVICES 8-Bit A to D Converter FEATURES Complete A/D Converter with Reference and Clock wow eonmON oR cot: Fast Successive Approximation Conversion 25s ee eT ; No Missing Codes Over Temperature ANALOS BS agy 0 to +70C AD570J -55C to +125C AD570S comm Le ae Digital Multiplexing 3 State Outputs 18 Pin Ceramic DIP = Low Cost Monolithic Construction wwouan QPFSET CONTROL fs AUTO BLANK CONTROL TEMPERATURE COMPENSATEO BURIED ZENER REFERENCE AND DAC CONTROL AD570 7 DATA AEABY PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD570 is an 8-bit successive approximation A/D converter 1. The AD570 is a complete 8-bit A/D converter. No consisting of a DAC, voltage reference, clock, comparator, suc- external components are required to perform a con- cessive approximation register and output buffers all fabri- version. Full scale calibration accuracy of +0.8% (2LSB cated on a single chip. No external components are required of 8 bits) is achieved without external trims. to perform a full accuracy 8-bit conversion in 25us. 2. The AD570 is a single chip device employing the most The AD570 incorporates the most advanced integrated cir- advanced IC processing techniques. Thus, the user has at cuit design and processing technology available today. I? L his disposal a truly precision component with the relia- (integrated injection logic) processing in the fabrication of the bility. and low cost inherent in monolithic construction. SAR function along with laser trimming of the high stability 3. The AD570 accepts either unipolar (0 to +10V) or SiCr thin film resistor ladder network at the wafer stage (LWT) bipolar (-5V to +5V) analog inputs by simply grounding and a ternperature compensated, subsurface Zener reference . . or opening a single pin. insures full 8-bit accuracy at low cost. 4. The device offers true 8-bit accuracy and exhibits no Operating on supplies of +5V and -15V, the AD570 will ac- missing codes over its entire operating temperature cept analog inputs of 0 to +10V unipolar or +5V bipolar, externally selectable. As the BLANK and CONVERT input is range: a driven low, the three state outputs will be open and a conver- 5. Operation Is guaranteed with -15V and +5V supplies. The sion will commence. Upon completion of the conversion, the device will also operate with a ~12V supply. DATA READY line will go low and the data will appear at the 6. The AD570S is also available with full processing to output. Pulling the BLANK and CONVERT input high blanks MIL-STD-883B, Class B. The single chip construction the outputs and readies the device for the next conversion. and functional completeness make the AD570 especially The AD570 executes a true 8-bit conversion with no missing attractive for high reliability applications. des i ci 25us. . . Par codes in approximately 254s 7. Every AD570 is subjected to long-term stabilization The AD570 is available in two versions; the AD570] is spec- bakes, given a powered burn-in at +125C, and tempera- ified for the 0 to 70 C temperature range, the AD570S for ture cycled ten times from -65C to +150C prior to -55C to +125C. Both guarantee full 8-bit accuracy and no final test to insure reliability and long-term stability. missing codes over their respective temperature ranges and In addition, all units are tested 100% at the extremes of are packaged in 18-pin hermetically-sealed ceramic DIPs. their respective temperature ranges for all parameters to guarantee full performance. *Covered by Patent No. 3,940,760, other patents pending. A/D CONVERTERS 1998SSPECIFICATIONS (typical @ +25C with V+ = +5V, V- = -15V, all voltages measured with respect to digital common, unless otherwise indicated) MODEL AD570JD AD570SD/AD570SD-883B? RESOLUTION? RELATIVE ACCURACY @ 25C2.3.4 Tmin tO Tmax FULL SCALE CALIBRATION? > (With 15Q Resistor In Series With Analog Input 8 Bits +1/2LSB max +1/2LSB max +2LSB (typ) * * * UNIPOLAR OFFSET (max)* +1/2LSB * BIPOLAR OFFSET (max)* +1/2LSB * DIFFERENTIAL NONLINEARITY (Resolution for Which no Missing Codes are Guaranteed) +25C 8 Bits * Tmin to Tmax 8 Bits * TEMPERATURE RANGE 0 to +70C -55C to +125C TEMPERATURE COEFFICIENTS* Guaranteed max Change Tmin tO Tmax Unipolar Offset Bipolar Offset Full Scale Calibration (With 15Q Fixed Resistor or 200Q Trimmer) POWER SUPPLY REJECTION* Max Change In Full Scale Calibration TTL Positive Supply +1LSB (88ppm/C) +1LSB (88ppm/C) +2LSB (176ppm/C) +1LSB (40ppm/C) +1LSB (40ppm/*C) +2LSB (80ppm/C) +4.5VRVt545.5V +2LSB max * Negative Supply ~16.5V<V-<-13.5V +2LSB max * ANALOG INPUT RESISTANCE 3kQ min * 5kQ) typ 7kQ max * ANALOG INPUT RANGES (Analog Input to Analog Common) Unipolar 0 to +10V * Bipolar -5V to +5V * OUTPUT CODING Unipolar Bipolar Positive True Binary Positive True Offset Binary LOGIC OUTPUT Bit Outputs and Data Ready Output Sink Current (our = 0.4V max, Trin to Tmax) Output Source Current (Bit Outputs) 3.2mA min (2TTL Loads) (Vout = 2.4V min, Tin tO Tmax) 0.5mA min * Output Leakage When Blanked +40uA max * LOGIC INPUT Blank and Convert Input OS<Vin SV+ +40uA max * Blank Logic 1 2.0V min * Convert Logic 0 0.8V max * CONVERSION TIME 15ps min * 25s typ * 40s max * 200S A/D CONVERTERSMODEL AD570JD AD570SD/AD570SD-883B* POWER SUPPLY Absolute Maximum V+ +7V * V- -16.5V * Specified Operating Rated Performance V+ +5V * V- -15V * Operating Range V+ +4.5V to +5.5V * V- -12.0V to -16.5V * Operating Current Blank Mode V+=+5V 2mA typ (10mA max) * V~ = -15V 9mA typ (15mA max) * Convert Mode V+=+5V 5mA . V~ = -15V 10mA Specifications sarne as AD570J Specifications subject to change without notice. NOTES: ' The AD570S is available fully processed and screened to the requirements of MIL-STD-88 3B, Class B. A complete list of tests is given on page 204S. When ordering, specify the AD570SD/883B. ? The AD570 is a selected version of the AD571 10-bit A to D converter. As such, some devices may exhibit 9 or 10 bits of relative accuracy or resolution, but that is neither tested nor guaranteed. Only TTL logic inputs should be connected to pins 1 and 18 (or no connection made) or damage may result. Relative accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the zero to the full scale of the device. * Specifications given in LSBs refer to the weight of a least significant bie at the 8-bit level, which is 0.39% of full-scale. 5 Full scale calibration is guaranteed trimmable to zero with an external 200 potentiometer in place of the 1522 fixed resistor. Full scale is defined as 10 volts minus 1 LSB, or 9.961 volts. Full Scale Calibration Temperature Coefficient includes effects of unipolar offset drift as well as gain drift. 7 The Data output lines have active pull-ups to source 0.5mA. The DATA READY line is open collector with a nominal 6kQ internal pull-up resistor. ABSOLUTE MAXIMUM RATINGS V+ to Digital Common V- to Digital Common Analog Common to Digital Common Analog Input to Analog Common Control Inputs Digital Outputs (Blank Mode) Power Dissipation OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.9 +0.01 (22.86 +0.25}+e-} 0.032 R (0.81) oe 0.472 (1.99) 0.288 0.31 an +0.01 ile, oN PIN #1 IDENTIFIER <r Jab i 0.185 (4.7) 0.035 (0.89) 0.032 |. (0.81) 0.018 0.1 0,005 0.054 (0.46) (2.54 0.13) (1.37) 0.8 +0.008 (20.32 +0.2) Figure 7. 0.085 (2.06) 0.01 0.002 +| - (0.25 40.05) 0.3 REF (7.62) a 0.095 (2.41) 18-Lead Ceramic Dual-In-Line Package A/D CONVERTERS 201SCIRCUIT DESCRIPTION The AD570 is a complete 8-bit A/D converter which requires no external components to provide the complete successive- approximation analog-to-digital conversion function. A block diagram of the AD570 is shown in Figure 2. Upon receipt of the CONVERT command, the internal 8-bit current out- put DAC is sequenced by the I? L successive-approximation register (SAR) from its most-significant bit (MSB) to least- significant bit (LSB) to provide an output current which accurately balances the input signal current through the 5kQ input resistor. The comparator determines whether the ad- dition of each successively-weighted bit current causes the DAC current sum to be greater or less than the input current; if the sum is less the bit is left on, if more, the bit is turned off. After testing all the bits, the SAR contains a 8-bit binary code which accurately represents the input signal to within +1/2LSB (0.20%). DIGITAL COMMON BLANK & CONVERT CONTROL. 1 ANALOG IN ANALOG COMMON 10 BIT CURRENT 10 BIT OUTPUT SAR ait DAC OUTPUTS ae | ICLOCKy BIPOLAR OFFSET CONTROL 3 STATE BUFFERS AUTO BLANK CONTROL TEMPERATURE COMPENSATED BURIED ZENER REFERENCE AND DAC CONTROL ADS57) 17 DATA READY *SEE NOTE 2. PAGE 3 Figure 2, AD570 Functional Block Diagram Upon completion of the sequence, the SAR sends out a DATA READY signal (active low), which also brings the three-state buffers out of their open state, making the bit output lines become active high or low, depending on the code in the SAR. When the BLANK and CONVERT line is brought high, the output buffers again go open, and the SAR is prepared for another conversion cycle. Details of the timing are given on page 205S. The temperature compensated buried Zener reference provides the primary voltage reference to the DAC and guarantees excellent stability with both time and tempera- ture. The bipolar offset input controls a switch which allows the positive bipolar offset current (exactly equal to the value of 2028 A/D CONVERTERS Br 2 BIT 3 BIT 4 BIT 5 arr 6 Bit 7 Bir 8 ital oa : : it a O DIGITAL COMMON BIPOLAR O OFFSET CONTROL O O ANALOG COMMON | ANALOG IN \ 9.151 THE ADS70 iS ALSO AVAILABLE IN A LASER-TRIMMED PASSIVATED CHIP FORM, CONSULT FACTORY FOR PRICING AND APPLICATION PARTICULARS. FIGURE 3 SHOWS THE CHIP METALLIZATION LAY OUT AND BONDING PADS. Figure 3. Chip Bonding Diagram the MSB less 4%LSB) to be injected into the summing (+) node of the comparator to offset the DAC output. Thus the nominal 0 to +10V unipolar input range becomes a~5V to +5V range. The 5kQ thin film input resistor is trimmed so that with a full scale input signal, an input current will be generated which exactly matches the DAC output with all bits on. (The input resistor is trimmed slightly low to facilitate user trimming, as discussed on the next page.) POWER SUPPLY SELECTION The AD570 is designed and specified for optimum performance using a +5V and -15V supply. The supply current drawn by the device is a function of the operating mode (BLANK or CONVERT), as given on the specification page. The supply currents change only moderately over temperature as shown in Figure 4, and do not change significantly with changes in V~ from -10.8 volts to -16 volts. C => CONVERT MODE B => BLANK MODE 414.0 10.0 -15V,C 9.0 1-15V,8 8.0 SUPPLY 7.0 CURRENTS mA 6.0 5.0 1 +5v.6 40 2.0 15 1+5V,B -50 -25 Qo 2 50 70 100 128 TEMPERATURE C Figure 4. AD570 Power Supply Current vs. TemperatureCONNECTING THE AD570 FOR STANDARD OPERATION The AD570 contains all the active componer.ts required to perform a complete A/D conversion. Thus, for most situa- tions, all that is necessary is connection of the power sup- ply (+5 and -15), the analog input, and the conversion start pulse. But, there are some features and special con- nections which should be considered for achieving optimum performance. The functional pin-out is shown in Figure 5. y ee oe BIT8| 2 17 |DATA READY 16 | DIGITAL COM AD5S70 [1s |erouas OFF BIT? BITE BITS o 14] ANALOG COM 13 | ANALOG IN BIT3) 7 12) Vv" BIT 4 BIt2f 8 111 SLK & CONV. MSB BIT 1] 9 10} vt *SEE NOTE 2, PAGE 3 Figure 5. AD70 Pin Connections FULL SCALE CALIBRATION The 5kQQ thin film input resistor is laser trimmed to produce a current which matches the full scale current of the internal DAC-plus about 0.3%when a full scale analog input voltage of 9.961 volts (10 volts 1LSB) is applied at the input. The input resistor is trimmed in this way so that if a fine trimming potentiometer is inserted in series with the input signal, the input current at the full scale input voltage can be trimmed down to match the DAC full scale current as precisely as desired. However, for many applications the nominal 9.961 volt full scale can be achieved to sufficient accuracy by simply inserting a 15Q resistor in series with the analog input to pin 13. Typical full scale calibration error will then be about +2LSB or 40.8%. If a more precise calibration is desired, a 200Q trimmer should be used instead. Set the analog input at 9.961 volts, and set the trimmer so that the output code is just at the transition between 11111110 and 11111111. Each LSB will then have a weight of 39.06mV. If a nominal full scale of 10.24 volts is desired (which makes the LSB have weight of exactly 40.00mV), a 502 resistor in series with a 20022 trimmer (or a 50022 trimmer with gocd resolution) should be used. Of course, larger full scale ranges can be ar- ranged by using a larger input resistor, but linearity and full scale temperature coefficient may be compromised if the external resistor becomes a sizeable percentage of 5kQ. GLELELELELELELELE! ase . a ipo - L BITB 2 tse [2 lo DR sit7/3]} ADS70 is }-o DIGITAL CoM Bite | 4 lis BIPOLAR (SHORT TO COMMON FOR \ CONTROLS UNIPOLAR OPEN FOR BIPOLAR BITS | 5 apo ANALOG COMMON ( TOLERATES 200mv TO DIGITAL COMMON BIT4) 6 a} ANALOG IN Pun 7 - 1522 FIXED OR prs ca bo 18 2002 VARIABLE RESISTOR (SEE TEXT) BIT2 [e. 1 fo BaC BIT 1 5 MSB Le fo}-o . "SEE NOTE 2,P/.GE 3 Figure 6. Standard AD570 Connections BIPOLAR OPERATION The standard unipolar 0 to +10V range is obtained by shorting the bipolar offset control pin to digital common. If the pin is left open, the bipolar offset current will be switched into the comparator summing node, giving a-5V to +5V range with an offset binary output code. (-5.00 volts in will give a 8-bit code of 00000000; an input of 0.00 volts results in an out- put code of 10000000 and 4.96 volts at the input yields the 11111111 code.) The bipolar offset control input is not di- rectly TTL compatible, but a TTL interface for logic control can be constructed as shown in Figure 7. +7 Aw OAL __2 ss Acom ADS70 BIPOLAR o \, | | OFFSET *8VCOM | | CONTROL | DATA | 8BITS l Dcom $ 30ki2 1sv COM -1 COM Figure 7. Bioolar Offset Controlled by Logic Gate Gate Output = 1 Unipolar 0 - 10V Input Range Gate Output = 0 Bipolar t5V Input Range COMMON MODE RANGE The AD570 provides separate Analog and Digital Common connections. The circuit will operate properly with as much as 200mV of common mode range between the two | commons. This permits more flexible control of system common bussing and digital and analog returns. In norma! operation the Analog Common terminal may gener- ate transient currents of up to 2mA during a conversion. In addition, a static current of about 2mA will flow into Analog Common in the unipolar mode after a conversion is complete. An additional 1mA will flow in during a blank interval with zero analog input. The Analog Common current will be modu- lated by the variations in input signal. The absolute maximum differential voltage rating between the two commons is +1 volt. We recommend the connection of a parallel pair of back-to-back protection diodes as shown in Figure 8 between the commons if they are not connected locally. = Ay % AcOoM 10 (2) 1NQ14 OR CARD yy EQUIVALENT AD570 CONNECTOR vt com Dcom v- COM Figure 8. Differential Common Voltage Protection A/B CONVERTERS 2038SZERO OFFSET The apparent zero point of the AD570 can be adjusted by inserting an offset voltage between the Analog Common of the device and the actual signal return or signal common. Figure 9 illustrates two methods of providing this offset. Figure 9A shows how the converter zero may be offset by up to +3 bits to correct the device initial offset and/or input signal offsets. As shown, the circuit gives approximately symmetrical ad- justment in unipolar mode. In bipolar mode R2 should be omitted to obtain a symmetrical range. Aw INPUT SIGNAL A4D570 Acom R, Re 392 $7.5k SIGNAL COMMON +15V -15V ZERO OFFSET ADJ +3 BIT RANGE Figure 9. (A) AIn AD570 Acom SIGNAL COMMON % BIT ZERO OFFSET Figure 9. (B) Figure 10 shows the nominal transfer curve near zero for an AD570 in unipolar mode. The code transitions are at the edges of the nominal bit weights. In some applications it will be pre- ferable to offset the code transitions so that they fall between the nominal bit weights, as shown in the offset characteristics. This offset can easily be accomplished as shown in Figure 9B. At balance (after a conversion) approximately 2mA flows into the Analog Common terminal. A 1022 resistor in series with this terminal will result in approximately the desired % bit off- set of the transfer characteristics. The nominal 2mA Analog Common current is not closely controlled in manufacture. If high accuracy is required, a 202 potentiometer (connected as a rheostat) can be used as R2. Additional negative offset range may be obtained by using larger values of R2. Of course, if the zero transition point is changed, the full scale transition point will also move. Thus, if an offset of LSB is introduced, full scale trimming as described on previous page should be done with an analog input of 9.941 voits. NOTE: During a conversion transient currents from the Analog Common terminal will disturb the offset voltage. Capacitive decoupling should not be used around the offset network. These transients will settle as appropriate during a conversion. Capacitive decoupling will pump up and fail to settle re- sulting in conversion errors. Power supply decoupling which returns to analog signal common should go to the signal input side of the resistive offset network. 2045 A/D CONVERTERS OUTPUT ro CODE \ 00000100 TT 00000011 00000010 00000001 00000000 OV 40mV 120mV 200mvV INPUT VOLTAGE NOMINAL CHARACTERISTICS REFERRED TO ANALOG COMMON CODE 00000100 00000011 Jo 00000010 OUTPUT co77 q ql 00000001 00000000 f--_- OV 40mV 120mV 200mvV INPUT VOLTAGE OFFSET CHARACTERISTICS WITH 1022 IN SERIES WITH ANALOG COMMON Figure 10. AD570 Transfer Curve - Unipolar Operation (Approximate Bit Weights Shown for IHustration, Nominal Bit Weights ~ 36.1mV) MIL-STD-883 The rigors of the military/aerospace environment, temperature extremes, humidity, mechanical stress, etc., demand the utmost in electronic circuits. The AD570, with the inherent reliability of integrated circuit construction, was designed with these applications in mind. The hermetically-sealed, low profile DIP package takes up a fraction of the space required by equivalent modular designs and protects the chip from hazardous environ- ments. To further insure reliability, the AD570 is offered with 100% screening to MIL-STD-883B, method 5004. Table I details the test procedures of MIL-STD-883. Analog Devices subjects each part ordered with 883B screening to these tests on a 100% basis. TABLE I TEST METHOD 1) Internal Visual 2010, Test Condition B (Pre cap) 2) Stabilization Bake Method 1008, 24 hours @ +150C 3) Temperature Cycling Method 1010, Test Condition C, 10 Cycles, -65C to +150C 4) Constant Acceleration Method 2001, Test Condition E, Y1 plane, 30kg 5) Seal, Fine and Gross Method 1014, Test Condition B and C 6) Burn-in Test Method 1015, Test Condition B, 160 hours @ +125C min 7) Final Electrical Tests Performed 100% to all min and max specifications on data pages. 8) External Visual Method 2009CONTROL AND TIMING OF THE AD570 There are several important timing and control features on the AD570 which must be understood precisely to aliow optimal interfacing to microprocessor or other types of con- trol systems. All of these features are shown in the timing diagram in Figure 11. The normal stand-by situation is shown at the left end of the drawing. The BLANK and CONVERT (B & C) line is held high, the output lines will be open, and the DATA READY (DR) line will be high. This mode is the lowest power state of the device (typically 150mW). When the (B & C) line is brought low, the conversion cycle is initiated; but the DR and Data lines do not change state. When the conversion cycle is complete (typically 25us), the DR line goes low, and within 500ns, the Data lines become active with the new data. About 1.5ys after the B & C line is again brought high, the DR line will go high and the Data lines will go open. When the B & C line is again brought low, a new conversion will begin. The minimum pulse width for the B & C line to blank previous data and start a new conversion is 2us. If the B & C line is brought high during a conversion, the conversion will stop, and the DR and Data lines will not change. If a 2us or longer pulse is applied to the B & C line during a conversion, the converter will clear and start a new conversion cycle. PULSE BLANKS DATA OUTPUTS OM RISING EDGE BLANKS DATA OUTPUTS. AND STARTS CONVERSION ON FALLING EDGE . HOLDS DATA QUTPUTS = START B&G 2us min Ree CONVERSION \ | | CONVERSION 4 4 CONVERSION TIME START STOP START ME 25us CONVERSION NEW be 25us | CONVERSION _ . ben 500ns _-| L INDICATES (max) DATA READY VKAKX a YyYvVY DATA , BLANK one BLANK ome BLANK OUT , (OPEN) ZERO (OPEN) 2EG0 (OPEN) AXRKY A _. AANAA Figure 11. AD570 Timing and Control Sequence NEW DATA READY CONTROL MODES WITH BLANK AND CONVERT The timing sequence of the AD570 discussed above allows the device to be easily operated in a variety of systems with differ- ing control modes. The two most common control modes, the Convert Pulse Mode, and the Multiplex Mode, are illustrated here. Convert Pulse Mode In this mode, data is present at the out- put of the converter at all tires except when conversion is taking place. Figure 12 illustrates the timing of this mode. The BLANK and CONVERT line is normally low and conversions are triggered by a positive pulse. A typical application for this timing mode is shown in Figure 15, in which p:P bus interfacing is easily accomplished with three-state buffers. Multiplex Mode In this mode the outputs are blanked except when the device is selected for conversion and readout; this timing shown in Figure 13. A typical AD570 multiplexing ap- plication is shown in Figure 16. This operating mode allows multiple AD570 devices to drive common data lines. All BLANK and CONVERT lines are held high to keep the outputs blanked. A single AD570 is selected, its BLANK and CONVERT line is driven low and at the end of conversion, which is indicated by DATA READY going low, the conversion result will be present at the outputs. When this data has been read from the 8-bit bus, BLANK and CONVERT is restored to the blank mode to clear the data bus for other _ converters. When several AD570s are multiplexed in sequence, a new conversion may be started in one AD570 while data is being read from another. As long as the data is read and the first AD570 is cleared within 15ys after the start of conversion of the second AD570, no data overlap will occur. CONVERT PULSE bac | eo CONVERT A INTERVAL a J Lo BLANK (OPEN) PREVIOUS NEW OUTPUTS DATA DATA Figure 12. Convert Pulse Mode CONVERSION Bac | uae STARTS [ CONVERSION ENDS pa ao END DATA READOUT READ OUT DATA x OUTPUTS Oy BLANK (OPEN) A ante HY BLANK (OPEN Figure 13. Multiplex Mode SAMPLE-HOLD AMPLIFIER CONNECTION TO THE AD570 Many situations in high-speed acquisition systems or digitizing of rapidly changing signals require a sample-hold amplifier (SHA) in front of the A-D converter. The SHA can acquire and hold a signal faster than the converter can perform a conver- sion. A SHA can also be used to accurately define the exact point in time at which the signal is sampled. For the AD570, a SHA can also serve as a high input impedance buffer. Figure 14 shows the AD570 connected to the AD582 monoli- thic SHA for high speed signal acquisition. In this configuration, the AD582 will acquire a 10 volt signal in less than 10ys with a droop rate less than 1004V/ms. The control signals are arranged so that when the control line goes low, the AD582 is put into the hold mode, and the AD570 will begin its conversion cycle. (The AD582 settles to final value well in advance of the +15V +5V -_ o CONTROL IN oO Bac AIN DATA READY NC 14] n3, 2st jog 5 VOLT com ADS82 AD570 > e 300pF + y 2. af fa Si e667 Nc UY NC DATA | 8BITS NULL ANALOG IN Tey oO L J ACOM ( T -15V +15 VOLT COM Figure 14, Sample-Hold Interface to the AD570 A/D CONVERTERS 2065Sfirst comparator decision inside the AD570). The DATA READY line is fed back to the other side of the differential input control gate so that the AD582 cannot come out of the hold mode during the conversion cycle. At the end of the conversion cycle, the DATA READY line gees low, auto- matically placing the AD582 back into the sample mode. This feature allows simple control of both the SHA and the A-D converter with a single line. Observe carefully the ground, sup- ply, and bypass capacitor connections between the two de- vices. This will minimize ground noise and interference during the conversion cycle to give the most accurate measurements. INTERFACING THE AD570 TO A MICROPROCESSOR The AD570 can easily be arranged to be driven from standard microprocessor control lines and to present data to any standard microprocessor bus (4-, 8-, 12-or 16-bit) with a mini- mum of additional control components. The configuration shown in Figure 15 is designed to operate with an 8-bit bus and standard 8080 control signals. The input control circuitry shown is required to insure that the AD570 receives a sufficiently long B & C input pulse. When the converter is ready to start a new conversion, the B & C line is low, and DR is low. To command a conversion, the start address decode line goes low, followed by WR. The B & C line will now go high, followed about 1.5us later by DR. This resets the external flip-flop and brings B & C back to low, which initiates the conversion cycle. At the end of the conversion cycle, the DR line goes low, the data outputs will become active with the new data and the control lines will return to the stand-by state. The new data will remain active until a new conversion is commanded. The self-pulsing nature of this circuit guarantees a sufficient convert pulse width. This new data can now be presented to the clata bus by en- abling the three-state buffers when desired. An 8-bit data word is loaded onto the bus when its decoded address goes low and the RD line goes low. Polling the converter to deter- mine if conversion is complete can be done by addressing the ANALOG IN 097 uP DATA BUS ANALOG COM START ADDRESS FROM DECODER FROM ss WR z ? HI BYTE ADDRESS FROM DECODER LO BYTE ADDRESS FROM DECODER me FROM SYS RD Figure 15. Interfacing AD570 to an 8-Bit Bus (8080 Control Structure) 206S A/D CONVERTERS gate (shown dotted) which buffers the DR line, if desired. In this configuration, there is no need for additional buffer reg- ister storage. The data is stored indefinitely in the AD570, since the B & C line is continually held low. BUS INTERFACING WITH A PERIPHERAL INTERFACE CIRCUIT An improved technique for interfacing to a uP bus involves the use of special peripheral interfacing circuits (or I/O devices), such as the MC6820 Peripheral Interface Adapter (PIA). Shown in Figure 16 is a straightforward application of a PIA to multiplex up to 10 AD570 circuits. The AD570 has 3-state outputs, hence the data bit outputs can be paralleled, provided that only one converter at a time is permitted to be the active state. The DATA READY output of the AD570 is an open collector with resistor pull-up, thus several DR lines can be wire-ORed to allow indication of the status of the selected device. One of the 8-bit ports of the PIA is programmed as an 8-bit input port. The 8-bits of the second port are program- med as outputs, and along with the 2 control bits (which act as outputs), are used to control the 10 AD570s. When a con- trol line is in the 1 or high state, the ADC will be automat- ically blanked. That is, its outputs will be in the inactive open state. If a single control line is switched low, its ADC will convert and the outputs will automatically go active when the conversion is complete. The result can then be read from port A. When the next conversion is desired, a different con- trol line can be switched to zero, blanking the previouslyactive port at the same time. Subsequently, this second device can be read by the microprocessor, and so-forth. The status lines are wire-ORed in 2 groups and connected to the two remaining control pins. This allows a conversion status check to be made after a convert command, if necessary. The ADCs are divided into two groups to minimize the loading effect of the internal pull-up resistors on the DATA READY buffers. See the MC6820 data sheet for more application detail. ANALOG _ IN BR Taps! | 4 LSB Bae [ STATUS GROUP 1 ~| OR L TROA = MSB s7o:} LL JL OS ADS70 : i PORTA : i S14 | O86 De7 | _ sb MC6820 g B Bac PERIPHERAL Rso 243] {2 TC INTERFACE RS1 24 g a ADAPTER ese zm > {Pta} cst rr4a! je a | DR CS 54g _ mse | PORTS AW AD570 = i, ENABLE : ome : RES ist | Bac l {TO TWO MORE IN GROUP 1) aT ti a {TO FOUR MORE IN GROUP 2) / STATUS GROUP 2 m oA MSB AD570: 7 LJ ie Bao C Figure 16. Multiplexing 10 AD570s Using Single PIA for pP Interface. No Other Logic Required (6800 Control Structure).