Document No. 70-0196-04 │www.psemi.com
Contact sales@psemi.com for full version of datasheet Page 1 of 4
©2005-2006 Peregrine Semiconductor Corp. All rights reserved.
RX1 RX2
RX3
TRX2 (WCDMA, RX)
TX1 (GSM/PCS)
TX2 (GSM/PCS)
CMOS
Control/Driver
and ESD
V1 V2 V3
TRX1 (WCDMA, RX)
The PE42671 is a HaRP™-enhanced SP7T
RF Switch develop ed on the UltraCMOS™
process technology. It addresses the specific
design needs of the Quad-Band GSM Handset
Antenna Switch Module Market for use in
GSM/PCS/EDGE/WC DM A ha nd sets. Th e
switch is comprised of two transmit ports that
can be used for GSM/PCS/EDGE, two
transmit/receive ports (TRX1 and TRX2) that
can be used for either WCDMA or as receive
ports, and three symmetric receive ports. On-
chip CMOS decode log ic facilitates three-p in
low vo ltage CMOS con trol, while high ESD
tolerance of 10 00 V at all po rts, no bloc king
cap aci tor req ui r em e nts, an d on- chip SAW filter
over-voltage protection devices make this the
u l tim ate in integ r ation and ruggedness.
Peregrine’s HaRP™ technology
enhancements de liver high linearity and
exceptional harmonics performance. It is an
innovative feature of the UltraCMOS™
proc es s , pr ov i ding perf or m a nc e superior to
GaAs with th e ec o nom y and in te gr ation of
conventional CMOS.
Product Brief
SP7T UltraCMOS™ 2.75 V Switch
100 – 3000 MH z, + 68 dBm IIP 3
Product Description
Figure 1. Functional Diagram
PE42671 DIE
Features
• 2 TX, 2 TRX, 3 RX ports
• Three pin CMOS logic control with
integral decoder/driver
• Exce pti o nal har m o ni c per f or m ance:
2fo = -83 dBc and 3fo = - 77.5 dBc
• Low TX inse rtion loss: 0.65 dB at
900 MH z, 0.75 dB at 190 0 MHz
• TX – RX Isolation of 46 dB at 900 MHz,
38 dB at 1900 MHz
• 1000 V HBM ESD tol er ance all por ts
• +68 dBm IIP3 @ 50 Ω
• -111 dBm IMD3
• No blocking capacitors required
* Dimensions shown are drawn die size.
Figure 2. Die Top View *
1156 µm
1576 µm
GND V
DD
GND V1
GND
TX2
GND
TRX1
TX1
GND
V3
ANT RX1 GND
RX2
GND
RX3
GND
GND
TRX2
GND
ANT
GND V2
Product Brief
PE42671
Page 2 of 4
©2005-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0196-04 │ UltraCMOS™ RFIC Solutions
Contact sales@psemi.com for full version of datasheet
Table 1. Target Electrical Specifications @ 25 °C, VDD = 2.75 V
Table 2. Opera ti ng Ranges Table 3. Absolute Max imum Rati ngs
Part perfor m ance is not guar anteed under t hes e
conditi ons . Exposur e to absolut e maximum conditions
for extended periods of time may adversely aff ect
reliability. Stress es in exces s of absolute maxim um
rati ngs m ay c aus e per m anent damage.
Note: 2. Assumes RF input period of 4620 µs and duty cycle of 50%. Note : 3. Ass um es RF in p ut perio d of 46 20 µs and duty cycle of 50%.
4. VDD within operating range specified in Table 2.
Table 1. Target Electrical Specifications @ 25 °C, VDD = 2.75 V
Note: 1. Insertion loss specified with optimal impedance matching.
Parameter Symbol Min Typ Max Units
Temperature ra nge TOP -40 +85 °C
VDD Supply V ol t age VDD 2.65 2.75 2.85 V
IDD Power Supply Current
(VDD = 2. 75 V ) IDD 13 50 µA
TX i nput power2 (VSWR ≤ 3:1)
824-915 MHz +35
dBm
+33
RX input po wer2
(VSWR =1:1) PIN +20 dBm
Control V ol tage Hi gh VIH 1.4 V
Control V ol tage L ow VIL 0.4 V
PIN
TX i nput power2 (VSWR ≤ 3:1)
1710-1910 MHz
TRX i nput po wer (V S WR ≤ 3: 1)
824 - 2170 MHz +31
Symbol Parameter/Conditions Min Max Units
VDD Power suppl y vo l t age -0.3 4.0 V
VI Voltage on any DC i nput -0.3 VDD+ 0. 3 V
TST Storage temperature ran ge -65 +150 °C
PIN (50 Ω)
TX i nput power (50 Ω) 3,4
824-915 MHz +38
dBm
TX i nput power (50 Ω) 3,4
1710-1910 MHz +36
RX input po wer (50 Ω) 3,4 +23
PIN (∞:1)
TX i nput power (VSWR = (∞:1)3,4
824-915 MHz +35
dBm
TX i nput power (VSWR = (∞:1)3,4
1710-1910 MHz +33
VESD ES D V ol tage ( HB M , M IL_STD 883
Method 3015. 7) 1000 V
TRX i nput po wer (VSWR = (∞:1)
824 - 2170 MHz +31
TRX i nput po wer (5 0 Ω)
824 - 2170 MHz +34
Parameter Condition Typ Units
Insertion loss1
TX - ANT (850 / 900)
TX - ANT (180 0 / 1900 )
TRX - ANT ( 850 WCDMA )
TRX - ANT ( 2100 WCDMA )
RX - A NT (850 / 900)
RX - A NT (1800 / 1900)
0.65
0.75
0.6
0.75
0.95
1.0
dB
dB
dB
dB
dB
dB
Return Loss Port under t est in on state (850 / 900)
(1800 / 1900 / 21 00) 20
15 dB
dB
Isolation
TX - RX (850 / 900)
TX - RX (180 0 / 1900)
TX - T X (850 / 900)
TX - T X (1800 / 1900)
TX - T RX (850 / 900 )
TX - T RX (1800 / 1900)
TRX - RX ( 85 0 WCDMA )
TRX - RX (2 100 WC DM A)
46
38
33
26
36
29
39
31
dB
dB
dB
dB
dB
dB
dB
dB
2nd Harmoni c TX 850 / 900 MHz , +35 dBm output power, 50 Ω
TX 1800 / 1900 M Hz, +33 dB m outp ut power, 50 Ω -83
-82 dBc
dBc
3rd Harmoni c TX 850 / 900 MHz , +35 dBm output power, 50 Ω
TX 1800 / 1900 M Hz, +33 dB m outp ut power, 50 Ω -77.5
-78 dBc
dBc
WCDM A 210 0 IMD3 TRX1 / T RX 2: Meas ured at 2.14 G Hz at ANT port, input +2 0 dB m CW
si gnal at 1.95 GHz and -1 5 dBm CW s i gnal at 1.76 GHz -111 dBm
WCDM A 210 0 I IP3 TRX1 / T RX 2: Measured at 2. 14 GHz at ANT port , input +20 dBm CW
si gnal at 1.95 GHz and -1 5 dBm CW s i gnal at 1.76 GHz +68 dBm
Product Brief
PE42671
Page 3 of 4
Document No. 70-0196-04 │www.psemi.com ©2005-2006 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latc h-Up Avoidance
Unlike conv entio nal CMOS devices, UltraCMO S™
devices are immune to latch-up.
Table 5. Truth Table
Table 6. Ordering Information
Table 4. Pin Descriptions Figure 3. Pad Configuration (Top View)
TX1
PE42671
Die
ANT
TX2
RX1 RX2
V
DD
V3
V2
V1
GND
GND
6
GND
GND
RX3
GND
GND
TRX2
GND
1
2
4
5
9
10 11 12 13 14 15 16
17
18
19
20
3
7
GND
8
GND
GND
21
24
22
23
TRX1
ANT
GND
Notes: 5. Bond wires should be physically short and connected to
gro un d pl ane for bes t per form anc e.
6. Blocking capacitors needed only when non-zero DC
voltage present.
Pin No. Pin Name Description
1 ANT RF Common – Antenna
Redund ant ANT pins for flexible bonding
2 RX16 RF I/O – RX1
3 GND5 Ground
4 TRX16 RF I/O – TRX1
5 GND5 Ground
6 ANT RF Common – Antenna
Redund ant ANT pins for flexible bonding
7 GND5 Ground
8 TX16 RF I/O - TX1
9 GND5 Ground
10 GND5 Ground
11 VDD Supply
12 V1 Switch control input, CMOS logic level
13 GND5 Ground
14 V2 Switch control input, CMOS logic level
15 V3 Switch control input, CMOS logic level
16 GND5 Ground
17 GND5 Ground
18 TX26 RF I/O – TX2
19 GND5 Ground
20 TRX26 RF I/O – TRX2
21 GND5 Ground
22 RX36 RF I/O – RX3
23 GND5 Ground
24 RX26 RF I/O – RX2
Order Code Description Package Shippin g Met hod
42671-90 PE42671-DIE-D Film Fra me Wafer (Gross Die / Wafer Quantity)
42671-99 PE42671-DIE-400G Waffle Pack 400 Dice / Waffle Pack
42671-00 PE42671-DIE-1H Evaluation Kit 1/ box
Path V3 V2 V1
TX1 - ANT 0 0 0
TX2 - ANT 0 0 1
TRX1 - ANT 0 1 0
TRX2 - ANT 1 1 0
RX1 - ANT 0 1 1
RX2 - ANT 1 0 0
RX3 - ANT 1 0 1
Product Brief
PE42671
Page 4 of 4
©2005-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0196-04 │ UltraCMOS™ RFIC Solutions
Contact sales@psemi.com for full version of datasheet
Sales Offices
The Americas
Peregrine Semiconductor Corporation
9450 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858- 731-9499
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vent s
F-92380 Garches , France
Tel: +33-1-4741-9173
Fax : +33-1 -4741 -917 3
For a list of represent at ives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet cont ains design target specificat ions f or product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet cont ains preliminary data. Additional data
may be added at a later date. Peregrine r eserves the right
to change specifications at any tim e without notice in order
to supply t he best possible product.
Product Specification
The data sheet contains final data . In the event Peregrine
dec ide s to cha nge the spe c ific a tions, Peregrine will notify
cust omers of the intended changes by issuing a DCN
(Document Change Not ice).
The information in t his data sheet is believed to be reliable.
Howeve r, Peregrine assume s no liabilit y for the use of this
information. Use shall be entir ely at the user’s own risk.
No patent rights or licenses to any circuits descr ibed in this
data sheet are im plied or granted to any third part y.
Peregrine’s pr oducts are not designed or int ended for use in
devices or systems int ended for surgical implant, or in other
applications intended t o support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situat ion in which personal injury or death m ight occur.
Peregr ine assumes no liability for damages, inc luding
consequential or incidental dam ages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered tr ademarks
and UltraCMOS and HaRP are trademarks of Per egrine
Semiconductor Cor p.
Spa ce and Defense Products
Americas :
Tel: 858-731-9453
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Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
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