54LCX16374 Low Voltage 16-Bit D Flip-Flop with 5V Tolerant Inputs and Outputs General Description Features The LCX16374 contains sixteen non-inverting D flip-flops with TRI-STATE (R) outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The LCX16374 is designed for low voltage (3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. n n n n n n n n 5V tolerant inputs and outputs Power down high impedance inputs and outputs Supports live insertion/withdrawal 2.0V-3.6V VCC supply operation 24 mA output drive Implements patented noise/EMI reduction circuitry Functionally compatible with the 54 series 16374 ESD performance: Human body model > 2000V Machine model > 200V n Standard Microcircuit Drawing (SMD) 5962-99535 Ordering Code Order Number 54LCX16374W-QML Package Number WA48A Package Description 48-Lead Ceramic Flatpack Logic Symbol Connection Diagram Pin Assignment for Cerpack DS101199-1 Pin Descriptions Pin Description Names OEn Output Enable Input (Active Low) CPn Clock Pulse Input I0-I15 Inputs O0-O15 Outputs DS101199-2 TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. (c) 2001 National Semiconductor Corporation DS101199 www.national.com 54LCX16374 Low Voltage 16-Bit D Flip-Flop with 5V Tolerant Inputs and Outputs July 1999 54LCX16374 Functional Description The LCX16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs andTRI-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. Inputs CP1 Inputs CP2 Outputs OE1 I0-I7 O0-O7 L H H L L L L L X O0 X H X Z Outputs OE2 I8-I15 O8-O15 L H H L L L L L X O0 X H X Z H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance O0 = Previous O0 before HIGH to LOW of CP Logic Diagrams Byte 1 (0:7) DS101199-3 Byte 2 (8:15) DS101199-4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Recommended Operating Conditions (Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) -0.5V to +7.0V DC Input Voltage (VI) -0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI < GND DC Output Diode Current (IOK) -50mA VO VCC +50mA 2.0V to 3.6V Data Retention 1.5V to 3.6V Input Voltage (VI) 0V to 5.5V High or Low State 0V to VCC TRI-STATE 0V to 5.5V Operating Temperature (TA) DC Output Voltage (VO) (Note 2) Output in High or Low State Operating Output Voltage (VO) -50 mA VO < GND 54LCX16374 Absolute Maximum Ratings (Note 1) -55C to +125C Minimum Input Edge Rate (t/V) VIN from 0.8V to 2.0V, VCC = 3.0V -0.5V to VCC + 0.5V Output in TRI-STATE -0.5V to 7.0V DC Output Source or Sink Current (IO) 50mA 100mA DC VCC or Ground Current Storage Temperature Range (TSTG) 0ns/V to 10ns/V Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: Unused inputs must be held HIGH or LOW. They may not float. -65C to +150C Power Dissapation 750mW Junction Temperature (TJ) 175C DC Electrical Characteristics Symbol Parameter Conditions VCC Min 2.0 VIH HIGH Level Input Voltage 2.7-3.6 VIL LOW Level Input Voltage 2.7-3.6 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage TA = -55C to +125C (V) Units Max V 0.8 V IOH = -100 A 2.7-3.6 VCC - 0.2 V IOH = -12 mA 2.7 2.2 V IOH = -12 mA 3.0 2.4 V IOH = -24 mA 3.0 2.2 V IOL = 100 A 2.7-3.6 0.2 V IOL = 12 mA 2.7 0.4 V IOL = 24 mA 3.0 0.55 V A II Input Leakage Current 0 VI 5.5V 2.7-3.6 IOZ 3-STATE Output Leakage 0 VO 5.5V 2.7-3.6 5.0 5.0 0 10 A A A VI = VIH or VIL IOFF Power-Off Leakage Current ICC Quiescent Supply Current ICC Increase in ICC per Input VI or VO = 5.5V VI = VCC or GND 2.7-3.6 20 3.6V VI, VO 5.5V 2.7-3.6 20 A VIH = VCC -0.6V 2.7-3.6 500 A 3 www.national.com 54LCX16374 AC Electrical Characteristics TA = -55C to +125C, CL = 50pF, RL = 500 Symbol VCC = 3.3V 0.3V Parameter Min Max Units VCC = 2.7V Min Max fMAX Maximum Clock Frequency 200 tPHL Propagation Delay 0.5 6.5 1.0 7.0 tPLH CP to On 0.5 6.5 1.0 7.0 tPZL Output Enable Time 0.5 6.5 1.0 7.0 0.5 6.5 1.0 7.0 tPZH tPLZ Output Disable Time tPHZ 200 MHz 1.0 6.5 1.0 7.0 1.0 6.5 1.0 7.0 ns ns ns tS Setup Time 3.5 3.5 ns tH Hold Time 2.0 2.0 ns tW Pulse Width 4.0 4.0 tOSHL Output to Output Skew (Note 4) tOSLH ns 1.0 1.0 1.0 1.0 ns Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two seperate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics Symbol Parameter Conditions VCC (V) TA = 25C Max Units VOLP Quiet Output Dynamic Peak VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 1.2 V VOLV Quiet Output Dynamic Valley VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 -1.1 V Capacitance Symbol Parameter Conditions Max Units pF CIN Input Capacitance VCC = Open, VI = 0V or VCC 10 COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 12 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 40 pF www.national.com 4 inches (millimeters) unless otherwise noted 48-Lead Ceramic Flatpack Package Number WA48A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. 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