Freescale Semiconductor Advance Information Document Number: MC10XS4200 Rev. 6.0, 12/2013 Dual 24 V, 10 mOhm High Side Switch 10XS4200 The 10XS4200 device is part of a 24 V dual high side switch product family with integrated control, and a high number of protective and diagnostic functions. It has been designed for truck, bus, and industrial applications. The low RDS(ON) channels (<10 m) can control different load types; bulbs, solenoids, or DC motors. Control, device configuration, and diagnostics are performed through a 16-bit serial peripheral interface (SPI), allowing easy integration into existing applications. This device is powered by SMARTMOS technology. Both channels can be controlled individually by external or internal clock signals, or by direct inputs. Using the internal clock allows fully autonomous device operation. Programmable output voltage slewrates (individually programmable) helps improve electromagnetic compatability (EMC) performance. To avoid shutting off the device upon inrush current, while still being able to closely track the load current, a dynamic overcurrent threshold profile is featured. Switching current of each channel can be sensed with a programmable sensing ratio. Whenever communication with the external microcontroller is lost, the device enters a Fail-safe operation mode, but remains operational, controllable, and protected. HIGH SIDE SWITCH FK SUFFIX (PB-FREE) 98ASA00428D 23 PIN PQFN (12 X12 mm) Features * * * * * * * * * Two fully protected 10 m (@ 25 C) high side switches Up to 6.0 A steady state current per channel Separate bulb and DC motor latched overcurrent handling Individually programmable internal/external PWM clock signals Overcurrent, short-circuit, and overtemperature protection with programmable autoretry functions Accurate temperature and current sensing OpenLoad detection (channel in OFF and ON state), also for LED applications (7.0 mA typ.) Normal operating range: 8.0 - 36 V, extended range: 6.0 - 58 V 3.3 V and 5.0 V compatible 16-bit SPI port for device control, configuration and diagnostics at rates up to 8.0 MHz VDD VDD VPWR 10XS4200 I/O I/O SCLK CSB SI MCU I/O SO I/O I/O GND I/O A/D A/D VDD CLOCK FSB SCLK CSB SO RSTB SI IN0 IN1 CONF0 CONF1 FSOB SYNC CSNS VPWR HS0 HS1 M LOAD GND Figure 1. Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2012-2013. All rights reserved. LOAD ORDERABLE PARTS ORDERABLE PARTS Table 1. Simplified Orderable Part VariationsTable Orderable Part Number MC10XS4200FK MC10XS4200BFK (1) MC10XS4200BAFK (1) Version Reverse Battery voltage (V) Negative clamp voltage (V) - -28 -24 -32 -32 B (2) BA (2), (3) Slew Rates Product ID Bit Standard 00 Accelerated 10 Overcurrent Profile Configuration Hardware Hardware + Software Notes: 1. Recommended for all new designs. 2. Version B and BA devices can support negative voltage battery and ground loss down to -32V, the overcurrent profile can be selected by SPI, errata sheet MC24XS4ER is no more valid. 3. Version BA devices have faster slew rates to reduce switching losses. 10XS4200 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VDD IUP VPWR Internal Regulator VDD Failure Detection POR Over/Undervoltage Protections Charge Pump Drain/Gate Clamp VREG CSB SCLK Selectable Slew Rate Gate Driver IDWN Selectable Overcurrent Detection SO SI RSTB HS0 Severe Short-circuit Detection FSB IN0 Short-circuit to VPWR detec. Control Logic Overtemperature Detect. IN1 FSOB OpenLoad Detect CONF0 CONF1 IUP IDWN RDWN HS0 Calibratable Oscillator * CLOCK HS1 HS1 VREG PWM Module * Temperature Feedback IDWN Output Current Sense Analog MUX Overtemperature Prewarning *blocks marked in grey have implemented independently for each of both channels GND CSNS SYNC Figure 2. Internal Block Diagram 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 3 TABLE OF CONTENTS TABLE OF CONTENTS Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Internal Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection and Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Commands and SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 5 7 7 9 23 26 26 26 28 29 29 35 44 52 54 54 63 10XS4200 4 Analog Integrated Circuit Device Data Freescale Semiconductor PIN ASSIGNMENT PIN ASSIGNMENT CSNS IN0 IN1 FSOB CONF0 CONF1 FSB CLOCK RSTB CSB SCLK SI VDD Transparent Top View 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 SO GND VPWR 23 22 21 GND 14 SYNC GND VPWR VPWR 15 19 20 HS1 HS0 Figure 3. 10XS4200 Pin Assignments The function of each pin is described in the section Functional Description Table 2. 10XS4200 Pin Description Pin Number Pin Name Function Formal Name Definition 1 CSNS Output Output Current/ Temperature Monitoring This pin either outputs a current proportional to the channel's output current or a voltage proportional to the temperature of the GND pin (pin 14). Selection between current and temperature sensing, as well as setting the current sensing sensitivity, are performed through the SPI interface. An external pulldown resistor must be connected between CSNS and GND. 2 3 IN0 IN1 Input Direct Inputs The IN[0 : 1] input pins are used to directly control the switching state of both switches and consequently the voltage on the HS0 : HS1 output pins. The pins are connected to GND by internal pull-down resistors 4 FSOB Output Fail-safe Output (Active Low) FSOB is asserted (active-low) upon entering Fail-safe mode (see Functional Description) This open-drain output requires an external pull-up resistor to VPWR 5 CONF0 Input Configuration Input 6 CONF1 The CONF[0 : 1] input pins are used to select the appropriate overcurrent detection profile (bulb /DC motor) for each of both channels. CONF requires a pull-down resistor to GND. 7 FSB Output Fault Status (Active Low) This open-drain output pin (external pull-up resistor to VDD is required) is set when the device enters Fault mode (see Fault Mode) 8 CLOCK Input PWM Clock The clock input gives the time-base when the device is operated in external clock/internal PWM mode. This pin has an internal pull-down current source. 9 RSTB Input Reset This input pin is used to initialize the device's configuration - and fault registers. Reset puts the device in Sleep mode (low current consumption) provided it is not stimulated by direct input signals.This pin is connected to GND by an internal pull-down resistor. 10 CSB Input Chip Select (Active Low) This input pin is connected to the SPI chip-select output of an external microcontroller. CSB is internally pulled up to VDD by a current source IUP. 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 5 PIN ASSIGNMENT Table 2. 10XS4200 Pin Description (continued) Pin Number Pin Name Function Formal Name Definition 11 SCLK Input Serial Clock This input pin is to be connected to an external SPI Clock signal. The SCLK pin is internally connected to a pull-down current source IDWN 12 SI Input Serial Input This input pin receives the SPI input data from an external device (microcontroller or another extreme switch device in case of daisy-chaining). The SI pin is internally connected to a pull-down current source IDWN 13 VDD Power Digital Drain Voltage 16 SO Output Serial Output This output pin transmits SPI data to an external device (external microcontroller or the SI pin of the next SPI device in case of daisy-chaining). The pin doesn't require external pull-up or pull-down resistors, but a series resistor is recommended to limit current consumption in case of GND disconnection 14, 17, 22 GND Ground Ground These pins, internally connected, are the ground pins for the logic and analog circuitry. It is recommended to also connect these pins on the PCB. 15,18,21 VPWR Power Positive Power Supply These pins, internally connected, supply both the device's power and control circuitry (except the SPI port). The drain of both internal MOSFET switches is connected to them. Pin 15 is the device's primary thermal pad. 19 20 HS1 HS0 Output Power Switch Outputs 23 SYNC Output Output Current Monitoring Synchronization This is the positive supply pin of the SPI interface. Output pins of the switches, to be connected to the load. This output pin is asserted (logic low) when the Current Sense (CS) output signal is within the specified accuracy range. Reading the SYNC pin allows the external microprocessor to synchronize to the device when operating in autonomous operating mode. SYNC is open-drain and requires a pull-up resistor to VDD. 10XS4200 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage. Parameter Symbol Maximum ratings Unit ELECTRICAL RATINGS VPWR Supply Voltage Range VPWR V Load Dump at 25 C (500 ms) 58 Reverse Battery at 25 C 10XS4200FK -28 10XS4200BFKand 10XS4200BAFK -32 Fast Negative Transient Pulses (ISO 7637-2 pulse #1, VPWR=14V & Ri=10) VDD Supply Voltage Range Voltage on Input pins (4) -60 VDD (except IN[0:1]) and Output pins (5) (except HS[0:1]) VMAX,LOGIC (4) -0.3 to 5.5 V -0.3 to 5.5 V Voltage on Fail-safe Output (FSOB) VFSO -0.3 to 58 V Voltage on SO pin VSO -0.3 to VDD+0.3 V Voltage (continuous, max. allowable) on IN[0:1] Inputs VIN,MAX 58 V Voltage (continuous, max. allowable) on output pins (HS [0:1]) VHS[0:1] 10XS4200FK 10XS4200BFK and 10XS4200BAFK Rated Continuous Output Current per V -28 to 58 channel(6) Maximum allowable energy dissipation per channel and two parallel channels, single-pulse method(7) -32 to 58 IHS[0:1] 6.0 A ECL [0:1]_SING 128 mJ Notes: 4. Concerned Input pins are: CONF[0:1], RSTB, SI, SCLK, Clock, and CSB. 5. Concerned Output pins are: CSNS, SYNC, and FSB. 6. Output current rating valid as long as maximum junction temperature is not exceeded. For computation of the maximum allowable output current, the thermal resistance of the package & the underlying heatsink must be taken into account 7. Single pulse Energy dissipation, Single-pulse short-circuit method (LL = 0.5 mH, R = 48 mVPWR = 28 V, TJ = 150 C initial). 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings (continued) All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage. Parameter Symbol Maximum ratings Unit ELECTRICAL RATINGS (CONTINUED) ESD Voltage(8) V Human Body Model (HBM) for HS[0:1], VPWR and GND VESD1 8000 Human Body Model (HBM) for other pins VESD2 2000 VESD3 750 VESD4 500 Ambient TA - 40 to 125 Junction TJ - 40 to 150 TSTG - 55 to 150 C RJC 0.22 C/ W TPPRT Note 10 C Charge Device Model (CDM) Package Corner pins (1, 13, 19, 20) All Other pins THERMAL RATINGS Operating Temperature C Storage Temperature Thermal Resistance Junction to Case Bottom/ VPWR Flag Surface Peak package reflow temperature during reflow(8),(10) Notes: 8. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 9. 10. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 10XS4200 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise. parameter Symbol Min Typ Max Unit Full Specification compliant 8.0 24 36 V Extended Mode(11) 6.0 - 58 SUPPLY ELECTRICAL CHARACTERISTICS Supply Voltage Range: VPWR VPWR Supply Current, device in wake-up mode, channel On, OpenLoad outputs in ON-state, HS[0 : 1] open, IN[0:1] > VIH IPWR(ON) mA 10XS4200FK and 10XS4200BFK - 6.5 8.0 10XS4200BAFK - 6.5 8.5 VPWR Supply Current, device in wake-up mode (Standby), channel Off IPWR(SBY) OpenLoad in OFF-state Detection Disabled, HS[0 : 1] shorted to ground with VDD = 5.5 V and RSTB > VWAKE Sleep State Supply Current mA - 6.5 8.0 A IPWR(SLEEP) VPWR = 24 V, RSTB = IN[0:1] < VWAKE, HS[0 : 1] connected to ground TA = 25 C - 3.0 10.0 TA = 125 C - - 60.0 3.0 - 5.5 VDD Supply Voltage VDD(ON) VDD Supply Current at VDD = 5.5 V IDD(ON) V mA No SPI Communication - - 2.2 8.0 MHz SPI Communication(12) - 5.0 - VDD Sleep State Current at VDD = 5.5 V with or without VPWR IDD(SLEEP) - - 5.0 A Overvoltage Shutdown Threshold VPWR(OV) 39 42 45.5 V VPWR(OVHYS) 0.2 0.8 1.5 V VPWR(UV) 5.0 - 6.0 V VPWR(POR) 2.2 2.6 4.0 V VDD(POR) 1.5 2.0 2.5 V VDD(FAIL) 2.2 2.5 2.8 V Overvoltage Shutdown Hysteresis Undervoltage Shutdown Threshold (13) VPWR Power-On-Reset (POR) Voltage VDD Power-On-Reset (POR) Voltage Threshold(13) Threshold(13) VDD Supply Failure Voltage Threshold (assumed VPWR > VPWR(UV)) Notes 11. In extended mode, several device functions (channel control, RDS(ON) and overtemperature protection) are guaranteed, but compliance with the specified values in this document is not. Below 6.0 V, the device is only protected from overheating (thermal shutdown). Above VPWR(OV), the channels can only be turned ON when the overvoltage detection function has been disabled. 12. 13. Typical value guaranteed per design. When the device recovers from undervoltage and returns to normal mode (6.0 V < VPWR < 58 V) before the end of the auto-retry period (see Auto-retry), the device performs normally. When VPWR drops below VPWR(UV), undervoltage is detected see Undervoltage Fault (Latchable Fault) and EMC Performances. 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise. parameter Symbol Min Typ Max Unit ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) ON-Resistance, Drain-to-Source (IHS = 3.0 A, TJ = 25 C) CSNS_ratio = 0 RDS(ON)25 m VPWR = 8.0 V - - 10 VPWR = 28 V - - 10 VPWR = 36 V - - 10 ON-Resistance, Drain-to-Source (IHS = 3.0 A,TJ = 150 C) CSNS_ratio = 0 RDS(ON)150 m VPWR = 8.0 V - - 18 VPWR = 28 V - - 18 VPWR = 36 V - - 18 -0.8 - +0.8 m - - 18 m ON-Resistance, Drain-to-Source difference from one channel to the other in parallel mode (IHS = 1.0 A,TJ = 150 C) CSNS_ratio = X ON-Resistance, Source-Drain (IHS = -3.0 A, TJ = 150 C, VPWR = -24 V) Max. detectable wiring length (2.5 mm) for severe short-circuit detection RDS(ON)150 RSD(ON)150 LSHORT cm 10XS4200FK and 10XS4200BFK High slew rate selected 20 85 140 Medium slew rate selected: 50 160 300 Low slew rate selected: 100 280 600 10XS4200BAFK High slew rate selected 20 75 130 Medium slew rate selected: 40 135 240 Low slew rate selected: 75 250 430 I_OCH1_0 55 66 77 49 Overcurrent Detection thresholds with CSNS_ratio bit = 0 (CSR0) Overcurrent Detection thresholds with CSNS_ratio bit = 1(CSR1) I_OCH2_0 35 42 I_OCM1_0 22 26 31 I_OCM2_0 13 16 19.5 I_OCL1_0 9.0 10.8 12.6 I_OCL2_0 6.0 7.2 8.4 I_OCL3_0 3.0 3.6 4.2 I_OCH1_1 18.3 22 26.5 I_OCH2_1 11.7 14.0 16.3 I_OCM1_1 7.2 8.7 10.1 I_OCM2_1 4.4 5.3 6.2 I_OCL1_1 3.0 3.6 4.2 I_OCL2_1 2.0 2.4 2.8 I_OCL3_1 0.96 1.2 1.44 A A 10XS4200 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise. parameter Symbol Min Typ Max Unit ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) Output pin leakage Current in sleep state (positive value = outgoing) IOUT_LEAK A 10XS4200FK VHS,OFF = 0 V (VHS,OFF = output voltage in OFF state) - - +16 VHS,OFF = VPWR, device in sleep state (VPWR = 24 V) -40.0 - +5.0 - -120 -1400 - - - +16 +5.0 +5.0 10XS4200BFK and 10XS4200BAFK VHS,OFF = 0 V (VHS,OFF = output voltage in OFF state) VHS,OFF = VPWR, device in sleep state (VPWR = 24 V) VHS,OFF = VPWR, device in sleep state (VPWR = 36 V) Output biasing current in off-state (positive value = outgoing) 10XS4200BFK with OL_OFF disabled (worst case for VPWR = 36 V, VHS,OFF = 34 V) IOUT_OFF Fast slew rate selected Medium slew rate selected Slow slew rate selected 10XS4200BAFK with OL_OFF disabled (worst case for VPWR = 36 V, VHS,OFF = 34 V) -620 -440 -330 -495 -360 -280 -380 -280 -230 -770 -520 -390 0 -620 -420 -315 - -460 -310 -240 1000 VD_GND(CLAMP) 58 - 66 V VDS(CLAMP) 58 - 66 V Fast slew rate selected Medium slew rate selected Slow slew rate selected With OL_OFF disabled and ECU ground disconnected (VPWR = 32 V) for 10XS4200B and 10XS4200BA Switch Turn-on threshold for Supply overvoltage (VPWR -GND) Switch turn-on threshold for Drain-Source overvoltage (measured at IOUT = 500 mA A Current Sensing Ratio (14) - CSNS_ratio bit = 0 (high current mode) CSR0 - 1/3000 - CSNS_ratio bit = 1 (low current mode) CSR1 - 1/1000 - I_LOAD_MIN - - 100 mA ICSR_LEAK -4.0 - +4.0 A 10XS4200FK - 11 - 10XS4200BFK and 10XS4200BAFK - -10 - -150 - 150 Minimum measurable load current with compensated error (16) CSNS leakage current in OFF state (CSNSx_en = 0, CSNS_ratio bit_x = 0) Systematic offset error (see Current Sense Errors) Random offset error I_LOAD_ERR_SYS I_LOAD_ERR_RAND mA mA Notes: 14. Current Sense Ratio CSRx = ICSNS / IHS[x] 15. ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section Current Sense Error Model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS 16. See note (15), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and Use of Offset Compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration. 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise. parameter Symbol Min Typ Max Unit ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) ESR0 Output Current Sensing Error (%, uncompensated(17) at output current level (Sense ratio CSR0 selected): ESR0_ERR % TJ=-40 C 6.0 A -13 - 13 3.0 A -12 - 12 1.5 A -17 - 17 0.75 A -31 - 31 6.0 A -10 - 10 3.0 A -9.0 - 9.0 1.5 A -12 - 12 -19 - 19 TJ=125C 0.75 A TJ=25 to 125C 6.0 A 3.0 A 1.5 A 0.75 A ESR0 Output Current Sensing Error (% after offset compensation output current level (Sense ratio CSR0 selected): (18) at -10 - 10 -9.0 - 9.0 -12 - 12 -22 - 22 ESR0_ERR(Comp) % TJ=-40 C 6.0 A -10 - 10 3.0 A -10 - 10 1.5 A -10 - 10 0.75 A -10 - 10 6.0 A -9.0 - 9.0 3.0 A -8.0 - 8.0 1.5 A -8.0 - 8.0 -9.0 - 9.0 -9.0 - 9.0 -8.0 - 8.0 -8.0 - 8.0 -9.0 - 9.0 TJ=125C 0.75 A TJ=25 to 125C 6.0 A 3.0 A 1.5 A 0.75 A Notes: 17. ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section Current Sense Error Model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS 18. See note (17), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and Use of Offset Compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration. 10XS4200 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise. parameter Symbol Min Typ Max Unit ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) ESR1 Output Current Sensing Error (%, uncompensated (19) at output current level (Sense ratio CSR1 selected): ESR1_ERR % TJ=-40 C 1.5 A -15 - 15 -12 - 12 -12 - 12 TJ=125C 1.5 A TJ=25 to 125C 1.5 A ESR1 Output Current Sensing Error (% (level) after offset compensation(20) at output current level (Sense ratio CSR1 selected): ESR1_ERR(Comp) % TJ=-40 C 1.5 A -10 - 10 0.5 A -11 - 11 0.25 A -18 - 18 0.15 A -29 - 29 1.5 A -8.0 - 8.0 0.5 A -10 - 10 0.25 A -12 - 12 -16 - 16 -8.0 - 8.0 -10 - 10 -13 - 13 -21 - 21 TJ=125C 0.15 A TJ=25 to 125C 1.5 A 0.5 A 0.25 A 0.15 A ESR0 Output Current Sensing Error in parallel mode (%, uncompensated(19)) at outputs Current level (Sense ratio CSR0 selected): ESR0_ERR_PAR % TJ=-40 C 6.0 A -10 - 10 3.0 A -11 - 11 6.0 A -8.0 - 8.0 3.0 A -8.0 - 8.0 6.0 A -8.0 - 8.0 3.0 A -8.0 - 8.0 5.5 - 7.5 TJ=125C TJ=25 to 125C Current Sense Clamping Voltage (condition: R(CSNS) > 10 kOhm) VCL(CSNS) V Notes: 19. ESRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section Current Sense Error Model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS 20. See note (19), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and Use of Offset Compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration. 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise. parameter Symbol Min Typ Max Unit IOLD(OFF) 30 - 100 A VOLD(THRES) 4.0 - 5.5 V 10XS4200FK 120 300 600 10XS4200BFK and 10XS4200BAFK 80 300 600 5.0 7.0 10 ELECTRICAL CHARACTERISTICS OF THE OUTPUT STAGE (HS0 AND HS1) (CONTINUED) OpenLoad detection Current threshold in OFF state (21) OpenLoad Fault Detection Voltage Threshold (21) OpenLoad detection Current threshold in ON state (see OpenLoad Detection In On State (OL_ON)): IOLD(ON) CSNS_ratio bit = 0 mA CSNS_ratio bit = 1 (fast slew rate SR[1:0] = 10 mandatory for this function) Time period of the periodically activated OpenLoad in ON state detection for CSNS_ratio bit = 1 tOLLED 105 150 195 ms Output Shorted-to-VPWR Detection Voltage Threshold (channel in OFF state) VOSD(THRES) VPWR-1.2 VPWR-0.8 VPWR-0.4 V Switch turn-on threshold for Negative Output Voltages (protects against negative transients) - (measured at IOUT = 100 mA, Channel in OFF state) VCL V 10XS4200FK -35 - -24 10XS4200BFK and 10XS4200BAFK -38 - -32 -2.0 - +2.0 V VHS_TH 0.45*VPWR 0.5*VPWR 0.55*VPWR V TSD 160 175 190 C VIH 2.0 - 5.5 V VIL -0.3 - 0.8 V VWAKE 1.0 - 2.2 V IDWN 5.0 - 20 A IUP_CSB 5.0 - 20 A IUP_CONF 25 - 100 A CSO - - 20 pF RDWN 125 250 500 k CIN - 4.0 12 pF Switch turn-on threshold for Negative Output Voltages difference from one channel to the other in parallel mode - (measured at IOUT = 100 mA, Channel in OFF state) Switching State (On/Off) discrimination thresholds Shutdown temperature (Power MOSFET junction; 6.0 V < VPWR < 58 V) VCL ELECTRICAL CHARACTERISTICS OF THE CONTROL INTERFACE PINS Logic Input Voltage, High(22) Logic Input Voltage, Low(22) Wake-up Threshold Voltage (IN[0:1] and RSTB)(23) Internal Pull-down Current Source (on inputs: CLOCK, SCLK and SI) Internal Pull-up Current Source (input CSB)(25) Internal Pull-up Current Source (input CONF[0:1]) (26) Capacitance of SO, FSB and FSOB pins in Tri-state Internal Pull-down Resistance (RSTB and IN[0:1]) Input Capacitance (27) (24) Notes: 21. Minimum required value of OpenLoad impedance for detection of OpenLoad in OFF-state: 200 k.(VOLD(THRES) = VHS @ IOLD(OFF)) 22. High and low voltage ranges apply to SI, CSB, SCLK, RSTB, IN[0:1] and CLOCK input signals. The IN[0:1] signals may be derived from VPWR and can tolerate voltages up to 58 V. 23. 24. Voltage above which the device wakes up Pull-down current-value for VSI > 0.8 V and VSCLK > 0.8 V and VCLOCK > 0.8 V. 25. Pull-up current-value for VCSB < 2.0 V. CSB has an internal pull-up current source connected to VDD. 26. Pins CONF[0:1] are connected to an internal current source, connected itself to an internal voltage regulator (VREG ~ 3.0 V). 27. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CONF[0:1], and CLOCK pins. This parameter is guaranteed by the manufacturing process but is not tested in production. 10XS4200 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 C, VPWR = 28 V & VDD = 5.0 V, unless specified otherwise. parameter Symbol Min Typ Max VDD-0.4 - - - - 0.4 Unit ELECTRICAL CHARACTERISTICS OF THE CONTROL INTERFACE PINS (CONTINUED) SO High-state Output Voltage VSOH (IOH = 1.0 mA) SYNC, SO, FSOB and FSB Low-state Output Voltage VSOL (IOL = -1.0 mA) SYNC, SO, CSNS, FSOB and FSB Tri-state Leakage Current: V V A ISO(LEAK) (0.0 V < V(SO) < VDD, or V(FS) or V(SYNC) = 5.5 V, or V(FSO) = 36 V or V(CSNS) = 0 V - 2.0 0.0 2.0 - Lighting applications 1.0 - 10 - DC motor applications 50 - Infinite CONF[0:1] Required values of the External Pull-down Resistor RCONF k 10XS4200 15 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise. Parameter Symbol Min Typ Max Unit OUTPUT VOLTAGE SWITCHING CHARACTERISTICS Rising and Falling edges medium slew rate (SR[1:0] = 00)(28) SRR_00 10XS4200FK and 10XS4200BFK SRF_00 V/s VPWR = 16 V 0.164 - 0.65 VPWR = 28 V 0.28 - 0.79 VPWR = 36 V 0.34 - 0.90 VPWR = 16 V 0.25 - 1.1 VPWR = 28 V 0.45 - 1.4 0.5 - 1.5 10XS4200BAFK VPWR = 36 V Rising and Falling edges low slew rate (SR[1:0] = 01)(28) SRR_01 10XS4200FK and 10XS4200BFK SRF_01 V/s VPWR = 16 V 0.081 - 0.32 VPWR = 28 V 0.14 - 0.395 VPWR = 36 V 0.17 - 0.45 VPWR = 16 V 0.125 - 0.55 VPWR = 28 V 0.225 - 0.7 0.25 - 0.75 10XS4200BAFK VPWR = 36 V Rising and Falling edges high slew rate / SR[1:0] = 10)(28) SRR_10 10XS4200FK and 10XS4200BFK SRF_10 V/s VPWR = 16 V 0.29 - 1.30 VPWR = 28 V 0.55 - 1.58 VPWR = 36 V 0.68 - 1.80 VPWR = 16 V 0.5 - 2.2 VPWR = 28 V 0.9 - 2.8 1.0 - 3.0 0.75 1.0 1.2 SR[1:0] = 00 -0.1 0.0 +0.1 SR[1:0] = 01 -0.06 0.0 +0.06 -0.14 0.0 +0.14 -0.2 0.0 0.2 10XS4200BAFK VPWR = 36 V Rising/Falling edge slew rate matching (SRR /SRF) SR 16 V < VPWR < 36 V Edge slew rate difference from one channel to the other in parallel mode(28) SR 16 V < VPWR < 36 V V/s 10XS4200FK and 10XS4200BFK SR[1:0] = 10 10XS4200BAFK SR[1:0] = 10 10XS4200 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics (continued) Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise. Parameter Symbol Min Typ Max Unit SWITCHING CHARACTERISTICS (CONTINUED) Output Turn-ON and Turn-OFF Delays (medium slew rate: SR[1:0] = 00) 16 V < VPWR < 36 V s t DLY_00 (29) 10XS4200FK and 10XS4200BFK 32 - 128 10XS4200BAFK 20 - 120 Output Turn-ON and Turn-OFF Delays (medium slew rate / SR[1:0] = 01) s t DLY_01 16 V < VPWR < 36 V(29) 10XS4200FK and 10XS4200BFK 59 - 245 10XS4200BAFK 40 - 240 Output Turn-ON and Turn-OFF Delays (medium slew rate / SR[1:0] = 16) s t DLY_10 16 V < VPWR < 36 V(29) 10XS4200FK and 10XS4200BFK 18 - 68 10XS4200BAFK 10 - 60 -25 0.0 25 Turn-ON and Turn-OFF Delay time matching (t DLY(ON) - t DLY(OFF)) t RF_00 f PWM = 400 Hz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 00 Turn-ON and Turn-OFF Delay time matching (t DLY(ON) - t DLY(OFF)) s t RF_01 s f PWM = 200 Hz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 01 10XS4200FK and 10XS4200BAFK -50 0.0 50 10XS4200BFK -90 0.0 90 -13 0.0 13 Turn-ON and Turn-OFF Delay time matching (t DLY(ON) - t DLY(OFF)) f PWM = 1.0 kHz, 16 V < VPWR < 36 V, duty cycle on IN[x] = 50 %, SR[1:0] = 10 t RF_10 s Notes 28. Rising and Falling edge slew rates specified for a 20 to 80% voltage variation on a 10 resistive load (see Figure 4). 29. Turn-on delay time measured as delay between a rising edge of the channel control signal (IN[0 : 1] = 1 or CSB) and the associated rising edge of the output voltage up to: VHS[0 : 1] = VPWR / 2 (where RL = 5.0). Turn-OFF delay time is measured as time between a falling edge of the channel control signal (IN[0 : 1] = 0 or CSB pin) and the associated falling edge of the output voltage up to the instant at which: VHS[0 : 1] = VPWR / 2 (RL = 5.0 ) 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 17 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics (continued) Unless specified otherwise: 8.0 V VPWR 36 V, 3.0 V VDD 5.5 V, - 40 C TA 125 C, GND = 0 V. Typical values are average values evaluated under nominal conditions TA = 25 C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise. Parameter Symbol Min Typ Max Unit SWITCHING CHARACTERISTICS (CONTINUED) Delay time difference from one channel to the other in parallel mode(30) t(DLY) 16 V < VPWR < 36 V s SR[1:0] = 00 10XS4200FK -21 0.0 21 10XS4200BFK and 10XS4200BAFK -25 0.0 25 10XS4200FK -40 0.0 40 10XS4200BFK and 10XS4200BAFK -50 0.0 50 10XS4200FK -11 0.0 11 10XS4200BFK and 10XS4200BAFK -12 0.0 12 SR[1:0] = 01 SR[1:0] = 10 Fault Detection Delay Time(31) tFAULT - 5.0 8.0 s Output Shutdown Delay Time(32) tDETECT - 7.0 12 s Current sense output settling Time for SR[1:0] = 00 (medium slew rate) (33) t CSNSVAL_00 s 10XS4200FK and 10XS4200BFK 16 V < VPWR < 36 V 0.0 - 210 0.0 - 200 10XS4200BAFK 16 V < VPWR < 36 V Current sense output settling Time for SR[1:0] = 01(low slew rate) (33) t CSNSVAL_01 s 10XS4200FK and 10XS4200BFK 16 V < VPWR < 36 V 0.0 - 310 0.0 - 300 10XS4200BAFK 16 V < VPWR < 36 V Current sense output settling Time for SR[1:0] = 10 (high slew rate) (33) t CSNSVAL_10 s 10XS4200FK and 10XS4200BFK 16 V < VPWR < 36 V 0.0 - 175 0.0 - 165 10XS4200FK 50 - 150 10XS4200BFK 50 - 160 10XS4200BAFK 25 - 130 10XS4200BAFK 16 V < VPWR < 36 V SYNC output signal delay for SR[1:0] = 00 (medium SR) (33) t SYNCVAL_00 s Notes: 30. Rising and Falling edge slew rates specified for a 20 to 80% voltage variation on a 10 resistive load (see Figure 4). 31. Time required to detect and report the fault to the FSB pin. 32. Time required to switch off the channel after detection of overtemperature (OT), overcurrent (OC), SC or UV error (time measured between start of the negative edge on the FSB pin and the falling edge on the output voltage until V(HS[0:1)) = 50% of VPWR 33. Settling time ( = t CSNSVAL_xx), SYNC output signal delay ( = t SYNCVAL_xx) and Read-out delay ( = t SYNREAD_xx) are defined for a stepped load current (100 mA< I(LOAD) 4.0 MHz, series resistors on the SPI pins should preferably be removed. Otherwise, 470 pF (VMAX. > 40 V) ceramic speed-up capacitors in parallel with the >8.0 k input resistors are required on pins SCLK, SI, SO, and CS. 10XS4200 22 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS IN[0:1] High Logic Level Low Logic Level Time or CSB High Logic Level Low Logic Level Time VHS[0:1] RPWM range defined for 50% of VPWR VPWR 50%VPWR Time VHS[0:1] 80% VPWR 20% VPWR t DLY_xx (t DLY(ON)) SR R t DLY_xx (t DLY(OFF)) SR F Time Figure 4. Output Voltage Slew Rate and Delay IOCH1 IOCH2 Load Current Bulb profile: CONFs = 0 (V (pin 5/6) <0.8 V). Static overcurrent protection profile activated once per turn-on. Default levels shown as solid lines IOCM1 IOCM2 IOCL1 IOCL2 IOCL3 Time t OCM2_L t OCM1_L t OCH2 t OCH1 Figure 5. Overcurrent Protection Profile for Bulb Applications 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 23 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS IOCH1 Inductive Load profile: CONFs = 1 (V (pin 5/6) > 2.0 V) IOCH2 Default levels shown as solid lines Dynamic overcurrent window, activated when the IOCLx threshold is crossed Load Current IOCL1 IOCL2 Load current IOCL3 Time t OCM2_M t OCM1_M t OCH2 t OCH1 Figure 6. Overcurrent Protection Profile for Applications with Inductive Loads (DC motors, solenoids) RSTB VIH 10% VDD VIL tWRSTB tCSB tENBL CSB 90% VDD VIH 10% VDD VIL tLEAD tRS tWSCLKh tLAG VIH 90% VDD 10% VDD SCLK tSI(SU) VIL tWSCLKl tSI(HOLD) SI Don't Care 90% VDD 10% VDD tFS VIH Must be Valid Don't Care Must be Valid Don't Care VIL Figure 7. Timing Requirements During SPI Communication 10XS4200 24 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS tFSI tRSI VOH 90% VDD 50% SCLK 10% VDD VOL tSO(EN) VOH 10% VDD SO VOL Low to High tRSO tVALID tFSO SO High To Low VOH 90% VDD 10% VDD VOL tSO(DIS) Figure 8. Timing Diagram for Serial Output (SO) Data Communication turn-on control (from IN_s or CSB) See Figure 4 VHS[0:1] turn-off control (from IN_s or CSB) VPWR 50%VPWR Time VCSNS t DLY_xx (t DLY(ON)) 95% of scaled output current VSYNC 5.0 V t DLY_xx (t DLY(OFF) synchronous Mode t SYNCVAL Track & Hold Mode Time t CSNSVAL_xx t SYNREAD_xx 0.0 V Time Figure 9. Synchronous & Track-and-Hold Current Sensing Modes: Associated Delay & Settling Times 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 10XS4200 is a two-channel, 24 V high side switch with integrated control and diagnostics designed for truck, bus, and industrial applications. The device provides a high number of protective functions. Both low RDS(ON) channels (<10 m) can independently drive various load types like light bulbs, solenoid actuators, or DC motors. Device control and diagnostics are configured through a 16-bit SPI port with daisy-chain capability. Independently programmable output voltage slew rates allow satisfying electromagnetic compatibility (EMC) requirements. Both channels can independently be operated in three different switching modes: internal clock and internal PWM mode (fully autonomous operation), external clock and internal PWM mode, and direct control switching mode. Current sensing with an adjustable ratio is available on both channels, allowing both high-current (bulbs) and lowcurrent (LED) monitoring. By activating the Track & Hold mode, current monitoring can be performed during the switch-Off phase. This allows random access to the current sense functionality. A patented offset compensation technique further enhances current sense accuracy. To avoid turning off upon inrush current, while being able to monitor it, the device features a dynamic overcurrent threshold profile. For bulbs, this profile is a stair function with stages of which the height and width are programmable through the SPI port. DC motors can be protected from overheating by activating a specific window-shaped overcurrent profile that allow stall currents of limited duration. Whenever communication with the external microcontroller is lost, the device enters Fail-safe Operation mode, but remains operational, controllable and protected. PIN ASSIGNMENT AND FUNCTIONS All logic input and output "pins" must be protected by series resistors of at least 1.0 kOhm, unless specified otherwise. Functions and register bits that are implemented independently for both channels have extension "_s". OUTPUT CURRENT MONITORING (CSNS) The CS pin allows independent current monitoring of channel 0 or channel 1 up to the steady-state overcurrent threshold. It can also be used to sense the device temperature. The different functions are selected by setting bits CSNS1_en and CSNS0_en to the appropriate value (Table 23). When the CSNS pin is sensed during switch-off in the (optional) track & hold mode (see Figure 9), it outputs the scaled value of the load current as it was just before turn-Off. When several devices share the same pull-down resistor, the CSNS pins of devices, the current of which is not monitored, must be tri-stated. This is accomplished by setting CSNS0_en = 0 and CSNS1_en = 0 in their GCR register (Table 12). Settling time (tCSNSVAL_XX) is defined as the time between the instant at the middle of the output voltage's rising edge (HS[0:1] = 50% of VPWR), and the instant at which the voltage on the CSNS pin has settled to 5.0% of its final value. Anytime an overcurrent window is active, the CSNS pin is disabled (see Overcurrent Detection on Resistive and Inductive Loads). The current and temperature sensing functions are unavailable in Fail-safe mode and in Normal mode when operating without the VDD supply voltage. In order to generate a voltage output, this pin requires a pulldown resistor (R(CSNS)=1.0 k typ. and 470 < R(CSNS) < 10 k). When the current sense resistor connected to the CSNS pin is disconnected, the CSNS voltage is clamped to VCL(CSNS). The CSNS pin can source currents up to about 5.6 mA. CURRENT SENSE SYNCHRONIZATION (SYNC) To synchronize current sensing with an external process, the SYNC signal can be connected to a digital input of an external MCU. An open-drain pull-down on SYNC indicates that the current sense signal is accurate and ready to be read. The current sense signal on the CSNS pin has the specified accuracy tSYNREAD_XX seconds after the falling edge on the SYNC pin (Figure 9) and remains valid until a rising edge is generated. The rising edge that is generated by the SYNC pin at the turn-OFF instant (internal or external) may also be used to implement synchronization with the external MCU. Parameter tSYNCVAL_xx is defined as the time between the instant at the middle of the output voltage rising edge (HS[0:1] = 50% of VPWR), and the instant at which the voltage on the SYNC-pin drops below 0.4 V (VSOL). The SYNC pins of different devices can be connected together to save micro-controller input channels. However, in this configuration, the CSNS of only one device should be active at a time. Otherwise, the MCU is not be able to determine the source of the SYNC signal. The SYNC pin requires an external pull-up resistor to VDD. DIRECT CONTROL INPUTS (IN0 AND IN1) The IN[0:1] pins allow direct control of both channels. A logic [0] level turns off the channel and a logic[1] level turns it on. When the device is in Sleep mode, a transition from logic 0 to logic 1 on any of these pins wakes it up (Channel configuration through the SPI). If it is desired to automatically turn on the channels after a transition to Fail-safe mode, inputs IN[0] and IN[1] must be externally connected to the VPWR pin by a pull-up resistor (e.g. 10 ktyp. However, 10XS4200 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION PIN ASSIGNMENT AND FUNCTIONS this prevents the device from going into Sleep mode. Both IN pins are internally connected to a pull-down resistor. CONFIGURATION INPUTS (CONF0 AND CONF1) The CONF[0 :1] input pins allow configuring both channels for the appropriate load type. CONF = 0 activates the bulb overcurrent protection profile, and CONF = 1 the DC motor profile. These inputs are connected to an internal voltage regulator of 3.3 V by an internal pull-up current source IUP. Therefore, CONF = 1 is the default value when these pins are disconnected. Details on how to configure the channels are given in the table Overcurrent Profile Selection. FAULT STATUS (FSB) This open-drain output is asserted low when any of the following faults occurs (see Fault Mode): overcurrent (OC), overtemperature (OT), output connected to VPWR, severe short-circuit (SC), OpenLoad in ON state (OL_ON), OpenLoad in OFF state (OL_OFF), external clock-fail (CLOCK_fail), overvoltage (OV), undervoltage (UV). Each fault type has its own assigned bit inside the STATR, FAULTR_s, or DIAGR_s register. Fault type identification and fault bit reset are accomplished by reading out these registers. The registers are part of the SO register (Table 13), and are accessed through the SPI port. PWM CLOCK (CLOCK) This pin is the input for an external clock signal that controls the internal PWM module.The clock signal is monitored by the device. The PWM module controls ON-time and turn-ON delay of the selected channels. The CLOCK pin should not be confused with the SCLK pin, which is the clock pin of the SPI interface. CLOCK has an internal pull-down current source (IDWN) to GND. RESET (RSTB) All SPI register contents are reset when RSTB = 0. When RSTB = 0, the device returns to Sleep mode tIN sec. after the last falling edge of the last active IN[0:1] signal. As long as the Reset input (RSTB pin) is at logic 0 and both direct input states remain low, the device remains in Sleep mode (Channel configuration through the SPI). A 0-to-1 transition on RSTB wakes the device and starts a watchdog timer to check the continuous presence of the SPI signals. To do this, the device monitors the contents of the first bit (WDIN bit) of all SPI words, following that transition (regardless the register it is contained in). When this contents is not alternated within a duration tWDTO, SPI communication is considered lost, and Fail-safe mode is entered (Entering Fail-safe Mode). RSTB pin is internally pulled to GND by a RDWN resistor. CHIP SELECT (CSB) Data communication over the SPI port is enabled when the CSB pin is in the logic [0] state. Data from the Input Shift registers are locked in the addressed SI registers on the rising edge of CSB. The device transfers the contents of one of the eight internal registers to the SO register on the falling edge of CSB. The SO output driver is enabled when CSB is logic [0]. CSB should transition from a logic [1] to a logic [0] state only when SCLK is at logic [0]. CSB is internally pulled up to VDD through IUP. (see Figure 7 and Figure 8). SPI SERIAL CLOCK (SCLK) The SCLK pin clocks the SPI data communication of the device. The serial input pin (SI) transfers data to the SI shift registers on the falling edge of the SCLK signal while data in the SO registers are transferred to the SO pin on the rising edge of the SCLK signal. The SCLK pin must be in low state when CSB makes any transition. For this reason, it is recommended to have the SCLK pin at a logic [0] state when the device is not accessed (CSB logic [1] state). When CSB is set to logic [1], signals at the SCLK and SI pins are ignored and the SO output is tri-stated (high-impedance). The SCLK pin is connected to an internal pull-down current source IDWN. SERIAL INPUT (SI) Serial input (SI) data bits are shifted in at this pin. SI data is read on the falling edge of SCLK. 16-bit data packages are required on the SI pin (see Figure 7), starting with bit D15 (MSB) and ending with D0 (LSB). All the internal device registers are addressed and controlled by a 4-bit address (D9-D12) described in Table 11. Register addresses and function attribution are described in Table 12. The SI pin is internally connected to a pull-down current source, IDWN. SUPPLY OF THE DIGITAL CIRCUITRY (VDD) This pin supplies the SPI circuit (3.3 V or 5.0 V). When lost, all circuitry is supplied by a VPWR derived voltage, except the SPI's SO shift-register, which can no longer be read. GROUND (GND) This is the GND pin common for both the SPI and the other circuitry. POSITIVE SUPPLY PIN (VPWR) This pin is the positive supply and the common input pin of both switches. A 100 nF ceramic capacitor must be connected between VPWR and GND, close to the device. In addition, it is recommended to place a ceramic capacitor of at least 1.0 F in parallel with this 100 nF capacitor. SERIAL OUTPUT (SO) The SO pin is a tri-stateable output pin that conveys data from one of the 13 internal SO registers, or from the previous SI register, to the outside world. The SO pin remains in a high-impedance state (tri-state) until the CSB pin becomes logic [0]. It then transfers the SPI data (device state, configuration, fault information). The SO pin changes state at the rising edge of the SCLK signal. For daisy-chaining, it can be read out on the falling edge of SCLK. VDD must be present before the SO registers can be read. The SO register assignment is described in Table 13. 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION OUTPUT PINS (HS0 AND HS1) FAIL-SAFE OUTPUT (FSOB) HS0 and HS1 are the output pins of the power switches to be connected to the loads. A ceramic <= 22 nF (+/- 20%) capacitor is recommended between these pins and GND for optimal EMC performances. This pin (active low) is used to indicate loss of SPI communication or loss of SPI supply voltage, VDD. This opendrain output requires an external pull-up resistor to VPWR. FUNCTIONAL INTERNAL BLOCK DESCRIPTION POWER SUPPLY internal regulator MCU INTERFACE MCU INTERFACE and OUTPUT CONTROL SELFPROTECTED HIGH SIDE SWITCHES HS0-HS1 SPI INTERFACE PARALLEL CONTROL INPUTS PWM CONTROLLER POWER SUPPLY The device operates with supply voltages from 6.0 to 58 V (VPWR), but is full spec. compliant between 8.0 and 36 V. The VPWR pin supplies power to the internal regulator, analog, and logic circuit blocks. The VDD pin (5.0 V typ.) supplies the output register of the Serial Peripheral Interface (SPI). Consequently, the SPI registers cannot be read without presence of VDD. The employed IC architecture guarantees a low quiescent current in Sleep mode. SWITCH OUTPUT PINS HS0 & HS1 HS0 and HS1 are the output pins of the power switches. Both channels are protected against various kinds of shortcircuits and have active clamp circuitry that may be activated when switching off inductive loads. Many protective and diagnostic functions are available. For large inductive loads, it is recommended to use a freewheeling diode. The device can be configured to control the output switches in parallel, which guarantees good switching synchronization. COMMUNICATION INTERFACE AND DEVICE CONTROL In Normal mode the output channels can either be controlled by the direct inputs or by the internal PWM module, which is configured by the data stored in the SPI registers. For bidirectional SPI communication, VDD has to be in the authorized range. Failure diagnostics and configurations are also performed through the SPI port. The reported failure types are: OpenLoad, short-circuit to battery, severe shortcircuit to ground, overcurrent, overtemperature, clock-fail, undervoltage, and overvoltage. The SPI port can be supplied either by a 5.0 V or by a 3.3 V voltage supply. For direct input control, VDD is not required. A Pulse Width Modulation (PWM) circuit allows driving loads at frequencies up to 1.0 kHz from an external or an internal clock. SPI communication is required to set these options. 10XS4200 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES The device possesses two high side switches (channels) each of which can be controlled independently. The device has four fundamental operating modes: Sleep, Normal, Failsafe, and Fault mode, as shown in Table 6. Each channel can be controlled in three different ways in Normal mode: by a signal on the Direct Input pin, by an internal clock signal (autonomous operation) or by an external clock signal. For bidirectional SPI communication, a second supply voltage is required (VDD = 5,0 V or 3.3 V). When only the direct inputs IN[x] are used, VDD isn't required. DEVICE START-UP SEQUENCE To put the device in a known configuration and guarantee predictable behavior, the device must undergo a wake-up sequence. However, it should not be woken up earlier than the moment at which VPWR has exceeded its undervoltage threshold, VPWR(UV), and VDD has exceeded its supply failure threshold, VDD(FAIL). In applications using the SPI port, the device is typically put in wake mode by setting RSTB=1. Wake-up of applications with direct input control can be achieved by having signals IN_ON[0] = 1 or IN_ON[1 ]= 1 (see Figure 10). After wake-up, all SPI register contents are reset and Normal mode is entered (as defined in Table 12 and Table 13). All the device functions are available 50 s later (typically). If the start-up sequence is not performed at device startup, its configuration may be undetermined and correct operation is not guaranteed. In situations where the above described start-up sequence can not be performed, it is recommended to generate a wake-up event after the moment VPWR has reached the undervoltage threshold. CHANNEL CONFIGURATION THROUGH THE SPI Setting the Channel Configuration The channel configuration is determined by the contents of the pulse-width (PWMR_s), the configuration (CONFR_s) and the overcurrent (OCR_s) registers. They allow setting, among others, the following parameters: duty-cycle, delay, Slew Rate, PWM enable (PWM_en), clock selection (CLOCK_sel), prescaler (PR), and direct_input disable (DIR_dis). Extension "_s" means that these registers exist for each of both channels. Function assignment is described in detail in the section SI Register Addressing Reading Back the Channel's Status and Settings The channel's global switching and operating states (On/ Off, normal/fault) are all contained in the STATR register (see Table 13). The precise fault type can be found by reading out the FAULTR_s and STATR registers. The channel' settings (channel configuration) can be read back by reading the PWMR, CONF, OCR, RETRY, GCR, and DIAG registers. For more information, see Serial Output Register Assignment. NORMAL MODE Normal mode (bit NM = 1) can be entered in two ways, either by driving the device through the direct inputs IN[x], or by establishing SPI communication (requires RSTB =high). Bidirectional SPI communication additionally requires the presence of VDD. To maintain the device in Normal mode, communication must take place regularly (see Entering and Maintaining Normal Mode). The device is in Normal mode (NM) when: * VPWR (and VDD) are within the normal range and * wake-up = 1, and * fail-safe = 0, and * fault = 0. Channel Control in Normal Mode In direct input mode, the channel's switching state (On/Off) basically follows the logic state of the direct input signal with the turn-on delay and slew rate specified in Table 5. In internal clock mode, the switching state is controlled by an internal clock signal (Internal Clock & Internal PWM (Clock_int_s bit = 1)). Frequency, slew rate, duty-cycle, and turn-on delay are programmable independently for both channels. In external clock mode, the frequency of the external clock controls the output's PWM frequency, but slew rate, duty cycle, and turn-on delay are still programmable. Factors Determining the Channel's Switching State The switching state of a channel is defined by the instantaneous value of the output voltage. It is defined as "On" when the output voltage V(HS[x]) > VPWR /2 and "Off" when V(HS[x]) < VPWR /2. The channel's switching state should not be confused with the device's internal channel control state hson[x] (= High Side On). Signal hson[x] defines the targeted switching state of the channel (On/Off). It is either controlled by the value of the direct input signal or by that of the internal/external clock signals combined with the SPI register settings. The value of hson[x] is given by the following boolean expression: hson[x] = [(IN[x] and DIR_dis[x]) or (On bit [x] and Duty_cycle[x] and PWM_en[x] = 1) or (On bit [x] and PWM_en[x] = 0)]. In this expression Duty_cycle[x] represents the value of the duty cycle, set by bits D7...D0 of the PWMR register (Table 7). The channel's actual switching state may differ from the control signal's state in the following cases: * short circuits to GND, before automatic turn-Off (t < tFAULT) * short circuits to VPWR when the channel is set to Off 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES * VPWR < 13 V when OpenLoad in Off state detection is selected and the load is actually lost * during the turn-on transition as long as V(HS[x])< VPWR/2 * during the turn-off transition as long as V(HS[x]) > VPWR/2 Entering and Maintaining Normal Mode A 0-to-1 transition on RSTB, (when both VPWR and VDD are present) or on any of both direct inputs IN[x] (when only supplied by VPWR), puts the device in Normal mode. If desired, the device can be operated in Normal mode without VDD, but this requires that at least one of both direct inputs be regularly turned on (Operation and Operating Modes). To maintain the device in Normal mode (NM), communication must take place on a regular basis. For SPI communication, the state of the WDIN bit must be alternated at least every 310 ms (typ.) (tWDTO), unless the WD_disable bit is set to 1. For direct input control, the timing requirements are shown in Figure 10. A signal called IN_ON[x] is not directly accessible to the user but is used by the internal logic circuitry to determine the device state. When no activity is detected on a direct input pin (IN[x]) for a time longer than tIN = 250 ms (typ.), timeout is detected and IN_ON[x] goes low. When this occurs on both channels, Sleep mode is entered (Sleep Mode), provided reset = RSTB = 0 Direct Control Mode When RSTB = 0 (and also in Fail-safe mode), the channels are merely controlled by the direct input pins IN[x]. All protective functions (OC, OT, SC, OV, and UV) are operational including auto-retry. To avoid entering Sleep mode at frequencies < 4.0 Hz, reset should be set to RSTB = 1. Going from Normal to Fail-safe, Fault or Sleep Mode The device changes from Normal to Fail-safe (Fail-safe Mode), Sleep mode (Sleep Mode), or Fault mode (Fault Mode), according to the value of the following signals (see Table 6). * wake-up = RSTB or IN_ON[0] or IN_ON[1] * fail-safe = (VDD Failure and VDD_FAIL_en) or (SPI watchdog timeout (tWDTO) and WD_DIS = 0) * fault = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and OV_DISB) Table 6. Device Operating Modes FailFault Comments safe Mode Wake-up Sleep 0 x x All channels are OFF. Normal 1 0 0 The SPI Watchdog is active when: VDD = 5.0 V, WD_DIS = 0, RSTB = 1 Fail-safe 1 1 0 The channels are controlled by the IN inputs. (see Fail-safe Mode) Fault 1 X 1 The channels are OFF, see Fault Mode. . IN[x] tIN IN_ON[x] Figure 10. Relation Between Signals IN(x) and IN_ON[x] x = Don't care. 10XS4200 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES (WD_dis = 1, D4 of the GCR register) avoids entering Failsafe mode after a watchdog timeout. Device behavior upon fault occurrence is explained in the paragraph on Faults (Fault Mode). It enters Fail-safe mode, when either a timeout on SPI communication or when VDD is lost, after having been initially present (if this function was previously enabled by setting: VDD_FAIL_EN bit = [1]). Setting watchdog disabled Sleep (wake-up = 0) (wake-up = 1) and (fail-safe = 1) and (fault = 0) (wake-up = 1) and (fault = 1) (wake-up = 0) (fail-safe = 1) and (wake-up = 1) and (fault = 1) Fail-safe (fail-safe = 0) and (wake-up = 1) and (fault = 0) Fault (fail safe = 1) and (wake-up = 1) and (fault = 0) (wake-up = 0) (fail-safe = 0) and (wake-up = 1) and (fault = 1) Normal (fail-safe = 0) and (wakeup = 1) and (fault = 0) (fail-safe = 0) and (wake-up = 1) and (fault = 0) (fail-safe = 1) and (wake-up = 1) and (fault = 0) Figure 11. Device Operating Modes SLEEP MODE In Sleep mode, the channels and the SPI interface are turned off to minimize current consumption. The device enters Sleep mode (wake-up = 0) when both Direct Input pins IN(x) remain Off longer than tIN sec. (when reset is active; RSTB = 0). This is expressed as follows: * VPWR (and VDD) are within the normal range, and * wake-up = 0 (wake-up = RSTB or IN_ON[0] or IN_ON[1]), and * fail-safe = X, and * fault = X When employed, VDD must be kept in the normal range. Sleep mode is the default mode after the first application of the supply voltage (VPWR), prior to any I/O communication (RSTB and the internal states IN_ON[0:1] are still at logic [0]). All SPI register contents remain in their default state during Sleep mode. FAIL-SAFE MODE Entering Fail-safe Mode Fail-safe mode is entered either upon loss of SPI communication or after loss of optional SPI supply voltage VDD (VDD Out of Range). The FSOB pin goes low and the channels are only controlled by the direct inputs (IN[0:1]). All protective functions remain fully operational. Previously latched faults are delatched and SPI register contents is reset (except bits POR & PARALLEL). The SPI registers can not be accessed. These conditions are also described by the following expressions: * VPWR is within the normal voltage range, and * wake-up = 1, fault = 0, and * fail-safe = 1 ((VDD Failure and VDD_FAIL_en=1 before) or (t(SPI)> tWDTO and WD_dis = 0). The second case corresponds to loss of SPI communication, which is detailed in the next section. Watchdog on SPI Communication and Fail-safe Mode When VDD is present, the SPI watchdog timer is started upon a rising edge on the RSTB pin. Thereafter, the device monitors the state of the first bit (WDIN) of all received SPI words. When the state of this bit is not alternated at least once within a data stream of duration tWDTO = 310 ms typ., the device considers the SPI communication has been lost and enters Fail-safe mode. This behavior can be disabled by setting the bit WD_DIS = 1. The value of watchdog timeout is derived from an internal oscillator. 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES Returning from Fail-safe to Normal mode Entering Fault Mode from Fail-safe Mode To exit Fail-safe mode and return to normal mode again, first a SPI data word with its WDIN bit = 1 (D15) must be received by the device (regardless the register it is contained in, and regardless of the values of the other bits in this register). Next, a second data word must be received within the timeout period (tWDTO = 310 ms typ.), to be able to change any SPI register contents. Upon entering Normal mode, the FSOB pin returns to logic high and previously set faults and SPI registers are reset, except bits POR, PARALLEL and fault bits of latchable faults that had actually been latched. When a Fault occurs in Fail-safe mode, the device is in Fault/Fail-safe mode and behaves according to the description of fault mode. However, SPI registers remain reset and can not be accessed. Only the Direct inputs control the channels. FAULT MODE The device enters Fault mode when any of the following faults occurs in Normal or Fail-safe mode: * Overtemperature fault, (latchable fault) * Overcurrent fault, (latchable fault) * Severe short-circuit fault, (latchable fault) * Output shorted to VPWR in OFF state (default: disabled) * OpenLoad fault in OFF state (default: disabled) * OpenLoad fault in ON state (default: disabled) * External clock failure (default: enabled) * Overvoltage fault (enabled by default) * Undervoltage fault, (latchable fault) The Fault Status pin (FSB) asserts a fault occurrence on any channel in real time (active low). Additionally, the assigned fault bit in the STATR_s or FAULTR_s register is set to one. Conversely to the FSB pin, a fault bit remains set until the corresponding register is read, even if the fault has disappeared. These bits can be read via the SO pin. Fault occurrence also results in a turn-off of the incurred channel, except for the following faults: OpenLoad (On and Off state), External Clock Failure and Output(s) shorted to VPWR. Under and overvoltage occurrences cause simultaneous turn-off of both channels. Details on the device's behavior, after the occurrence of one of the above faults can be found in Protection and Diagnostic Features. Fault mode (Operation and Operating Modes) is entered when: * * * * VPWR (+VDD) were within the normal voltage range, and wake-up = 1, and fail-safe = X, and fault = 1 (see Going from Normal to Fail-safe, Fault or Sleep Mode) Resetting FAULT bits Registers STATR_s and FAULTR_s contain global and channel-specific fault information. Reading the register the fault bit is contained in, clears it, provided a failure cause disappearance has been detected and the fault wasn't latched. Returning from Fault Mode to Fail-safe Mode When disappearance of the fault previously produced in Fail-safe mode has been detected, the device returns to Failsafe mode and behaves accordingly. FSB goes high, but the auto-retry counter is not reset. Latched faults are not delatched. SPI registers remain reset. LATCHABLE FAULTS An auto-retry function (see Auto-retry) controls how the device responds to the so-called latchable faults. Latchable faults are: overcurrent (OC), severe short-circuit (SC), overtemperature (OT), and undervoltage (UV). If a latchable fault occurs, the channel is turned off, the FSB pin goes low, and the assigned fault bit is set. These bits can not be reset before the next turn-on event is generated by auto-retry. Next, the channel is automatically turned on at a programmable interval, provided auto-retry was enabled and the channel wasn't latched. If the failure disappears prior to the expiration of the available number of auto-retries, the FSB pin automatically returns to logic [1], but the fault bit remains set. It can still be reset by reading out the SPI register in which it is contained. However, the fault actually gets latched if the failure cause hasn't disappeared at the first turn-on event following expiration of the available amount of auto-retries (see Autoretry). In that case, the channel gets latched and the FSB pin remains low. The fault bit can only be reset by reading out the associated SPI register, after having performed a delatch sequence (Fault Delatching). Fault Delatching To delatch a latched channel and be able to turn it on again, a delatch sequence must execute after the disappearance of the failure cause. Delatching also allows to reset the fault bit of latched faults (see Resetting FAULT bits). To reset the FSB pin, both channels must be delatched. Delatching is achieved by either alternating the state of the channels' fault control signal fc[x] (generating a 1_0_1 sequence), or by resetting the auto-retry counter (provided retry is enabled). (See Reset of the Auto-retry Counter) Delatching then actually occurs at the rising edge of the turnon event. Signal fc[x] is an internal signal used by the device's internal logic circuitry to control the diagnostic functions. The value of fc[x] depends on the state of the variables IN_ON[x], DIR_dis[x] and ON[x] and is expressed as follows: fc[x] = ((IN_ON[x] and DIR_dis[x] = 0) or ON[x] = 1) Alternating the fc[x] signal is achieved differently according to the way the user controls the device. 10XS4200 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES * In direct-input controlled mode (DIR_dis_s = 0), the IN[x] pin must be set low, remain low for at least tIN seconds, and set high again (be switched On). This might happen automatically when operating at frequencies, f<4.0 Hz. * In SPI-controlled mode, the ON_bit state (D8 of the PWMR_s reg.) must be alternated (`toggled'). No minimum OFF state duration is required in this case. Performing a delatch sequence anytime during an ongoing auto-retry sequence (before latching) allows turning the channel on unconditionally. When a Power-ON event occurs (see Loss of VPWR, Loss of VDD and Power-on-Reset (POR)), latched channels are also delatched and faults are reset. When Fail-safe mode is entered (fault=1, fail-safe becomes 1) during operating in Fault mode (fault=1, failsafe=0), previously latched faults are delatched and SPI register content is reset (except bits POR & PARALLEL). The device is then in a combined Fail-safe/Fault mode. When the device was already in Fail-safe mode (fault=1, failsafe=1) and (new) faults occurs, the internal auto-retry counter is not reset and latched channels are not delatched until a delatching sequence has been performed (see Protection and Diagnostic Features). PROGRAMMABLE PWM MODULE Each channel has a fully independent PWM module activated by setting PWM_en_s. It modulates an internal or external clock signal. Setting Clock_int_s = 1 (bit D6 of the OCR_s register) activates the internal clock, and setting Clock_int_s = 0 activates the external clock. The duty cycle can be set in a range from 0 to 100% with 8 bit-resolution (Table 7) by setting bits D8...D0 of the PWMR_s register (Table 12). The channel's switching frequency equals the clock frequency divided by 256 in internal clock mode, and by 256 or 512 in external clock mode. Table 7. PWM Duty Cycle Value Assignment ON-bit Duty Cycle Channel Configuration 0 X OFF 1 00000010 PWM (3/256 duty cycle) 1 n PWM ((n+1)/256 duty cycle) 1 11111111 fully ON By delaying the activation of one channel relative to the other (Table 8), switch-on surges can be delayed, which may improve EMC performance. Switch-On delay can be selected among seven different values (default=0) by setting bits D2...D0 of the CONFR_s register (expressed as a number of ext./int. PWM clock periods). To start the PWM function at a known point in time, the PWM_en_s bit (D8 /D7 of the GCR reg.) must be set to 1 after having set the PWMR_s (duty cycle) and CONFR_s (delay) registers. The best way to optimize EMC is to use an external clock with a staggered switch on delay. Table 8. Switch-on Delay in PWM Mode Delay Bits Switch-On Delay 000 no delay 001 32 PWM clock periods 010 64 PWM clock periods 011 96 PWM clock periods 100 128 PWM clock periods 101 160 PWM clock periods 110 192 PWM clock periods 111 224 PWM clock periods External Clock & Internal PWM (CLOCK_int_s = 0) PR_x CLOCK (1 + PR_x) Internal Oscillator CS CLOCK_fail PWMR_s register CLOCK_sel_x PWM_en_x MUX External Clock Frequency Monitoring 256 VPWR PWM Mode HS_x Driver Block Internal Clock Calibration IN_x Software Configurable Figure 12. Internal and External Clock Operation . Table 7. PWM Duty Cycle Value Assignment ON-bit Duty Cycle Channel Configuration 0 X OFF 1 00000000 PWM (1/256 duty cycle) 1 00000001 PWM (2/256 duty cycle) HSx The channels can be controlled by an external clock signal by setting bit D6 =0 of the OCR_s register (Clock_int_s). Duty cycle values specified in Table 7 apply. When an external clock is used, the value of frequency division (256 when PR[x] = 0) may be doubled by setting the prescaler bit PR[x]) = 1(bit D7 of the OCR_s reg.). This allows driving the channels at different switching frequencies from a single clock signal. Simultaneously setting PWM_en_1=1 and PWM_en_0=1 synchronizes the channels. The clock frequency on the CLOCK pin is monitored when external clock (CLOCK_int_s = 0) and pulse width modulation (PWM_en_s = 1) are both selected. If a clock failure occurs under these conditions (f< fCLOCK(LOW) or f> fCLOCK(HIGH)), the external clock signal is ignored and a fault is detected (FSB =0), CLOCK_fail bit is set (OD2 in the DIAGR register). The state of the ON_s bit in the SPI register then determines the channel's switching state. To return to external clock mode (and reset FSB), the clock-fail bit must be read and the external clock has to be within the authorized range again. 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES Internal Clock & Internal PWM (Clock_int_s bit = 1) 1- Device Configuration in Parallel mode: By using a reference time slot (usually available from an external microcontroller), the period of each of the internal PWM clocks can be changed or calibrated (see Programmable PWM module). Calibration of the default period = 1/fPWM(0) reduces its maximum variation from about +/-30 percent to +/- 10%. The programming procedure is activated by sending a dedicated word to the SI-CALR register (see Table 12). Next, the device sets the new value of the switching period in 2 steps. First it measures the time elapsed between the first falling edge on the CSB pin and the next rising edge on the CSB pin (tCSB). Then it changes the value of the internal clock period accordingly. The actual value of the channel's switching period is obtained by multiplying the internal clock period by 256. There are two ways to configure the On/Off control: SPI control and Direct Input Control. * SPI controlled Parallel mode: The switching configuration is solely defined by the (SI) PWMR_0, CONFR_0, OCR_0, and RETRY_0 registers. As soon as PARALLEL=1, the contents of the corresponding registers in bank 1 is replaced by that of bank 0, except bits D6-D8 of the CONFR_1 register (configuration OpenLoad/ Output short-circuited diagnostics). It is recommended to disable the off-state OpenLoad for the HS1 output (not necessary for 10XS4200B). After setting PARALLEL=1, contents of SO registers in bank 0 are copied to the registers of bank 1 only when new information is written in them. Bits OD3, OD4 and OD5 of both FAULTR_s registers are always reported independently. * Direct Input mode: The IN0 and IN1 pins must be connected externally. tCSB CSB 2- Diagnostics in Parallel Mode: SI SI command ignored tCSB CALR_s Internal clock period of channel s When the duration of the negative CSB pulse is outside a predefined time slot (from t CSB(MIN) to t CSB(MAX)), the calibration event is ignored and the internal clock frequency remains unchanged. If the value (fPWM(0)) has not been previously calibrated, it remains at its default level. Synchronization of both Channels When internal clock signals are used to drive the PWM modules, perfect synchronization over a long time can not be achieved, since both clock signals are independent. However, when the channels are driven by the external clock, perfect synchronization can be achieved by simultaneously setting PWM_en_1=1 and PWM_en_0=1. The best way to optimize EMC is to use an external clock with a staggered switch on delay (see Table 8). PARALLEL OPERATION The channels can be paralleled to drive higher currents. Setting the PARALLEL bit in the GCR register to logic [1] is mandatory in this case. The improved synchronization of both transistors allows an equal current distribution between both channels. In parallel mode, both output pins (HS[x]) must be connected, as well as both IN[x] pins, in case of external control. CONF0 and CONF1 must be set to equal values. The Diagnostics in Parallel mode operate as follows: * OpenLoad in OFF state and - OpenLoad in ON state: The OL_ON and OL_OFF bits of both FAULTR registers independently report failures of the channels according to the settings of bits D7 and D6 of the CONFR_s register. * Current sensing: Refer to the Table 23 for a description of the various current sensing modes. Only the Current sense ratio of bank 0 (D5 of the OCR_0 register) is considered. The corresponding bit in the OCR_1 register is copied from that of the OCR_0 register. * Output shorted to battery: The OS-bit (OD3) of each of both FAULT registers independently report this fault, according to the settings of bit D8 of the CONFR_s reg. 3- Protections in Parallel Mode: * Overcurrent: -Only the Configuration of overcurrent thresholds & blanking windows of channel 0 are considered. -In case overcurrent (OC) occurs on any channel, both channels are turned-off. Regardless the order of occurrence of OC, both OC-bits (OD0) in the FAULT registers are simultaneously set to logic 1. * Severe short-circuit: In case of SC detection on any channel, both channels are turned-off and the SC bits (OD1) in both FAULT registers are simultaneously set to logic 1. * Overtemperature: In case of OT detection on any channel, both channels are turned-off and both OT bits in the FAULT registers (OD2) are simultaneously set to logic 1. * auto-retry: 10XS4200 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES Only one 4-bit auto-retry counter specifies the number of successive turn-on events on paralleled channels (RETRYR_0). The counter value in register RETRYR_1 (OD4...OD7) is copied from that in RETRYR_0. To delatch the channels, only channel 0 needs to be delatched. PROTECTION AND DIAGNOSTIC FEATURES PROTECTIVE FUNCTIONS done by connecting a resistor with the appropriate value between the CONF0 (or CONF1) pin and GND (Table 9). Overtemperature Fault (latchable fault) The channels have individual overtemperature detection. As soon as a channel's junction temperature rises above TSD (175 C typ.), it is turned OFF, the overtemperature bit (OT = OD2) is set, and FSB = 0. FSB can only be reset by turning ON the channel when the junction temperature of both channels has dropped below the threshold: TJ 50 kOhm or VIH (2.0 V)< V(CONF) < 5.0 V inductive: CONF = 1, DC motor mode When overcurrent windows are active, current sensing is disabled and the SYNCB pin remains high. This is illustrated by Figure 13. After turn on, the output voltage (second waveform (20 V/div.)) and the output current (first waveform, 12 A/div.) rise immediately, but the current sense voltage (third waveform, 2.0 V/div, 1.0 V = 3.0 A) and its synchronization signal SYNC (fourth waveform, 5.0 V/div.) only become active at the end of the selected overcurrent window (duration tOCM2_L). Overcurrent Fault (latchable fault) When overcurrent (OC) is detected, the channel is immediately turned Off (after t FAULT seconds). The OC-bit is set to 1 and FSB becomes low [0]. Overcurrent is detected anytime the load current crosses an overcurrent threshold or exceeds the window width of the selected overcurrent protection profile. This profile is a stair function with windows the height and width of which are preselected through the SPI port. The maximum allowable value of the load current at a particular moment in time is defined by levels I_OCH and I_OCM and windows tOCM_x and tOCH (programmable by SPI bits). The steady-state overcurrent protection level I_OCL is defined by the settings of the OCL and HOCR bits. Anytime an overcurrent window is active, current sensing is blanked, and SYNC becomes 1. Overcurrent Duration Counter The load current can spend only a defined amount of time in a particular window of the overcurrent profile. If the time in the window exceeds the selected window width (tOCx) or the overcurrent threshold is crossed, the channel is turned off (OC fault), followed by auto-retry, if enabled. An internal overcurrent duration counter is employed for this function. Overcurrent Detection on Resistive and Inductive Loads According to the load type (resistive or inductive), one of two different overcurrent profiles should be selected. This is Figure 13. Current Sense Blanking During Overcurrent Window Activity Activation of the lighting profile is time driven and activation of the DC motor profile is event driven, as explained by the following. In lighting mode, the height of the overcurrent profile is defined by three different thresholds (I_OCH, I_OCM and I_OCL, which stand for the higher, the middle, and the lower overcurrent threshold), as illustrated by Figure 5. This profile has two adjacent windows the width of which is compatible with typical bulb inrush current profiles. The width of the first 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES of these windows is either tOCH1 or tOCH2. The width of the second window is either tOCM1_L or tOCM2_L (see Table 18). The lighting profile is activated at each turn-on event including auto-retry, except in switch mode. In switch mode, the profile is activated only at the first turn-on event, but is not renewed. During the on-period, the load current is continuously compared to the programmed overcurrent profile. The channel is switched Off when a threshold is crossed or a window width is exceeded. In DC motor mode, only one overcurrent window exists, defined by two different current levels, as illustrated by Figure 6. This window is opened anytime the output current exceeds the selected lower overcurrent level (IOCLx). In this case, the allowed overcurrent duration is defined by parameters tOCM1_M, tOCM1, and tOCH2. The selection of the different profiles and values is explained in the section Address A0100 -- Overcurrent protection configuration Register (OCR_s). Auto-retry After Overcurrent Shut Off When auto-retry is activated, OC-latching (Overtemperature Fault (latchable fault)) only occurs after expiration of the available amount of auto-retries (described in Auto-retry). Switch Mode Operation and Overcurrent Duration Switch mode is defined as any device operation with a duty cycle lower than 100% at a frequency above fPWM_EXT (min.) or fPWM_INT (min.). The device may operate in Switch mode in internal/external PWM or in direct input mode. In switch mode, the accumulated time spent by the load current in a particular window segment during On-times of successive switching periods is identified by the aforementioned duration counter, and compared to the active segment width. The associated off-times are excluded by the duration counter. The channel is turned-off when the value of the counter exceeds the window width. In Figure 14, overcurrent detection shutdown is shown in case of switch mode operation with a duty cycle of 50% (solid line) and 100% (fully-on, dashed line). The device is turned off much later in switch mode than in fully-on mode, since the duration counter only counts overcurrent during on-times. Figure 14. Overcurrent Shutdown in PWM Mode (solid line) and Non-PWM Mode (dashed line) Reset of the Duration Counter Reset of the duration counter is achieved by performing a delatch sequence (Fault Delatching). In lighting mode (CONFs = 0), this counter is also reset automatically at each auto-retry (but not in DC motor mode). In DC motor mode, the duration counter is reset either by performing a delatch sequence or (automatically) after occurrence of a new on-period without any overcurrent ([hson[x]=1). Reset then actually occurs at the first turn-off instant following that on-period. In switch mode, the duration counter is not reset by normal PWM activity unless delatching is performed. Severe Short-circuit Fault (latchable fault) When a severe short-circuit (SC) is detected at turn-ON (wiring length LLOAD< LSHORT, Table 4), the channel is shut Off immediately. For wiring lengths above LSHORT, the device is protected from short-circuits by the normal overcurrent protection functions (Overcurrent Fault (latchable fault)). When an SC occurs, FSB goes low (logic [0]), and the SC bit is set, eventually followed by an auto-retry. SC is of the latchable type (see Protection and Diagnostic Features and Fault Delatching). Overvoltage Detection (enabled by default) By default, the supply overvoltage protection (VPWR) is enabled. When overvoltage occurs (VPWR > VPWR(OV)), the device turns OFF both channels simultaneously, the FSB pin is asserted low, and the OV fault bit is set to logic [1]. The channels remain OFF until the supply voltage drops below a threshold voltage VPWR < VPWR(OV) - VPWR(OVHYS). The OV bit can then be reset by reading out the STATR register. The overvoltage protection can be disabled by setting the OV_dis = 1 in the general configuration (GCR) register. In this case, the FSB pin neither asserts a fault occurrence, nor turns the channels off. However, the fault register (OV bit) still reports an overvoltage occurrence (when VPWR > VPWR(OV)) as a warning. When VPWR > VPWR(OV), the value of the on- 10XS4200 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES resistance on both channels (RDS(ON)) still lays within the ranges specified in Table 4. Undervoltage Fault (Latchable Fault) The channels are always turned off when the supply voltage (VPWR) drops below VPWR(UV). FSB drops to logic [0], and the fault register's (common) UV bit is set to [1]. When the undervoltage condition then disappears, two different cases exist: * If the channel's internal control signal hson[x] is off, FSB returns to logic [1], but the UV bit remains set until at least one output is turned on (warning). * If the channel's control signal is on, the channel is only turned on if a delatch or POR sequence is performed prior to the turn on request. The UV bit can then only be reset by reading out the STATR register. Auto-retry (if enabled) starts as soon as the UV condition disappears. Extended Mode Protection (VPWR and the GND) is monitored. When the VPWR-to-GND voltage exceeds the threshold VD_GND(CLAMP), the channel is automatically turned on. The feature is not operational in cases of ground loss. Negative Output Voltage Protection The device tries to limit the undervoltage on the output pins HS[x] when turning off inductive loads. When the output voltage drops below VCL, the channel is switched on automatically. This feature is not guaranteed after a device ground loss. The energy dissipation capabilities of the circuit are defined by the ECL [0:1] parameters. For inductive loads larger than 20 H, it is recommended to employ a freewheeling diode. The three different overvoltage protection circuits are symbolically represented in Figure 15. The values of the clamping diodes are those specified in Table 4. Coupling factor k represents the current ratio between the current in the supply voltage measurement diode (zener) and that injected into the MOSFET's gate to turn it on. In extended mode (6.0 V < VPWR < 8.0 V or 36 V < VPWR < 58 V), the channels are still fault protected, but compliance with the specified protection levels is not guaranteed. The register settings however (including previously detected faults) remain unaltered, provided VDD is within the authorized range. Below 6.0 V, the channels are only protected from overtemperature, and this fault is only reported in the SPI register at the moment VPWR has again risen above VPWR(UV). To allow the outputs to remain ON between 36 V and 58 V, overvoltage detection should be disabled by setting OV_dis = 1 in the GCR reg.). Faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if: * VDD < VDD(FAIL) with VPWR in the normal voltage rang * VDD and VPWR are below the VSUPPLY(POR) voltage threshold * The corresponding SPI register is read after the disappearance of the failure cause (and delatching) . Drain/source Overvoltage protection The device can withstand reverse supply voltages on VPWR down to -28 V. Under these conditions, the outputs are automatically turned ON and the channel's ON resistance (RDS(ON)) is similar to that during regular supply voltages. No additional components are required to protect the VPWR circuit except series resistors (>8.0 k) between the direct inputs IN[0:1] and VPWR in case they are connected to VPWR. The VDD pin needs reverse voltage protection from an externally connected diode (Figure 21). The device tries to limit the Drain-to-Source voltage by turning on the channel whenever VDS exceeds VDS(CLAMP). When a fault occurs (SC, OC, OT, and UV), the device is rapidly switched Off (in t < tFAULT seconds), regardless the value of the selected slew rate. This may induce voltage surges on VPWR and/or the output pin (HS[x]), when connected to an inductive line/load. Turning on the device also dissipates the energy stored in the inductive supply line. This function monitors overvoltage for VPWR > 30 V. Below VPWR < 30 V, the negative output voltage protection protects the device from overvoltage by turning on the channel. The feature remains functional after device ground loss. VPWR K.Iz VDS(CLAMP)-Vth HS[x] DC Vth I2 VD_GND(Clamp) IMEG Load VCL-Vth GND Figure 15. Supply and Output Voltage Protections Reverse Voltage Protection on VPWR Load and system Ground Loss In case of load ground loss, the channel's state does not change, but the device detects an OpenLoad fault. In case of a system GND loss, the channels are turned off. Supply Overvoltage Protection In order to protect the device from excessive voltages on the supply lines, the voltage between the device's supply pins 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 37 FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES Device Ground Loss In the (improbable) case where the device loses all of its three ground connections (pins 14, 17, and 22), the channels' state (On/ Off) depends on several factors: the values of the series resistors connected to the device pins, the voltage of the direct input signals, the device's momentary current consumption (influenced by the SPI settings), and the state of other high side switches on the board, when there are pins in common like FSB, FSOB and SYNC. In the following description, all voltages are referenced to the system (module) GND. When series resistors are used, the channel state can be controlled by entering Fail-safe mode. The channels are turned off automatically when the voltage applied to the IN[x] input(s) through the series resistor(s) is not higher than VDD and be turned on when the IN[x] input(s) are tied to VPWR. Fail-Safe is entered under the following conditions: * all unused pins are tied to the overall system GND connection by resistors > 8.0 k. * any device pin connected to external system components has a series resistors > 8.0 k (except pins VPWR, VDD, HS[0], HS[1] and R(CSNS)>2.0 k) * FSB, FSOB, and SYNC pins are in the logic high state when they are shared with other devices. This means none of the other devices are in Fault- or Fail-safe mode, nor should current sensing be performed on any one of them when GND is lost When no series resistors are employed, the channel state after GND loss is determined by the voltage on pins IN[0:1] and the voltage shift of the device GND. Device GND shift is determined by the lowest value of the external voltage applied to either pin of the following list: CLOCK, FSB, IN[0:1], FSOB, SCLK, CS,SI, SO, RSTB, CONF[0:1], SYNC, and CSNS. When the device GND voltage becomes a logic low (V(GND)< VIL), the SPI port continues to operate and the device operates normally. When the GND voltage becomes logic high (V(GND)> VIH), SPI communication is lost and Failsafe mode is entered. When the voltage applied to the IN[0:1] input is VPWR, the channel is turned on when it is VDD, the channel is turned off if (VDD - V(GND)) < VIH. SUPPLY VOLTAGES OUT OF RANGE VDD Out of Range If the external VDD supply voltage is lost (or falls outside the authorized range: VDD VPWR (POR), after a period VPWR < VPWR (POR) (and VDD < VDD (POR) before and after) * VDD > VDD (POR) after a period with VDD < VDD (POR) (VPWR < VPWR (POR) before and after) POR is also set at the transition to wake-up (by setting RSTB =1 or IN[x]=1) when VPWR > VPWR (POR) (before and after) or VDD >VDD(POR) (before and after). POR is not performed when VPWR > VPWR (POR) after a period VPWR < VPWR (POR) (and VDD > VDD (POR) permanently). 10XS4200 38 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES (fc[x] = 0) (OpenLoadOFF = 1 or OS = 1 or OV = 1) OFF (fc[x] = 1 and (OV = 0)) (OpenLoadOFF = 1 or OS = 1 or OV = 1) (OpenLoadON = 1) ON (fc[x]= 0 or OV = 1) Latched OFF (count = 16) (Retry = 1) (fc[x] = 0) Auto-retry Loop (after Retry Period and OV = 0 and OT = 0 and UV = 0) (OV = 1) OFF (OpenloadOFF = 1 or OS = 1 or OV = 1 or UV = 1 or OT = 1) (fc[x] = 0) (OpenLoadON = 1) ON (Retry = 1) = > count = count+1 Figure 16. State Machine: Fault Occurrence and Auto-retry AUTO-RETRY The auto-retry circuitry automatically tries to turn on the channel on a cyclic basis. Only faults of the latchable type (overcurrent, severe short-circuit, overtemperature (OT), and undervoltage (UV)) may activate auto-retry. For UV and OT faults, auto-retry only starts after disappearance of the failure cause when auto-retry is enabled. The retry condition is expressed by: Retry[x] = OC[x] or SC[x] or OT[x] or UV. If Auto-retry has been enabled, its mode of operation depends on the settings of the auto-retry related bits (bits D0...D3 of the SI-RETRY_s register, see Table 13) and the available amount of auto-retries (bits OD7...OD4 of the SORETRY_s reg.). More details can be found in Number Of Auto-retries. If Auto-retry is disabled, latchable faults are automatically latched upon their occurrence (see Protection and Diagnostic Features). Auto-retry Configuration To enable the auto-retry function, bit retry_s (D0 of the SI RETRY_s register) has to be set to the appropriate value. Auto-retry is enabled for retry_s = 0 when the channel is configured for lighting applications (CONF=0). It is enabled for retry_s=1 for DC motor applications (CONF[x] =1). Table 10. Auto-Retry Activation for Lamps (CONF=0) and DC Motors (CONF=1) CONF[x] Retry_s bit auto-retry 0 0 enabled 0 1 disabled 1 0 disabled 1 1 enabled If auto-retry is enabled, an auto-retry sequence starts when the channel's fault control signal is set to 1 (fc[x] = 1, Fault Delatching) and the retry condition applies (Retry[x]=1. See Auto-retry). When a failure occurs (fault = 1), the channel are automatically switched on again after the auto-retry period. The value of this period (tAUTO) is set through the SPI port bits (D2 and D3 of the RETRY_s register, see Table 22). When the failure cause disappears before expiration of the available amount of auto-retries, the device behaves normally (FSB = 1), but the fault bit remains set until it is cleared. This guarantees a maximum device availability without preventing fault detection. Number Of Auto-retries In case the device is configured for an unlimited amount of auto-retries (Retry-unlimited_s = 1), auto-retry continues as long as the device remains powered. The channel is never latched off. 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 39 FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES In case a limited amount of retries is selected (Retryunlimited_s = 0), auto-retry continues as long as the value of the 4-bit auto-retry counter does not exceed 15 (bits OD4...OD7 of the RETRY_s register). After 15 retries, the Rfull bit of the STATR (OD4 for channel 0, OD5 for channel 1) register is set to a logic high. The amount of available autoretries is then reduced to one. If the fault still hasn't disappeared at the next retry, the corresponding channel is switched off definitively and the fault is latched (FSB = 0). See Protection and Diagnostic Features and Fault Delatching. Any channel can be turned on at any moment during the auto-retry cycle by performing a delatch sequence. However, this does not reset the retry counter. The value of the auto-retry counter can be read back in Normal mode (SO-RETRY register bits OD7-OD4). Reset of the Auto-retry Counter The counter of the amount of retries is reset when: Fail-safe is entered (Fail-safe Mode) Sleep mode is left (Sleep Mode) POR occurs (Supply Voltages Out of Range) the retry function is set to unlimited (bit Retryunlimited_s = 1 (D1 = 1)) * the retry function is disabled (retry_s bit = D0 of the RETRY_s register under goes a 1-0 sequence for CONF = 1 and a 0-1 sequence for CONF = 0). If the channel is latched at the moment the auto-retry counter is reset (case 4), the channel is delatched, and turned on after one retry period (if retry was enabled). * * * * Auto-retry and Overcurrent Duration During the on-period following each auto-retry, the load current profile is compared to the length and height of the selected overcurrent threshold profile, as described in the section on overcurrent protection. See Overcurrent Fault (latchable fault). When the lighting profile is activated, the overcurrent duration counter is reset at each auto-retry (to allow sustaining new inrush currents). For DC motor mode however, it is only reset at the turn-off event of the first PWM period without any overcurrent (see Reset of the Duration Counter) Figure 16 gives a description of the retry state machine with the various transitions between operating modes. DIAGNOSTIC FEATURES Diagnostic functions OpenLoad in On state (OLON), OpenLoad in Off state (OLOFF) and output short-circuited to VPWR (OS) are operational over the frequency and duty cycle ranges specified in Table 5 for PWM mode, but the precise values also depend on the way the device is controlled (direct/internal PWM), on the current sense ratio and on the optional activation of the OpenLoad in On state detection. As an example, in direct input (DIR_DIS_S = 0), Low-Current mode (CSR1), OLON, OLOFF, and OS detection are performed for duty cycle values up to: RPWM_400_h = 85% (instead of 90%) when OpenLoad in On state detection is enabled (OLON_dis=0). Output Shorted to VPWR Fault The device detects short-circuits between the output and VPWR. The detection is performed during the Off-state. The output-shorted to VPWR fault-bit (OS_s) is set whenever the output voltage rises above VOSD(THRES). The fault is reported in real time on the FSB pin and saved by the OS_s bit. Occurrence of this fault does not trigger automatic turn-off. Even if the short-circuit disappears, the OS_s bit is not cleared until the FAULTR register is read. The function may be disabled by setting OS_dis_s=1. The function operates over the duty cycle ranges specified in Diagnostic Features. This type of event shall be limited to 1000 min. during the vehicle lifetime. In case of permanent output shorted to the battery condition, it is needed to turn-on the corresponding channel. OpenLoad Detection In Off State OpenLoad in OFF state detection (OL_OFF) is performed continuously during each OFF state (both for CSR0 and CSR1). This function is implemented by injecting a small current into the load (IOLD(OFF)). When the load is disconnected, the output voltage rises above VOLD(THRES). OL_OFF is then detected and the OL_OFF bit in the FAULTR register is set. If disappearance of the open load fault is detected, the FSB output pin returns to a high immediately, but the OL_OFF bit in the fault register remains set until it is cleared by a read out of the FAULTR register. The function may be disabled by setting OLOFF_dis_s=1. The function operates over the duty cycle ranges specified in section Diagnostic Features. OpenLoad Detection In On State (OL_ON) OpenLoad in ON state detection (OLON) is performed continuously during the On state for CSR0 over the ranges specified in section Diagnostic Features. An OpenLoad in On state fault is detected when the load current is lower than the OpenLoad current threshold IOLD(ON). This happens at IOLD(ON) = 300 mA (typ.) for high-current sense mode (CSR0), and at 7.0 mA (typ.) for low-current mode. FSB is asserted low and the OLON bit in the fault register is set to 1, but the channel remains On. FSB goes high as soon as the disappearance of the failure cause is detected, but the OL_ON bit remains set. In high current mode (CSR0), OpenLoad in On state detection is done continuously during the On state and the OLON-bit remains set even if the fault disappears. In high current mode, the OLON-bit is cleared when the FAULTR register is read during the Off state, even if the fault hasn't disappeared. The OLON bit is also cleared when the FAULTR register is read during the ON state, provided the failure cause (load disconnected) has disappeared. 10XS4200 40 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES In low current mode (CSR1), OL_ON is done periodically instead of continuously, and only operates when fast slew rate is selected. When the internal PWM module is used with an internal or external clock (case 1), the period is 150 ms (typ.). When the direct inputs are used (case 2), the period is that of the input signal. The detection instants in both cases are given by the following: 1. In internal PWM (int./ext. clock), low current mode (CSR1), OpenLoad in ON state detection is not performed each switching period, but at a fixed frequency of about 7.0 Hz (each tOLLED =150 ms typ.). The function is available for a duty cycle of 100%. OLON detection is also performed at 7.0 Hz, at the first turn-off event occurring 150 ms after the previous OL_ON detection event (before OS and OL_OFF). 2. In direct input, low current mode (CSR1), OL_ON is performed each switching period (at the turn-off instant) but the duty cycle is restricted to the values. Consequently, when the signal on the IN[x] pin has a duty cycle of 100%, OL_ON is not performed. To solve this problem, either the internal PWM function must be activated with a duty cycle of 100%, or the channel's direct input must be disabled by setting Dir_dis_s=1 (bit D5 of the CONFR-s register). The OLON-bit is only reset when the FAULTR register is read after occurrence of an OL_ON detection event without fault presence. Instantaneous and Sampled Current Sensing The device offers two possibilities for load current sensing: instantaneous (synchronous) sensing mode and track & hold mode (see Figure 9). In synchronous mode, the load current is mirrored through the current sense pin (Output Current Monitoring (CSNS)) and is therefore synchronous with it. After turn-off, the current sense pin does not output the channel current. In track & hold mode however, the current sense pin continues to mirror the load current as it was just before turn-off. Synchronous mode is activated by setting the T_H_en bit to 0, and Track & Hold mode by setting the T_H_en bit to 1. Current Sense Ratio Selection The load current is mirrored through the CSNS pin with a sense ratio (Figure 17) selected by the CSNS_ratio bit in the OCR register. To achieve optimal accuracy at low current levels, the lower current sensing ratio, called CSR1, can be selected. In that case, the overcurrent threshold levels are decreased. The best accuracy that can be obtained for both ratios is shown in Figure 18. The amount of current the CSNS pin can sink is limited to ICSNS,MAX..The CSNS pin must be connected to a pull-down resistor (470 < R(CSNS) <10 k, 1.0 k typical), in order to generate a voltage output. A small low-pass filter can be used for filtering out switching transients (Figure 21). Current sensing operates for load currents up to the lower overcurrent threshold (OCLx A). OpenLoad Detection in Discontinuous Conduction Mode Synchronous Current Sensing Mode If small inductive loads (solenoids / DC motors) are driven at low frequencies, discontinuous conduction mode may occur. Undesired OpenLoad in On state errors may then be detected, as the inductor current needs some time to rise above the OpenLoad detection threshold after turn-on. This problem can be solved by increasing the switching frequency, or by disabling the function and activating OpenLoad in Off state detection instead. When small DC motors are driven in discontinuous conduction mode, undesired OpenLoad in Off state detection may also occur when the load current reaches 0 A during the Off state. This problem can be solved by increasing the switching frequency, or by enabling OpenLoad in the Off state detection only during a limited time, preferably directly after turn-off (see Diagnostic Features). The signal on the SYNC pin can be used to identify the turn-off instant. For activation of synchronous mode, T_H_en must be set to 0 (default). After turn-on, the CSNS output current accurately reflects the value of the channel's load current after the required settling time. From this moment on (CSNS valid), the SYNC pin goes low and remain low until a switch off signal (internal/external) is received. This allows synchronization of the device's current sensing feature with an external process running on a separate device (see Current Sense Synchronization (SYNC)). After turn-off, the load current does not flow through the switch, and the load current cannot be monitored. CURRENT & TEMPERATURE SENSING The scaled values of either of the output currents or the temperature of the device's GND pin (#14) can be made available at the CSNS pin. To monitor the current of a particular channel or the general device temperature, the CSNS0_en and CSNS1_en bits (see Table 23) in the general configuration register (GCR) must be set to the appropriate values. When overcurrent windows are active, current sensing is disabled and the SYNCB pin remains high. Track & Hold Current Sensing Mode In Track & Hold mode (T&H) (T_H_en = 1), conversely from synchronous mode, the CSNS output current is available even after having switched off the load. This feature is useful when the device operates autonomously (internal clock/PWM), since it allows current monitoring without any synchronization of the device. An external sample and hold (S/H) capacitor is not required. After turn on, the CSNS output current reflects the channel's load current with the specified accuracy, after occurrence of the negative edge on the SYNC pin, as in synchronous mode (see Current Sense Synchronization (SYNC)). However, at the switch-off instant, the last observed CSNS current is sampled and its value saved, thanks to an internal S/H capacitor. The SYNC pin goes high (SYNC = 1). If the channel on which Track & Hold current sensing is performed is changed to another, the 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 41 FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES internal S/H hold capacitor is first emptied and then charged again to allow current monitoring of the other channel. Consequently, T&H current monitoring of a channel is lost when this channel is in the Off state at the moment the current is monitored on the other channel. Track & Hold mode should not be used for frequencies below 60 Hz. ICSNS1=CSRx *(ILOAD+ I_LOAD_ERR_SYS + I_LOAD_ERR_RAND) (2) When bit OFP is set to 0, ICSNS can be described by: ICSNS2 = CSRx *(ILOAD+ I_LOAD_ERR_SYS - I_LOAD_ERR_RAND) (3) The random offset term I_LOAD_ERR_RAND can be computed from equations (2) and (3) as follows: . 4000 I_LOAD_ERR_RAND 1/C S R 0 3500 Current Sensing Ratio current sunk through the CSNS pin (ICSNS) can be described by: 3000 = (ICSNS1 - ICSNS2) / (2*CSRx) (4) The compensated current sense value ICSNS,COMP can be obtained by computing the average value of measurements ICSNS1 and ICSNS2 as follows: 2500 2000 ICSNS, COMP = (ICSNS1 + ICSNS2) / 2 1500 (5) 1/C S R 1 1000 When equations 2 and 3 are substituted in equation 5, the random offset error cancels out, as shows eq. 6: 500 0 0 2 4 6 8 10 ICSNS, COMP = (I_LOAD_ERR_SYS + ILOAD) * CSRx (6) O u tp u t C u r r e n t (A ) Figure 17. Current Sensing Ratio Versus Output Current Current Sense Errors Current sense accuracy is adversely affected by errors of the internal circuitry's current sense ratio and offset. The value of the current sensing output current can be expressed with sufficient accuracy by the following equation: ICSNS = (I(HS[x])+ I_LOAD_ERR_SYS + I_LOAD_Err_RAND)*CSRx with CSR0 = (1/3000+GAIN0) and CSR1 = (1/1000+GAIN1). The systematic offset error I_LOAD_ERR_SYS is referenced at the operating point 28 V and 25 C. It can eventually be fine tuned by performing a calibration. Gain errors at 25 C (=current sense ratio errors, represented by gain0 and gain1) can also be reduced by performing a calibration at a point in the range of interest. If calibration can not be done, it is recommended to use the typical value of I_LOAD_ERR_SYS (see Systematic offset error (see Current Sense Errors)). (1) Current Sense Error Model The device's offset error has a "systematic" and a "random" component (I_LOAD_ERR_SYS, I_LOAD_ERR_RAND). At low current levels, the random offset error may become dominant. The systematic offset error is caused by predictable variations with supply voltage and temperature, and has a small but positive value with small spread. The random offset error is a randomly distributed parameter with an average value of zero, but with high spread. The random offset error is subject to part to part variations and also depends on the values of supply voltage and device temperature. The device has a special feature called offset compensation, allowing an almost complete compensation of the random offset error (see ESR0_ERR). This offset compensation technique greatly minimizes this error. Computing the compensated current sensing value is illustrated in the next sections. I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS (uncompensated) (10) I(HS[x]) = ICSNS,COMP / CSRx - I_LOAD_ERR_SYS (compensated) (11) Activation and Use of Offset Compensation Offset Compensation in Track & Hold Mode According to the settings of the OFP_s bit (in the RETRYR_s register), opposite values of the random offset error are generated. To compensate the random offset error, two separate measurements with opposite values of the random offset error are required. The measured values must be saved by an external micro-processor. Compensation of the random offset error is achieved by computing the average of both. When a dedicated bit called Offset Positive (OFP = bit D8 of the RETRYR_s register) is set to 1, the In Track & Hold mode, the last observed sense current (ICSNS) is sampled at the switch off instant. This takes into account the currently active settings of the OFP_s offset compensation bit. Changing the value of the OFP bit during the switch's off time produces an identical value of the current sense output. Consequently, to implement the before mentioned offset compensation technique, the channel must have been turned on at least once prior to sensing the output current, with an opposite value of the OFP bit. The figures of uncompensated and compensated current sense accuracy mentioned in Table 4, have been obtained by applying the error model of eq. 7 to the data: ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx (7) ESRx_ERR = (ICSNS1 - ICSNS_MODEL)/ICSNS_MODEL (8) ESRx_ERR(COMP)= (ICSNS, COMP - ICSNS_MODEL)/ICSNS_MODEL (9) The computation has been applied to each of the specified measurement points. Model parameters I_LOAD_ERR_SYS and CSRx have the nominal values, specified on ESR0_ERR. The load current can be computed from this model as: 10XS4200 42 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES System Requirements for Current Monitoring Current monitoring is usually implemented by reading the (RC-filtered) voltage across the pull-down resistor connected between the CSNS pin and GND (Figure 21). Therefore, measurements (1) and (2) must be spaced sufficiently wide apart (e.g. 5 time constants) to get stabilized values, but close enough to be sure that the offset value wasn't changed. The A/D converter of the external micro-controller that is used to read the current sense voltage V(csns) must have sufficient resolution to avoid introducing additional errors. Accuracy with and without Offset Compensation The sensing accuracy for CSR0 and CSR1, obtained before and after offset compensation, is shown in Figure 18 (solid lines = Full Scale accuracy with offset compensation and dotted lines without offset compensation). Figure 19. Track and Hold Current Sense Accuracy Temperature Prewarning Detection . In Normal mode, the temperature prewarning (OTW) bit is set (FAULTR register) when the observed temperature of the GND pin is higher than TOTWAR (pin #14, see Figure 3). The feature is useful when the temperature of the direct surroundings of the device must be monitored. However, the channel isn't switched off. To be able to reset the OTW-bit, the FAULTR register must be read after the moment that temperature T C < TOTWAR. Switching State Monitoring Figure 18. Current Sense Accuracy Versus Output Current In Track & Hold mode, the accuracy of the current sense function is lowered according to the values shown in Figure 19 (error percentage as a function of the switch-off time is displayed, for CSR0 and CSR1). Track & Hold mode shouldn't be used below f= 60 Hz. The switching state (On/Off) of the channels is reported in real time by bits OUT[x] in the STATR register (bit OD0/OD1). The Out[x] bit is asserted logic high when the channel is on (output voltage V(HS[x]) higher than VPWR /2). When supply voltage VPWR drops below 13 V, the reported channel state may not correspond to the state of the channel's control signal hson[x], in case of an open load fault (see Factors Determining the Channel's Switching State). EMC PERFORMANCES Specified EMC performance is board and module dependent, and applies to a typical application (Figure 21). The device withstands transients per ISO 7637-2 /24 V. An external freewheeling diode connected to at least one output is required for sustaining ISO 7637 Pulse 1 (600 V). To withstand Pulse 2, at least one of the 2 channels must be connected to a typical load (bulb). It withstands electric fields up to 200 V/m and bulk current injection (BCI) up to 200 mA per ISO11452. 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 43 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND SPI REGISTERS LOGIC COMMANDS AND SPI REGISTERS SPI PROTOCOL DESCRIPTION or 3.3 V CMOS logic levels. Parity check is performed after transfer of each 16-bit SPI data word.The SPI interface can be driven without series resistors provided that voltage ratings on VDD and SPI pins (Table 3) aren't exceeded. Unused SPI-pins must be tied to GND, eventually by resistors (see Device Ground Loss). The SPI interface offers full duplex, synchronous data transfer over four I/O lines: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CSB).The SI / SO pins of the device follow a first-in first-out (D15 to D0) protocol. Transfer of input and output words starts with the most significant bit (MSB). All inputs are compatible with 5.0 CSB SCLK SI SO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 Notes 1. RSTB must be in a logic [1] state during data transfer. 2. Data enter the SI pin starting with D15 (MSB) and ending with bit D0. 3. Data are available on the SO pin starting with bit 0D15 (MSB) and ending with bit 0 (OD0). Figure 20. 16-Bit SPI Interface Timing Diagram SERIAL INPUT COMMUNICATION PROTOCOL SPI communication requires that RSTB = high. SPI communication is accomplished with 16-bit messages. A valid message must start with the MSB (D15) and end with the LSB (D0) (Table 22). Incoming messages are interpreted according to Table 12. The MSB, D15, is the watchdog bit (WDIN). Bit D14, Parity check (P), must be set such that the total number of 1-bits in the SPI word is even (P=0 for an even number of 1-bits and P=1 for an odd number). Bank selection is done by setting bit D13. Bits D12: D10 are used for register addressing. The remaining ten bits, D9 : D0, are used to configure the device and activate diagnostic and protective functions. Multiple messages can be transmitted for applications with daisy chaining (or to validate already transmitted data) by keeping the CSB pin at logic 0. Messages with a length different from a multiple of 16 or with a parity error are ignored. The device has thirteen input registers for device configuration and thirteen output registers containing the fault/device status and settings. Table 12 gives the SI register function assignment. Bit names with extension "_s" refer to functions that have been implemented independently for each of both channels. SERIAL PORT OPERATION (MSB-first) at the serial clock frequency (SLCK). Bits at the SI pin are clocked in at the same time. The first sixteen SO register bits are those addressed by the previous SI word (bit D13, D2...D0 of the STATR_s input register). At the end of the chip select event (0-to-1 transition), the SI register contents are latched. The second SPI word clocked out of the Serial Output (SO) after the first CSB event represents the initial SO register contents. This allows daisy chaining and data integrity verification. The message length is validated at the end of the CSB event (0-to-1 transition). If it is valid (multiples of 16, no parity error), the data is latched into the selected register. After latch-in, the SO pin is tri-stated and the status register is updated with the latest fault status information. Daisy Chain Operation Daisy-chaining propagates commands through devices connected in series. The commands enter the device at the SI pin and leave it by the SO pin, delayed by one command cycle of 16 bits. To address a particular device in a daisy chain, the CSB pin of all the devices in that chain has to be kept low until the SPI message has arrived at its destination. Once the command has been clocked in by the addressed device, it can be executed by setting CSB =1. When Chip Select occurs (1-to-0 transition on the CSB pin), the output register data is clocked out of the SO pin 10XS4200 44 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND SPI REGISTERS Table 11. SI Message Bit Assignment Bit n SI Reg. Bit MSB D15 Watchdog in (WDIN): Its state must be alternated at least once within the timeout period . D14 Parity (P) check. P-bit must be set to 0 for an even number of 1-bits and to 1 for an odd number. D13 Selection between SI registers from bank 0 (0= channel 0) and bank 1 (Table 14). . . . D12 : D10 LSB D9:D0 Bit Functional Description Register address bits. Used to configure the device and the protective functions and to address the SO registers. Table 12. Serial Input register Addresses and Function Assignment SI Data SI Register D 15 D D D D D D9 14 13 12 11 10 D8 D7 D6 D5 D4 D3 D2 D1 D0 STATR_s WDIN P A0 0 0 0 0 0 0 0 0 0 0 SOA2 SOA1 SOA0 PWMR_s WDIN P A0 0 0 1 0 ON_s PWM7_s PWM6_s PWM5_s PWM4_ s PWM3_s PWM2_s PWM1_s PWM0_s CONFR_s WDIN P A0 0 1 0 0 OS_dis_s OLON_dis OLOFF_dis DIR_dis_s _s _s SR1_s SR0_s DELAY2_s WDIN P A0 1 0 0 0 HOCR_s PR_s tOCH_s tOCM_s OCH_s RETRY_s WDIN P A0 1 0 1 0 OFP_s 0 OCR_s Clock_int_s CSNS_rati o_s 0 PWM_en PWM_en_ PARALLEL _1 0 DELAY1_s DELAY0_ s OCM_s OCL_s Auto_period Auto_period 1_s 0_s Retry_unli mited_s retry_s 0 (49) T_H_en WD_dis VDD_FAIL_en CSNS1_en CSNS0_en OV_dis GCR WDIN P 0 1 1 0 0 CALR_s WDIN P A0 1 1 1 0 1 0 1 0 1 1 0 1 1 contents after reset* 0 X 0 X X X 0 0 0 0** 0 0 0 0 0 0 * = RSTB = 0 or VDD(FAIL) after VDD = 5.0 V or POR ** = except bit D6 (PARALLEL) of the GCR register that is saved when VDD(FAIL) occurs, provided VDD = 5.0 V and VDD_FAIL_EN = 1 before X = register address, P = parity bit Notes 49. Bit D4 of RETRY_s Serial Input register MC10XS4200FK = 0 MC10XS4200BFK and MC10XS4200BAFK= CONF_SPI_s Setting bit D4 to 0 (CONF_SPI_s=0) will configure the overcurrent profile as the CONF pin . Setting bit D4 to 1 (CONF_SPI_s=1) will configure the overcurrent profile as the opposite of CONF pin . After device reset, the overcurrent profile is defined by the CONF input pin. The SPI-SO CONF bit reporting shall combine external hardware configuration and SPI setting. 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 45 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND SPI REGISTERS Table 13. Serial Output Register Bit Assignment bits D13, D2, D1, D0 of the Previous STATR SO Returned Data S O A 3 S O A 2 S O A 1 S O OD OD OD OD OD OD O OD8 OD7 A 15 14 13 12 11 10 D9 0 OD6 0 0 0 0 WDI N PF SOA SOA SO 3 2 A1 SO A0 N M FAULTR A0 0 _s 0 1 WDI N PF SOA SOA SO 3 2 A1 SO A0 N OTW M PWMR_ A0 0 s 1 0 WDI N PF SOA SOA SO 3 2 A1 SO A0 N M CONFR_ A0 0 s 1 1 WDI N PF SOA SOA SO 3 2 A1 SO A0 OLO DIR_di SR1_s N OS_ OLOFF N_di s_s M dis_s _dis_s s_s A0 1 0 0 WDI N PF SOA SOA SO 3 2 A1 SO A0 N M HOC Clock_i CSNS_ tOCH_ PR_s R_s nt_s ratio_s s RETRYR A0 1 _s 0 1 WDI N PF SOA SOA SO 3 2 A1 SO A0 N M OFP STATR OCR_s OV OD5 OD4 OD3 OD2 OD1 OD0 UV POR R_FUL R_FUL L1 L0 FAULT1 FAULT0 OUT1 OUT0 0 0 OLON OLOFF _s _s OS_s OT_s SC_s OC_s PWM3_s PWM2_s PWM1_s PWM0_s SR0_s DELAY2_s tOCM_s OCH_s ON_ PWM PWM6 PWM5 PWM4 s 7_s _s _s _s R3 R2 R1 R0 DELAY1_ DELAY0_ s s OCM_s Auto_period Auto_period0 Retry_unli 1_s _s mited_s 0 1 1 0 WDI N PF SOA SOA SO 3 2 A1 SO A0 N PWM PWM PARAL T_H_e WD_di VDD_Fail_e n s n M _en_ _en_ LLEL 1 0 CSNS1_en CSNS0_e n DIAGR(1) 0 1 1 1 WDI N PF SOA SOA SO 3 2 A1 SO A0 N M IN0 CLOCK_fail CAL_fail1 0 0 0 0 0 0 GCR contents N/ N/ N/ N/ after reset or A A A A failure* 0 0 0 CON CON F1 F0 0 0 ID1 ID0 IN1 0** 0*** 0 OCL_s retry_s OV_dis CAL_fail0 0 0 * = RSTB = 0 or VDD(FAIL) after VDD = 5.0 V, or POR ** = except bit D6 (PARALLEL) of the GCR register that is saved when VDD(FAIL) occurs provided VDD = 5.0 V and VDD_Fail_en = 1 before *** = except bit D7 (POR) of the STATR register that is saved when VDD(FAIL) occurs after VDD = 5.0 V and VDD_Fail_en = 1 (fail-safe mode) x = register address, PF = parity Fault 1. DIAGR Serial Output register bits D5 and D6 for product identification will report: MC10XS4200FK and MC10XS4200BFK:00 MC10XS4200BAFK: 10 SI REGISTER ADDRESSING The address in the title of the following sections (A0xxx) refer to bits D[13:10] of the SPI word required to address the associated SI register. Bit A0 = D13 selects between registers of bank 0 and bank 1 (Table 14). The function assignment of register bits D[8:0] is described in the associated section. The "_s" behind a register name indicates that the variable applies to the register contents of both banks. Table 14. Value of bit A0 Required for Addressing Register Banks 0 or 1 Value A0 (D13) Bank 0 0 = channel 0 (default) 1 1 = channel 1 ADDRESS A0000 -- STATUS REGISTER (STATR_S) To read back the contents of any of the 13 SO registers, bits D[13:10] of the channel's SI STATR register must be set to A0000 and bits D[2:0] in the same SPI word to the address of the desired SO register. The SO registers thus addressed 10XS4200 46 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND SPI REGISTERS are: STATR, FAULTR_s, PWMR_s, CONFR_s, OCR_s, RETRY_s, GCR, and DIAGR (Table 13). ADDRESS A0001-- PWM CONTROL REGISTER (PWMR_S) The PWMR_s register contents determines the value of the PWM duty cycle at the output (Table 12), both for internal and external clock signals. Bit D8 must be set to 1 to activate this function. The desired value of duty cycle is obtained by setting Bits D7:D0 to one of the 256 levels as shown in Table 7.To start the PWM function at a known point in time, the PWM_en_s bit (both in the GCR register) must be set to 1. ADDRESS A0010-- CHANNEL CONFIGURATION REGISTER (CONFR_S) The CONFR_s is used to select the appropriate value of slew rate and turn-ON delay. The settings of Bits D[8:6] determine the activation of OpenLoad and short-circuit (to VPWR) detection. Bit D13 ( = A0) of the incoming SPI word determines which of both CONFR registers is addressed (Table 11). Setting bit D8 (OS_dis_s) to logic [1] disables detection of short-circuits between the channel's output pin and the VPWR pin. The default value [0] enables the feature. Setting bit D7 (OLON_dis_s) to logic [1] disables detection of OpenLoad in the On state for the selected channel. The default value [0] enables this feature (Table 15). Setting bit D6 (OLOFF_dis_s) to logic [1] disables detection of OpenLoad in the OFF state. The default value [0] enables the feature, see Table 15. Table 15. Selection of OpenLoad Detection Features OLON_dis_s (D7) OLOFF_dis_s (D6) (in On state) (in Off state) Selected OpenLoad Detection function 0 0 both enabled (default) 0 1 Off state detection disabled 1 0 On state detection disabled 1 1 Both disabled Setting bit D5 (DIR_DIS_s) to logic [0] enables direct control on the selected channel. Setting bit D5 to logic [1] disables direct control. In that case, the channel state is determined by the settings of the internal PWM functions. D4:D3 bits (SR1_s and SR0_s) control the slew rate at switch On and switch Off (Table 16). The default value ([00]) corresponds to the medium slew rate. Rising and falling edge slew rates are identical. Table 16. Slew Rate Selection SR1_s (D4) SR0_s (D3) Slew Rate 0 0 medium (default) 0 1 low 1 0 high 1 1 medium SR TOTWAR). Reading either FAULT register clears both OTW bits. Bits OD5: OD0 of the Fault register (FAULTR_s) report the faults that occurred on the channel previously selected by bit SOA3 = A0 (Table 14). * bit OD0 = OC_s: overcurrent fault on channel s, * bit OD1 = SC_s: severe short-circuit on channel s, * bit OD3 = OS_s: output shorted to VPWR on channel s, * bit OD4 = OLOFF_s: OpenLoad in OFF state on channel s, * bit OD5 = OLON_s: OpenLoad in ON state on channel s. (The threshold value above which this fault is triggered depends on the selected current sense ratio; for CSR0 @ 300 mA typ. and for CSR1 @ 7.0 mA typ.). The Fault Status pin (FSB) is set to 0 (active Low) upon occurrence of any of the above mentioned faults. Latched faults can only be delatched by the procedure described in Fault Delatching. The FAULTR_s register is reset when it is read out, provided that the failure cause has disappeared and latched faults have been delatched. PREVIOUS ADDRESS SOA3 : SOA0 = A0010 (PWMR_S) The device outputs the contents of the addressed PWMR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). PREVIOUS ADDRESS SOA3 : SOA0 = A0011 (CONFR_S) The device outputs the contents of the addressed CONFR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). PREVIOUS ADDRESS SOA3 : SOA0 = A0100 (OCR_S) The device outputs the contents of the addressed OCR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). PREVIOUS ADDRESS SOA3 : SOA0 = A0101 (RETRYR_S) The device outputs the contents of the addressed RETRYR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). Bit OD8 contains the value of the OFP bit (offset positive), used for current sense offset compensation. Bits OD7: OD4 contain the real time value of the auto-retry counter. When these bits contain [0000], either auto-retry has not been enabled or Auto-retry did not occur. PREVIOUS ADDRESS SOA3 : SOA0 = 0110 (GCR) The device outputs the contents of the General Configuration Register (GCR) common to both channels. PREVIOUS ADDRESS SOA3 : SOA0 = 0111 (DIAGR_S) Bit OD8 ( Ch. 1 = CONF1) and bit OD7 ( Ch. 0 = CONF0) of the DIAGR_s register contain the values of the channels' configuration bits (0 = bulb, 1 = DC motor) Bits OD6:OD5 contain the Product Identification (ID) number, equal to 00 for 10XS4200 and 10XS4200B and 10 for 10XS4200BA.. Bits OD4:OD3 report the logic state of the direct inputs IN[1:0] in real time (1 = On, 0 = OFF), OD4 = Ch. 1, OD3 = Ch. 0. Bit OD2 reports a logic [1] in case an external clock error occurred (if an external clock was selected by Clock_int = 0) Bit OD1:OD0 report logic [1] in case a calibration failure occurred during calibration of a channel's internal clock period. 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 51 TYPICAL APPLICATIONS TYPICAL APPLICATIONS Figure 21 shows the electrical circuit of a typical truck application. As an example, an external circuit is added that takes over load control in case Fail-safe mode is activated VPWR (FSOB goes low). This circuit allows keeping full control of both channels in case of SPI failure. VDD Voltage regulator 100 nF 10 F 100 nF 10 F 470 pF speed-up capacitor for SPI frequencies > 4.0 Mhz recommended on pins CS, SCLK, SI, SO VDD VDD VPWR VPWR VDD 10 k 100 nF 10 k VDD I/O 470 pF SCLK CSB I/O SO SI 1.0 k 1.0 k 1.0 k 1.0 k 1.0 k <5.0 k 75 k 1.0 k I/O A/D 22 nF 1.0 k 10 k HS0 10XS4200 FSOB SCLK CSB RSTB SI SO CONF0 CONF1 SYNC CSNS 1.0 k 1.0 F CLOCK FSB IN0 IN1 1.0 k MCU GND 100 nF 1.0 k I/O VPWR VDD 100 k 22 nF LOAD 0 HS1 22 nF M LOAD 1 GND 10 k VPWR External Control Circuitry direct controls (pedals, handles, etc.) Figure 21. Typical Application with Two Different Load Types 10XS4200 52 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS . VPWR VDD Voltage regulator 100 nF 10 F 10 F 100 nF 470 pF speed-up capacitor for SPI frequencies > 4.0 Mhz recommended on pins CS, SCLK, SI, SO VDD VPWR VDD VPWR VDD 10 k 100 nF 10 k VDD I/O 1.0 k FSB IN0 IN1 1.0 k 470 pF SCLK CS I/O SO SI I/O GND 100 nF 1.0 F CLOCK I/O MCU VPWR VDD 100 k 1.0 k 1.0 k 1.9 k 1.0 k 75 k 1.0 k 1.0 k 75 k A/D 1.0 k 22 nF FSOB SCLK CSB RSTB SI SO CONF0 CONF1 SYNC CSNS HS0 22 nF 10XS4200 M LOAD HS1 GND 1.0 k 10 k VPWR External Control Circuitry direct controls (pedals, handles,...) Figure 22. Two Channels in Parallel / Recommended External Current Sense Circuit 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 53 PACKAGING SOLDERING INFORMATION PACKAGING SOLDERING INFORMATION The 10XS4200 is packaged in a surface mount power package (PQFN), intended to be soldered directly on the printed circuit board. The AN2467 provides guidelines for Printed Circuit Board design and assembly. 10XS4200 54 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ASA00428D listed below. Dimensions shown are provided for reference only. FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 55 PACKAGING PACKAGE DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A 10XS4200 56 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 57 PACKAGING PACKAGE DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A 10XS4200 58 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 59 PACKAGING PACKAGE DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A 10XS4200 60 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 61 PACKAGING PACKAGE DIMENSIONS FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A 10XS4200 62 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 4/2012 * Initial release 2.0 6/2012 * * Updated the values in Table 5, Dynamic Electrical Characteristics Updated the values in ESR1_ERR 3.0 4/2013 * * Gramatical accuracy and form consistency changes made. No changes to content. Revised back page. Updated document properties. Added SMARTMOS sentence to first paragraph. 4.0 9/2013 * * * * * Changed ECL value Removed ECL_REP energy values Removed RDSON values at 1.0 A. Rectification of the inversion between tDLY values at slow and medium slew rate. Correction of the resistive loads values in notes 29 and 31 5.0 10/2013 * * Added 10XS4200BFK and 10XS4200BAFK to the ordering information Introduction of parameters related to 10XS4200BFk and 10XS4200BAFK device (Table 1) and in the Electrical tables. 6.0 12/2013 * Inversion of 10XS4200BFK and 10XS4200BAFK tRF_01 values 1.0 10XS4200 Analog Integrated Circuit Device Data Freescale Semiconductor 63 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no on the information in this document. warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. 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