Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Stereo 2.6W Audio Power Amplifier (with DC_Volume Control)
Features
•Low Operating Current with 9mA
•Improved Depop Circuitry to Eliminate Turn-on
and Turn-off Transients in Outputs
•High PSRR
•32 Steps Volume Adjustable by DC Voltage with
Hysteresis
•2.6W per Channel Output Power into 4Ω Load
at 5V, BTL Mode
•Two Output Modes Allowable with BTL and SE
Modes Selected by SE/BTL Pin
•Low Current Consumption in Shutdown Mode
(1µA)
•Short Circuit Protection
•Thermal Shutdown Protection and Over-Current
Protection Circuitry
•The OUT+ Signal and the IN- Signal are Outphase
•Power Enhanced Package (DIP-16 / DIP-16A)
•Lead Free and Green Devices Available
(RoHS Compliant)
Applications
General Description
APA2069 is a monolithic integrated circuit, which pro-
vides precise DC volume control, and a stereo bridged
audio power amplifiers capable of producing 2.6W
(2W) into 4Ω with less than 10% (1.0%) THD+N. The
attenuator range of the volume control in APA2069 is from
20dB (DC_Vol=0V) to -80dB (DC_Vol=3.54V) with 32
steps. The advantage of internal gain setting can be less
components and PCB area. Both of the depop circuitry
and the thermal shutdown protection circuitry are inte-
grated in APA2069, that reduce pops and clicks noise
during power up or shutdown mode operation. It also
improves the power off pop noise and protects the chip
from being destroyed by over temperature and short cur-
rent failure. To simplify the audio system design, APA2069
combines a stereo bridge-tied loads (BTL) mode for
speaker drive and a stereo single-end (SE) mode for head-
phone drive into a single chip, where both modes are
easily switched by the SE/BTL input control pin signal.
•NoteBook PC
•LCD Monitor or TV
Pin Configuration
GND 5
GND 4 13 GND
SE/BTL 8
15 VDD
LIN- 6 12 GND
RIN- 3 14 ROUT+
BYPASS 2 16 ROUT-
11 LOUT+
10 VDD
VOLUME 7
SHUTDOWN 1
9 LOUT-
APA2069
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw2
Ordering and Marking Information
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Symbol
Parameter Rating Unit
VDD Supply Voltage Range -0.3 to 6 V
VIN Input Voltage Range, SE/BTL, SHUTDOWN -0.3 to VDD+0.3 V
TA Operating Ambient Temperature Range -40 to 85 °C
TJ Maximum Junction Temperature 150 °C
TSTG Storage Temperature Range -65 to +150 °C
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C
PD Power Dissipation Internal Limited W
(Over operating free-air temperature range unless otherwise noted.)
Absolute Maximum Ratings (Note 1)
Thermal Characteristics
Symbol
Parameter Typical Value Unit
θJA Thermal Resistance from Junction to Ambient in Free Air (Note 2) DIP-16
/
DIP-
16A
45 °C/W
θJC Thermal Resistance from Junction to Case in Free Air DIP-16
/
DIP-
16A
10 °C/W
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Symbol
Parameter Range Unit
VDD Supply Voltage 4.5 ~ 5.5 V
SHUTDOWN 2.0 ~
VIH High Level Threshold Voltage SE/BTL 4.0 ~ V
SHUTDOWN ~ 1.0
VIL Low Level Threshold Voltage SE/BTL ~ 3.0 V
VICM Common Mode Input Voltage ~ VDD-0.5 V
Recommended Operating Conditions
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
APA2069
Handling Code
Temperature Range
Package Code
Package Code
J : DIP-16 / DIP-16A
Operating Ambient Temperature Range
I : - 40 to 85 oC
Handling Code
TU : Tube
Assembly Material
L : Lead Free Device
G : Halogen and Lead Free Device
APA2069 J :APA2069
XXXXX XXXXX - Date Code
Assembly Material
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw3
APA2069
Symbol Parameter Test Conditions Min.
Typ.
Max.
Unit
SE/BTL=0V - 9 20
IDD Supply Current SE/BTL=5V - 4 10 mA
ISD Supply Current in Shutdown Mode SE/BTL=0V
SHUTDOWN=0V - 1 - µA
IIH High Input Current - 900
- nA
IIL Low Input Current - 900
- nA
VOS Output Offset Voltage - 5 - mV
Operating Characteristics, BTL mode. VDD=5V, TA=25OC, RL=4Ω, AV=6dB (unless otherwise noted)
APA2069
Symbol Parameter Test Conditions Min.
Typ.
Max.
Unit
THD+N=10%, RL=3Ω, fin=1kHz - 2.9 -
THD+N =10%, RL=4Ω, fin=1kHz - 2.6 -
THD+N =10%, RL=8Ω, fin=1kHz - 1.6 -
THD+N =1%, RL=3Ω, fin=1kHz - 2.4 -
THD+N =1%, RL=4Ω, fin=1kHz - 2 -
PO Maximum Output Power
THD+N =0.5%, RL=8Ω, fin=1kHz 1 1.3 -
W
PO=1.2W, RL=4Ω, fin=1kHz - 0.07
-
THD+N Total Harmonic Distortion Plus Noise PO=0.9W, RL=8Ω, fin=1kHz - 0.08
- %
PSRR Power Ripple Rejection Ratio VIN=0.1Vrms, RL=8Ω, CB=1µF, fin=120Hz
- 60 - dB
Crosstalk
Channel Separation CB=1µF, RL=8Ω, fin=1kHz - 90 - dB
S/N Signal to Noise Ratio PO=1.1W, RL=8Ω, A_weighting - 95 - dB
VDD=5V, TA=25°C (unless otherwise noted)
Electrical Characteristics
APA2069
Symbol Parameter Test Conditions Min.
Typ.
Max.
Unit
THD+N=10%, RL=16Ω, fin=1kHz - 220
-
THD+N =10%, RL=32Ω, fin=1kHz - 120
-
THD+N =1%, RL=16Ω, fin=1kHz - 160
-
PO Maximum Output Power
THD+N =1%, RL=32Ω, fin=1kHz - 95 -
mW
PO=125mW, RL=16Ω, fin=1kHz - 0.09
-
THD+N Total Harmonic Distortion Plus Noise PO=65mW, RL=32Ω, fin=1kHz - 0.09
- %
PSRR Power Ripple Rejection Ratio VIN=0.1Vrms, RL=32Ω, CB=1µF, fin=120Hz
- 60 - dB
Crosstalk
Channel Separation CB=1µF, RL=32Ω, fin=1kHz - 60 - dB
S/N Signal to Noise Ratio PO=75mW, SE, RL=32Ω, A_weighting - 100
- dB
Operating Characteristics, SE mode. VDD=5V, TA=25°C, AV=0dB (unless otherwise noted)
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw4
Typical Operating Characteristics
THD+N vs. Output PowerTHD+N vs. Output Power
Output Power (W)Output Power (W)
THD+N(%)
THD+N(%)
0.01
10
0.1
1
03.50.5 11.5 22.5 3
VDD = 5V
AV =20dB
fin= 1kHz
BTL
RL = 8Ω
RL = 4ΩRL = 3Ω
0.01
10
0.1
1
0240m
40m 80m 120m 160m 200m
VDD = 5V
AV =14dB
fin = 1kHz
SE
RL = 32ΩRL = 16Ω
THD+N vs. Output PowerOutput Noise Voltage vs. Frequency
Output Power (W)Output Power (W)
THD+N(%)
THD+N(%)
0.01
10
0.1
1
03.5
0.5 11.5 22.5 3
VDD = 5V
fin =1kHz
RL =3Ω
BTL
AV = 20dB
AV = 6dB
0.05
10
0.1
1
10m
5
100m 1
VDD = 5V
AV =20dB
RL =3Ω
BTL
fin= 20kHz
fin= 20Hz
fin = 1kHz
THD+N vs. Frequency
Frequency (Hz)
THD+N vs. Frequency
Frequency (Hz)
THD+N(%)
THD+N(%)
0.01
10
0.1
1
20 20k100 1k 10k
VDD = 5V
RL =3Ω
PO = 1.8W
BTL
AV = 20dB
AV = 6dB
0.01
10
0.1
1
20 20k100 1k 10k
VDD = 5V
AV = 6dB
RL =3Ω
BTL
PO = 0.9W
PO = 1.8W
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw5
Typical Operating Characteristics (Cont.)
THD+N vs. Output PowerTHD+N vs. Output Power
Output Power (W)Output Power (W)
THD+N(%)
THD+N(%)
0.01
10
0.1
1
03.50.5 11.5 22.5 3
VDD = 5V
fin =1kHz
RL =4Ω
BTL
AV = 20dB
AV = 6dB
THD+N vs. Frequency THD+N vs. Frequency
Frequency (Hz)Frequency (Hz)
THD+N(%)
THD+N(%)
0.01
10
0.1
1
20 20k
100 1k 10k
VDD = 5V
RL=4Ω
PO=1.5W
BTL
AV = 20dB
AV = 6dB
0.01
10
0.1
1
20 20k100 1k 10k
VDD = 5V
AV= 6dB
RL=4Ω
BTL
PO = 0.8W
PO = 1.5W
THD+N vs. Output Power
Output Power (W)
THD+N vs. Output Power
Output Power (W)
THD+N(%)
THD+N(%)
0.01
10
0.1
1
03.50.5 11.5 22.5 3
AV = 20dB
AV = 6dB
VDD = 5V
fin= 1kHz
RL=8Ω
BTL
0.01
10
0.1
1
10m
5
100m 1
fin = 20kHz
fin = 20Hz
fin = 1kHz
VDD = 5V
AV = 20dB
RL=8Ω
BTL
0.01
10
0.1
1
10m
5
100m 1
VDD = 5V
AV =20dB
RL =4Ω
BTL
fin = 20kHz
fin = 20Hz
fin = 1kHz
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw6
Typical Operating Characteristics (Cont.)
THD+N vs. Frequency THD+N vs. Frequency
Frequency (Hz)Frequency (Hz)
THD+N(%)
THD+N(%)
0.01
10
0.1
1
20 20k100 1k 10k
PO = 0.5W
VDD = 5V
AV = 6dB
RL=8Ω
BTL
PO = 0.9W
0.01
10
0.1
1
20 20k
100 1k 10k
AV = 6dB
AV = 20dB
VDD=5V
RL=8Ω
PO=0.9W
BTL
THD+N vs. Output PowerTHD+N vs. Output Power
Output Power (W)Output Power (W)
THD+N(%)
THD+N(%)
0.01
10
0.1
1
0240m40m 80m 120m 160m 200m
VDD=5V
fin=1kHz
RL=16Ω
SE
AV = 0dB
AV = 14dB
0.01
10
0.1
1
10m 300m50m 100m 200m
VDD=5V
AV=14dB
RL=16Ω
CO=1000µf
SE
fin = 20kHz
fin= 1kHz
fin = 20Hz
THD+N vs. Frequency
Frequency (Hz)
THD+N vs. Frequency
Frequency (Hz)
THD+N(%)
THD+N(%)
0.01
10
0.1
20 20k
100 1k 10k
VDD=5V
RL=16Ω
PO=125mW
CO=1000µf
SE
AV = 0dB
1
AV = 14dB
0.01
10
0.1
1
20 20k
100 1k 10k
VDD=5V
AV=0dB
RL=16Ω
CO=1000µf
SE
PO = 125mW
PO = 60mW
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw7
Typical Operating Characteristics (Cont.)
THD+N vs. Output PowerTHD+N vs. Output Power
Output Power (W)Output Power (W)
THD+N(%)
THD+N(%)
0.01
10
0.1
1
0240m40m 80m 120m 160m 200m
VDD=5V
fin=1kHz
RL=32Ω
SE
AV = 0dB
AV = 14dB
0.01
10
0.1
1
10m 300m
50m 100m 200m
VDD=5V
AV=14dB
RL=32Ω
CO=1000µf
SE
fin = 20Hz
fin= 1kHz
fin= 20kHz
THD+N vs. Frequency THD+N vs. Frequency
Frequency (Hz)Frequency (Hz)
THD+N(%)
THD+N(%)
0.01
10
0.1
1
20 20k100 1k 10k
VDD=5V
AV=14dB
RL=32Ω
CO=1000µf
SE
PO = 65mW
PO = 30mW
0.01
10
0.1
1
20 20k100 1k 10k
VDD=5V
RL=32Ω
PO=65mW
CO=1000µf
SE
AV = 0dB
AV = 14dB
Frequency Response
Frequency (Hz)
Frequency Response
Frequency (Hz)
Amplitude(dB)
Amplitude(dB)
Phase(Degrees)
Phase(Degrees)
+160
+330
+170
+180
+190
+300
+310
+320
+0
+20
+4
+8
+12
+16
10 200k100 1k 10k 100k
Gain( 20dB)
Phase( 20dB)
Phase( 6dB)
Gain( 6dB)
VDD=5V
RL=8Ω
PO=0.5W
BTL
+160
+330
+170
+180
+190
+300
+310
+320
+0
+20
+4
+8
+12
+16
10 200k
100 1k 10k 100k
Phase( 6dB)
Gain( 20dB)
Gain( 6dB)
Phase( 20dB)
VDD=5V
RL=4Ω
PO=0.8W
BTL
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw8
Typical Operating Characteristics (Cont.)
Frequency Response Frequency Response
Frequency (Hz)Frequency (Hz)
Amplitude(dB)
Amplitude(dB)
Phase(Degrees)
Phase(Degrees)
+120
+300
+140
+160
+180
+200
+220
+240
+260
+280
-10
+14
-6
-2
+2
+6
+10
20 200k
100 1k 10k 100k
Gain(14dB)
Phase(14dB)
VDD=5V
RL=16Ω
CO=1000µf
PO=60mW
SE
Gain(0dB)
Phase(0dB)
+165
+220
+170
+180
+190
+200
+210
-10
+14
-6
-2
+2
+6
+10
20 200k
100 1k 10k 100k
Gain(14dB)
Gain(0dB)
Phase(14dB)
Phase(0dB)
VDD=5V
RL=32Ω
CO=1000µf
PO=30mW
SE
Crosstalk vs. Frequency Crosstalk vs. Frequency
Frequency (Hz)Frequency (Hz)
Crosstalk(dB)
Crosstalk(dB)
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
Right to Left
Left to Right
VDD=5V
RL=4Ω
PO=1.5 W
BTL
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
VDD=5V
RL=8Ω
PO=0.9 W
BTL
Right to Left
Left to Right
Crosstalk vs. Frequency
Frequency (Hz)
Crosstalk vs. Frequency
Frequency (Hz)
Crosstalk(dB)
Crosstalk(dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
Right to Left
Left to Right
VDD=5V
RL=16Ω
CO=1000µf
PO=125mW
SE
-100
+0
-80
-60
-40
-20
20 20k
100 1k 10k
-10
-30
-50
-70
-90
VDD=5V
RL=32Ω
CO=1000µf
PO=65mW
SE
Right to Left
Left to Right
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw9
Typical Operating Characteristics (Cont.)
Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency
Frequency (Hz)Frequency (Hz)
Output Noise Voltage(V)
Output Noise Voltage(V)
1µ
100µ
10µ
20µ
20 20k100 1k 10k
Filter BW<22kHz
A-Weighting
VDD=5V
AV=0dB
RL=32Ω
SE
1µ
100µ
10µ
20µ
20 20k
100 1k 10k
VDD=5V
AV=6dB
RL=4Ω
BTL
A-Weighting
Filter BW<22kHz
PSRR vs. Frequency PSRR vs. Frequency
Frequency (Hz)Frequency (Hz)
PSRR(dB)
PSRR(dB)
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
100 1k 10k
VDD=5V
RL=4Ω
VIN=200mV
AV=20dB
BTL
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
100 1k 10k
VDD=5V
RL=32Ω
VIN=200mV
AV=14dB
SE
Shutdown Attenuation vs. Frequency
Frequency (Hz)
Gain vs. Volume Voltage
DC Volume(V)
Gain(dB)
Shutdown Attenuation(dB)
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
VDD=5V
RL=8Ω
VIN=1Vrms
AV=6dB
BTL
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Up Down
VDD=5V
No Load
BTL
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw10
Typical Operating Characteristics (Cont.)
Supply Current vs. Supply VoltagePower Dissipation vs. Output Power
Supply Voltage (V)Output Power (W)
Power Dissipation(W)
Supply Current(mA)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.00 0.50 1.00 1.50 2.00 2.50
RL=3Ω
RL=4Ω
RL=8Ω
VDD=5V
THD+N<1%
BTL
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
3.0 3.5 4.0 4.5 5.0 5.5
BTL
SE
No Load
Power Dissipation vs. Output Power
Output Power (W)
Power Dissipation(W)
0
20
40
60
80
100
120
140
160
180
200
0 50 100 150 200 250
RL=8Ω
RL=32Ω
RL=16Ω
VDD=5V
THD+N<1%
SE
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw11
PIN
NO. NAME CONFIG
FUNCTION
1
SHUTDOWN I
It will be into shutdown mode when pull low. ISD = 1µA
2 BYPASS I Bias voltage generator
3 RIN- I Right channel input terminal
4,5,12,13 GND - Ground connection, Connected to thermal pad.
6 LIN- I Left channel input terminal
7 VOLUME I Input signal for internal volume gain setting.
8
SE/BTL
I
Output mode control input, high for SE output mode and low for BTL mode.
9 LOUT- O Left channel negative output in BTL mode and high impedance in SE mode.
10,15 VDD - Supply voltage
11 LOUT+ O Left channel positive output in BTL mode and SE mode.
14 ROUT+ O Right channel positive output in BTL mode and SE mode.
16 ROUT- O Right channel negative output in BTL mode and high impedance in SE mode.
Pin Description
Block Diagram
Shutdown
ckt
Power and Depop
Circuit
SE/BTL
LOUT+
LOUT-
LIN-
SE/BTL
SHUTDOWN
BYPASS
Volume
Control
VOLUME
APA2069_Block
ROUT+
RIN-
BYPASS
ROUT-
GND
VDD
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw12
Typical Application Circuit
4Ω
4ΩRing
Headphone
Jack
Sleeve
Control
Pin
Tip
SE/BTL
Signal
1µF
220µF
220µF
1kΩ
1kΩ
R-Ch
Input
VDD
100k Ω
Shutdown
Signal
1µF
L-CH
Input
VDD
VDD GND
100µF
0.1µF
100k Ω
Shutdown
ckt
SE/BTL
LOUT+
LOUT-
LIN-
SE/BTL
SHUTDOWN
BYPASS
Volume
Control
VOLUME
A2069_AppCkt
ROUT+
RIN-
BYPASS
ROUT-
VDD
50kΩ
2.2 µF
GND
Volume Control Table_BTL Mode
Av(dB) High(V) Low(V) Hysteresis(mV)
Recommended Voltage(V)
20 0.12 0.00 0
18 0.23 0.17 52 0.20
16 0.34 0.28 51 0.31
14 0.46 0.39 50 0.43
12 0.57 0.51 49 0.54
10 0.69 0.62 47 0.65
8 0.80 0.73 46 0.77
6 0.91 0.84 45 0.88
4 1.03 0.96 44 0.99
2 1.14 1.07 43 1.10
0 1.25 1.18 41 1.22
-2 1.37 1.29 40 1.33
-4 1.48 1.41 39 1.44
-6 1.59 1.52 38 1.56
-8 1.71 1.63 37 1.67
Supply Voltage VDD=5V
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw13
Volume Control Table_BTL Mode (Cont.)
Av(dB) High(V) Low(V) Hysteresis(mV)
Recommended Voltage(V)
-10 1.82 1.74 35 1.78
-12 1.93 1.85 34 1.89
-14 2.05 1.97 33 2.01
-16 2.16 2.08 32 2.12
-18 2.28 2.19 30 2.23
-20 2.39 2.30 29 2.35
-22 2.50 2.42 28 2.46
-24 2.62 2.53 27 2.57
-26 2.73 2.64 26 2.69
-28 2.84 2.75 24 2.80
-30 2.96 2.87 23 2.91
-32 3.07 2.98 22 3.02
-34 3.18 3.09 21 3.14
-36 3.30 3.20 20 3.25
-38 3.41 3.32 18 3.36
-40 3.52 3.43 17 3.48
-80 5.00 3.54 16 5
Supply Voltage VDD=5V
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw14
Internal to the APA2069, two separate amplifiers drive
OUT+ and OUT- (see Figure 1). The SE/BTL input con-
trols the operation of the follower amplifier that drives
LOUT- and ROUT-.
• When SE/BTL keeps low, the OP2 turns on and the
APA2069 is in the BTL mode.
• When SE/BTL keeps high, the OP2 is in a high output
impedance state, which configures the APA2069 as SE
driver from OUT+. IDD is reduced by approximately one-
half in the SE mode.
The Control of the SE/BTL input can be a logic-level TTL
source or a resistor divider network or the stereo head-
phone jack with switch pin as shown in the Application
Circuit.
Application Information
Figure 1: APA2069 Internal Configuration
(each channel)
CB x 150kΩ
1≤1
RiCi<< 1
RLCC(1)
BTL Operation
The APA2069 output stage (power amplifier) has two
pairs of operational amplifiers internally, which allows
different amplifier configurations.
The power amplifier’s OP1 gain is set by internal unity-
gain and input audio signal comes from internal vol-
ume control amplifier. While the second amplifier OP2
is internally fixed in a unity-gain, inverting configuration.
Figure 1 shows that the output of OP1 is connected to
the input to OP2, which results in the output signals of
with both amplifiers with identical in magnitude, but out
of phase 180°. Consequently, the differential gain for
each channel is 2 x (Gain of SE mode).
By driving the load differentially through outputs OUT+
and OUT-, an amplifier configuration is commonly referred
to the bridged mode is established. BTL mode operation
is different from the classical single-ended SE amplifier
configuration where one side of its load is connected to
the ground.
A BTL amplifier design has a few distinct advantages over
the SE configuration, as it provides differential drive to the
load, thus, doubles the output swing for aspecified sup-
ply voltage.
When placed under the same conditions, a BTL amplifier
has four times the output power of a SE amplifier. A BTL
configuration, such as the one used in APA2069, also
creates a second advantage over SE amplifiers. Since
the differential outputs, ROUT+, ROUT-, LOUT+, and
LOUT-, are biased at half-supply, it’s not necessary for
DC voltage to be across the load. This eliminates the
Single-Ended Operation
Output SE/BTL Operation
The best cost saving feature of APA2069 is that it can
be switched easily between BTL and SE modes. This
feature eliminates the requirement for an additional
headphone amplifier in applications where internal
stereo speakers are driven in BTL mode but external
headphone or speakers must be accommodated.
Vbias
Circuit
OUT+
OUT-
OP1
OP2
Volume Control
amplifier output
signal
RL
To consider the single-supply SE configuration shown in
the Application Circuit, a coupling capacitor is required to
block the DC offset voltage from reaching the load. These
capacitors can be quite large (approximately 33µF to
1000µF) so they tend to be expensive, occupy valuable
PCB area, and have the additional drawback of limiting
low-frequency performance of the system (refer to the
Output Coupling Capacitor).The rules described still hold
with the addition of the following relationship:
need for an output coupling capacitor which is required in
a single supply, SE configuration.
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw15
Figure 2: SE/BTL Input Selection by Readphone Plug
The APA2069 has an internal stereo volume control whose
setting is the function of the DC voltage applied to the
VOLUME input pin. The APA2069 volume control consists
of 32 steps that are individually selected by a variable DC
voltage level on the VOLUME control pin. The range of
the steps, controlled by the DC voltage, are from 20dB
to -80dB. Each gain step corresponds to a specific input
voltage range, as shown in the table. To minimize the
effect of noise on the volume control pin, which can affect
the selected gain level, hysteresis and clock delay are
implemented. The amount of hysteresis corresponds to
half of the step width, as shown in the volume control
graph.
In Figure 2, input SE/BTL operates as below :
When the Readphone plug is inserted, the 1kΩ resistor is
disconnected and the SE/BTL input is pulled high and
enables the SE mode. When the input goes high, the
OUT- amplifier is shutdown which causes the speaker to
mute. The OUT+ amplifier then drives through the output
capacitor (CO) into the headphone jack. When there is no
headphone plugged into the system, the contact pin of
the headphone jack is connnected from the signal pin,
the voltage divider set up by resistors 100kΩ and 1kΩ.
Resistor 1kΩ then pulls low the SE/BTL pin, enabling the
BTL function.
Output SE/BTL Operation (Cont.)
Application Information (Cont.)
Figure 3: Gain Setting vs. DC Volume Pin Voltage
(3)
(2)
Volume Control Function
For the highest accuracy, the voltage shown in the ‘rec-
ommended voltage’ column of the table is used to select
a desired gain. This recommended voltage is exactly half-
way between the two nearest transitions. The gain levels
are 2dB/step from 20dB to -40dB in the BTL mode, and
the last step at -80dB as mute mode.
Input Resistance, Ri
The gain for each audio input of the APA2069 is set by the
internal resistors (Ri and RF) of volume control amplifier
in inverting configuration.
BTL mode operation brings the factor of 2 in the gain
equation due to the inverting amplifier mirroring the volt-
age swing across the load. For varying gain settings, the
APA2069 generates each input resistance on the figure 4.
The input resistance will affect the low frequency perfor-
mance of audio signal. The minmum input resistance is
25kΩ when gain setting is 20dB and the resistance will
ramp up when close loop gain below 20dB. The input
resistance has wide variation (+/-10%) caused by pro-
cess variation.
i
F
VR
R
A Gain SE −==
i
F
R
R
-2Gain BTL ×=
Ring
Headphone Jack
Sleeve
Control
Pin
Tip
1kΩ
VDD
100kΩ
SE/BTL
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DC volume (V)
Gain (dB)
Backward
Forward
APA2069 DC Volume Control Curve (BTL)
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw16
Application Information (Cont.)
Figure 4: Input resistance vs. Gain setting
(4)
(5)
Input Resistance, Ri (Cont.)
(6)
Input Capacitor, Ci
In the typical application, an input capacitor, Ci, is required
to allow the amplifier to bias the input signal to the proper
DC level for optimum operation. In this case, Ci and the
minimum input impedance Ri (25kΩ) form a high-pass
filter with the corner frequency determined in the follow-
ing equation :
The value of Ci is important to consider as it directly af-
fects the low frequency performance of the circuit. Con-
sider the example where Ri is 25kΩ and the specification
calls for a flat bass response down to 50Hz. Equation is
reconfigured as below :
When the input resistance variation is considered, the
value of Ci is 0.13µF, a value in the range 0.22µF to 1.0µF
would be chosen. A further consideration for this capacitor
is the leakage path from the input source through the
input network (Ri+RF, Ci) to the load. This leakage current
creates a DC offset voltage at the input to the amplifier
that reduces useful headroom, especially in high gain
applications. For this reason, a low-leakage tantalum or
ceramic capacitor is the best choice. When polarized ca-
pacitors are used, the positive side of the capacitor should
face the amplifier input in most applications as the DC
level there is held at VDD/2, which is likely higher than the
source DC level. Please note that it is important to con-
firm the capacitor polarity in the application.
Effective Bypass Capacitor, CB
A power amplifier, proper supply bypassing, is critical for
low noise performance and high power supply rejection.
The capacitor location on the BYPASS pin should be as
close to the device as possible. The effect of a larger
supply bypass capacitor is to improve PSRR due to in-
creased half-supply stability. Two critical criteria of by-
pass capacitor (CB): 1st, it depends upon desired PSRR
requirements and click-and-pop performance; 2nd, the
leakage current of CB will induce the voltage drop of VBYPASS
(voltage of BYPASS pin), and if the VBYPASS is less than
0.49VDD, APA2069 will enter mute condition. The value of
VBYPASS can be calculated as below:
Where
ILeakage =Leakage current of CB
Therefore, it is recommended that CB leakage current
should be no more then 0.4µA for properly work of
APA2069.
(7)
To avoid the start-up pop noise, the bypass voltage should
rise slower than the input bias voltage and the relation-
ship shown in equation should be maintained.
The capacitor is fed from a 150kΩ resistor inside of the
amplifier and the 150kΩ is the maximum input resis-
tance of (Ri+RF). Bypass capacitor, CB, values of 2.2µF to
10µF ceramic or tantalum low-ESR capacitors are rec-
ommended for the best THD+N and noise performance.
The bypass capacitance also affects the start up time.
It is determined in the following equation:
(8)
0
20
40
60
80
100
120
140
160
-40 -30 -20 -10 0 10 20
Ri vs. Gain (BTL)
Gain (BTL)
Ri (kΩ)
Ω
<<
ΩX150kC1
)X150k C (1
iB
Ω×= 150k I-0.5VVLeakageDDBYPASS
i
CCk252 1
)highpass(F×Ω×π
=
C
iFk252 1
C×Ω×π
=
)X150k5X(C TB
up start Ω=
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw17
By switching the SHUTDOWN pin to low, the amplifier
enters a low-current state, IDD<1µA. APA2069 is in the
shutdown mode. Under normal operation, SHUTDOWN
pin pull to high level to keep the IC out of the shutdown
mode. The SHUTDOWN pin should be tied to a defi-
nite voltage to avoid unwanted state changing.
In order to reduce power consumption while not in use,
the APA2069 contains a shutdown pin to externally turn
off the amplifier bias circuitry. This shutdown feature
turns the amplifier off when a logic low is placed on the
SHUTDOWN pin. The trigger point between a logic high
and logic low level is typically 2.0V. It is best to switch
between the ground and the supply VDD to provide maxi-
mum device performance.
Application Information (Cont.)
(9)
Output Coupling Capacitor, CO
In the typical single-supply SE configuration, an output
coupling capacitor (CO) is required to block the DC bias at
the output of the amplifier thus preventing DC currents in
the load. As with the input coupling capacitor, the output
coupling capacitor and impedance of the load form a high-
pass filter governed by the following equation:
For example, a 330µF capacitor with an 8Ω speaker would
attenuate low frequencies below 60.6Hz. The main
disadvantage, from a performance standpoint, is the load
impedance is typically small, which drives the low-fre-
quency corner higher degrading the bass response.
Large values of CO are required to pass low frequencies
into the load.
Power Supply Decoupling, CS
The APA2069 is a high-performance CMOS audio ampli-
fier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD+N) is
as low as possible. Power supply decoupling also pre-
vents the oscillations being caused by long lead length
between the amplifier and the speaker. The optimum
decoupling is achieved by using two different types of
capacitors that target on different types of noise on the
power supply leads.
For higher frequency transients, spikes, or digital hash
on the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 0.1µF, is placed as close
as possible to the device VDD lead works the best. For
filtering lower-frequency noise signals, it is recom-
mended to place a large aluminum electrolytic capacitor
of 10µF or greater near the audio power amplifier
Optimizing Depop Circuitry
Circuitry has been included in the APA2069 to minimize the
amount of popping noise at power-up and when coming
out of shutdown mode. Popping occurs whenever a volt-
age step is applied to the speaker. In order to eliminate
clicks and pops, all capacitors must be fully discharged
before turn-on. Rapid on/off switching of the device or
the shutdown function will cause the clicks and pops.
The value of Ci will also affect turn-on pops (Refer to
Effective Bypass Capacitance). The bypass voltage ramp
up should be slower than input bias voltage. Although the
bypass pin current source cannot be modified, the size of
CB can be changed to alter the device turn-on time and the
amount of clicks and pops. By increasing the value of CB
, turn-on pop can be reduced. However, the tradeoff for
using a larger bypass capacitor is to increase the turn-on
time for this device. There is a linear relationship be-
tween the size of CB and the turn-on time. In a SE
configuration, the output coupling capacitor, CO, is of par-
ticular concern.
This capacitor discharges through the internal 10kΩ
resistors. Depending on the size of CO, the time constant
can be relatively large. To reduce transients in the SE
mode, an external 1kΩ resistor can be placed in parallel
with the internal 10kΩ resistor. The tradeoff for using this
resistor is an increase in quiescent current. In most
cases, choosing a small value of Ci in the range of
0.33µF to 1µF, CB being equal to 4.7µF and an external
1kΩ resistor should be placed in parallel with the inter-
nal 10kΩ resistor should produce a virtually clickless
and popless turn-on.
Shutdown Function
A high gain amplifier intensifies the problem as the small
delta in voltage is multiplied by the gain, therefore, it is
advantageous to use low-gain configurations.
OL
CCR21
)highpass(Fπ
=
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw18
Application Information (Cont.)
(10)
(11)
(12)
(13)
BTL Amplifier Efficiency
An easy-to-use equation to calculate efficiency starts out
as being equal to the ratio of power from the power sup-
ply to the power delivered to the load.
The following equations are the basis for calculating
amplifier efficiency.
Where
Efficiency of a BTL configuration :
Table 1 calculates efficiencies for four different output
power levels.
Note that the efficiency of the amplifier is quite low for
lower power levels and rises sharply as power to the load
is increased resulting in a nearly flat internal power dissi-
pation over the normal operating range. Note that the in-
ternal dissipation at full output power is less than the
dissipation in the half power range. Calculating the effi-
ciency for a specific system is the key to proper power
supply design. For a stereo 1W audio system with 8Ω
loads and a 5V supply, the maximum draw on the power
supply is almost 3W.
A final point to remember about linear amplifiers (either
SE or BTL) is how to manipulate the terms in the effi-
ciency equation to the utmost advantage when possible.
Note that in equation, VDD is in the denominator. This indi-
cates that as VDD goes down, efficiency goes up. In other
words, use the efficiency analysis to choose the correct
supply voltage and speaker impedance for the application.
PO (W)
Efficiency (%)
IDD (A)
VPP(V)
PD (W)
0.25 31.25 0.16 2.00
0.55
0.50 47.62 0.21 2.83
0.55
1.00 66.67 0.30 4.00
0.5
1.25 78.13 0.32 4.47
0.35
**High peak voltages cause the THD+N to increase.
Power Dissipation
Whether the power amplifier is operated in BTL or SE
mode, power dissipation is the major concern. Equa-
tion14 states the maximum power dissipation point for a
SE mode operating at a given supply voltage and driving
a specified load.
(14)
In BTL mode operation, the output voltage swing is
doubled as in SE mode. Thus, the maximum power dis-
sipation point for a BTL mode operating at the same given
conditions is 4 times as in SE mode.
SUP
O
P
P
Efficiency =
L
PP
L
ormsorms
OR2)VV(
RVV
P×
=
×
=
2
V
VP
orms =
L
P
DDDDAVGDDSUP R
V2
VlVP π
×=×=
DD
P
L
P
DD
L
PP
SUP
O4V
V
)
R
V2
V(
)
R2VV
(
P
Pπ
=
π
×
×
=
Table 1. Efficiency vs. Output Power in 5-V/8Ω BTL Sys-
tems
L
2
2
DD
MAXD, R2V
=P : mode SE π
(15)
Since the APA2069 is a dual channel power amplifier, the
maximum internal power dissipation is 2 times that both
of equations depend on the mode of operation. Even with
this substantial increase in power dissipation, the
APA2069 does not require extra heatsink. The power dis-
sipation from equation14, assuming a 5V-power supply
and an 8Ω load, must not be greater than the power dis-
sipation that results from the equation16:
L
2
2
DD
MAXD, R2
4V
=P : mode BTL π
(16)
For DIP16-A package with thermal pad, the thermal resis-
tance (θJA) is equal to 45οC/W.
JA
AMAXJ,
MAXD, T-T
Pθ
=
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw19
Application Information (Cont.)
Power Dissipation (Cont.)
Since the maximum junction temperature (TJ,MAX) of
APA2069 is 150οC and the ambient temperature (TA) is
defined by the power system design, the maximum power
dissipation which the IC package is able to handle can be
obtained from equation16.
Once the power dissipation is greater than the maximum
limit (PD,MAX), either the supply voltage (VDD) must be
decreased, the load impedance (RL) must be increased
or the ambient temperature should be reduced.
Thermal Consideration
Linear power amplifiers dissipate a significant amount of
heat in the package under normal operating conditions.
To calculate maximum ambient temperatures, first con-
sideration is that the numbers from the Power Dissipa-
tion vs. Output Power graphs are per channel values,
therefore, the dissipation of the IC heat needs to be
doubled for two-channel operation. Given θJA, the maxi-
mum allowable junction temperature (TJMAX), and the to-
tal internal dissipation (PD), the maximum ambient tem-
perature can be calculated with the following equation.
The maximum recommended junction temperature for
the APA2069 is 150°C. The internal dissipation figures
are taken from the Power Dissipation vs. Output Power
graphs.
TAMax = TJMax -θJAPD (16)
150 - 45(0.8*2) = 78°C
The APA2069 is designed with a thermal shutdown pro-
tection that turns the device off when the junction tem-
perature surpasses 150°C to prevent damaging the IC.
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
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Package Information
DIP-16
Note : 1. Followed from JEDEC MS-001AB
2. Dimension D, D1 and E1 do not include mold flash or
protrusions. Mold flash or protrusions shall not exceed
10 mil.
S
Y
M
B
O
LMIN. MAX.
5.33
0.38
0.36 0.56
1.14 1.78
0.20 0.35
18.6 20.31
0.13
2.92 3.81
A
A1
b
b2
c
D
D1
E
E1
e
eA
MILLIMETERS
A2 2.92 4.95
2.54 BSC
DIP-16
7.62 8.26
6.10 7.11
eB
L
10.92
7.62 BSC
MIN. MAX.
INCHES
0.210
0.015
0.100 BSC
0.300 BSC
0.115 0.195
0.014 0.022
0.045 0.070
0.008 0.014
0.732 0.800
0.005
0.300 0.325
0.240 0.280
0.430
0.115 0.150
D
E1
0.38
ceA
eB
E
A2
A1
AL
b b2 e
D1
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw21
DIP-16A
Package Information
D1 b2b e
A2
A
A1
L
eB
eA
c
E
0.38
S
Y
M
B
O
LMIN. MAX.
5.33
0.38
0.36 0.56
1.14 1.78
0.20 0.35
18.6 20.31
0.13
2.92 3.81
A
A1
b
b2
c
D
D1
E
E1
e
eA
MILLIMETERS
A2 2.92 4.95
2.54 BSC
DIP-16A
7.62 8.26
6.10 7.11
eB
L10.92
7.62 BSC
MIN. MAX.
INCHES
0.210
0.015
0.100 BSC
0.300 BSC
0.115 0.195
0.014 0.022
0.045 0.070
0.008 0.014
0.732 0.800
0.005
0.300 0.325
0.240 0.280
0.430
0.115 0.150
Note : 1. Followed from JEDEC MS-001AB
2. Dimension D, D1 and E1 do not include mold flash or
protrusions. Mold flash or protrusions shall not exceed
10 mil.
D
E1
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw22
Classification Profile
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Reflow Profiles
Copyright ANPEC Electronics Corp.
Rev. A.9 - Jul., 2011
APA2069
www.anpec.com.tw23
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Reliability Test Program
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
